Uwe Hermann
14 years ago
2 changed files with 256 additions and 0 deletions
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/*
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* This file is part of the libopenstm32 project. |
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* |
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* Copyright (C) 2010 Gareth McMullin <gareth@blacksphere.co.nz> |
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* |
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* This program is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#ifndef LIBOPENSTM32_ETHERNET_H |
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#define LIBOPENSTM32_ETHERNET_H |
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#include <libopenstm32/memorymap.h> |
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#include <libopenstm32/common.h> |
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/* Ethernet MAC registers */ |
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#define ETH_MACCR MMIO32(ETHERNET_BASE + 0x00) |
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#define ETH_MACFFR MMIO32(ETHERNET_BASE + 0x04) |
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#define ETH_MACHTHR MMIO32(ETHERNET_BASE + 0x08) |
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#define ETH_MACHTLR MMIO32(ETHERNET_BASE + 0x0C) |
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#define ETH_MACMIIAR MMIO32(ETHERNET_BASE + 0x10) |
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#define ETH_MACMIIDR MMIO32(ETHERNET_BASE + 0x14) |
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#define ETH_MACFCR MMIO32(ETHERNET_BASE + 0x18) |
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#define ETH_MACVLANTR MMIO32(ETHERNET_BASE + 0x1C) |
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#define ETH_MACRWUFFR MMIO32(ETHERNET_BASE + 0x28) |
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#define ETH_MACPMTCSR MMIO32(ETHERNET_BASE + 0x2C) |
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#define ETH_MACSR MMIO32(ETHERNET_BASE + 0x38) |
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#define ETH_MACIMR MMIO32(ETHERNET_BASE + 0x3C) |
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#define ETH_MACA0HR MMIO32(ETHERNET_BASE + 0x40) |
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#define ETH_MACA0LR MMIO32(ETHERNET_BASE + 0x44) |
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#define ETH_MACA1HR MMIO32(ETHERNET_BASE + 0x48) |
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#define ETH_MACA1LR MMIO32(ETHERNET_BASE + 0x4C) |
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#define ETH_MACA2HR MMIO32(ETHERNET_BASE + 0x50) |
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#define ETH_MACA2LR MMIO32(ETHERNET_BASE + 0x54) |
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#define ETH_MACA3HR MMIO32(ETHERNET_BASE + 0x58) |
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#define ETH_MACA3LR MMIO32(ETHERNET_BASE + 0x5C) |
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/* Ethernet MMC registers */ |
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#define ETH_MMCCR MMIO32(ETHERNET_BASE + 0x100) |
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#define ETH_MMCRIR MMIO32(ETHERNET_BASE + 0x104) |
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#define ETH_MMCTIR MMIO32(ETHERNET_BASE + 0x108) |
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#define ETH_MMCRIMR MMIO32(ETHERNET_BASE + 0x10C) |
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#define ETH_MMCTIMR MMIO32(ETHERNET_BASE + 0x110) |
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#define ETH_MMCTGFSCCR MMIO32(ETHERNET_BASE + 0x14C) |
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#define ETH_MMCTGFMSCCR MMIO32(ETHERNET_BASE + 0x150) |
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#define ETH_MMCTGFCR MMIO32(ETHERNET_BASE + 0x168) |
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#define ETH_MMCRFCECR MMIO32(ETHERNET_BASE + 0x194) |
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#define ETH_MMCRFAECR MMIO32(ETHERNET_BASE + 0x198) |
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#define ETH_MMCRGUFCR MMIO32(ETHERNET_BASE + 0x1C4) |
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/* Ethrenet IEEE 1588 time stamp registers */ |
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#define ETH_PTPTSCR MMIO32(ETHERNET_BASE + 0x700) |
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#define ETH_PTPSSIR MMIO32(ETHERNET_BASE + 0x704) |
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#define ETH_PTPTSHR MMIO32(ETHERNET_BASE + 0x708) |
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#define ETH_PTPTSLR MMIO32(ETHERNET_BASE + 0x70C) |
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#define ETH_PTPTSHUR MMIO32(ETHERNET_BASE + 0x710) |
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#define ETH_PTPTSLUR MMIO32(ETHERNET_BASE + 0x714) |
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#define ETH_PTPTSAR MMIO32(ETHERNET_BASE + 0x718) |
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#define ETH_PTPTTHR MMIO32(ETHERNET_BASE + 0x71C) |
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#define ETH_PTPTTLR MMIO32(ETHERNET_BASE + 0x720) |
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/* Ethernet DMA registers */ |
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#define ETH_DMABMR MMIO32(ETHERNET_BASE + 0x1000) |
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#define ETH_DMATPDR MMIO32(ETHERNET_BASE + 0x1004) |
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#define ETH_DMARPDR MMIO32(ETHERNET_BASE + 0x1008) |
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#define ETH_DMARDLAR MMIO32(ETHERNET_BASE + 0x100C) |
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#define ETH_DMATDLAR MMIO32(ETHERNET_BASE + 0x1010) |
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#define ETH_DMATDLAR MMIO32(ETHERNET_BASE + 0x1010) |
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#define ETH_DMASR MMIO32(ETHERNET_BASE + 0x1014) |
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#define ETH_DMAOMR MMIO32(ETHERNET_BASE + 0x1018) |
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#define ETH_DMAIER MMIO32(ETHERNET_BASE + 0x101C) |
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#define ETH_DMAMFBOCR MMIO32(ETHERNET_BASE + 0x1020) |
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#define ETH_DMACHTDR MMIO32(ETHERNET_BASE + 0x1048) |
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#define ETH_DMACHRDR MMIO32(ETHERNET_BASE + 0x104C) |
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#define ETH_DMACHTBAR MMIO32(ETHERNET_BASE + 0x1050) |
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#define ETH_DMACHRBAR MMIO32(ETHERNET_BASE + 0x1054) |
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/* Ethernet MAC Register bit definitions */ |
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/* Ethernet MAC configuration register ETH_MACCR bits */ |
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#define ETH_MACCR_RE 0x00000004 |
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#define ETH_MACCR_TE 0x00000008 |
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#define ETH_MACCR_DC 0x00000010 |
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#define ETH_MACCR_BL 0x00000060 |
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#define ETH_MACCR_APCS 0x00000080 |
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#define ETH_MACCR_RD 0x00000200 |
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#define ETH_MACCR_IPCO 0x00000400 |
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#define ETH_MACCR_DM 0x00000800 |
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#define ETH_MACCR_LM 0x00001000 |
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#define ETH_MACCR_ROD 0x00002000 |
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#define ETH_MACCR_FES 0x00004000 |
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#define ETH_MACCR_CSD 0x00010000 |
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#define ETH_MACCR_IFG 0x000E0000 |
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#define ETH_MACCR_JD 0x00400000 |
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#define ETH_MACCR_WD 0x00800000 |
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/* Ethernet MAC frame filter register ETH_MACFFR bits */ |
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#define ETH_MACFFR_PM 0x00000001 |
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#define ETH_MACFFR_HU 0x00000002 |
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#define ETH_MACFFR_HM 0x00000004 |
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#define ETH_MACFFR_DAIF 0x00000008 |
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#define ETH_MACFFR_PAM 0x00000010 |
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#define ETH_MACFFR_BFD 0x00000020 |
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#define ETH_MACFFR_PCF 0x000000C0 |
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#define ETH_MACFFR_SAIF 0x00000100 |
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#define ETH_MACFFR_SAF 0x00000200 |
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#define ETH_MACFFR_HPF 0x00000400 |
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#define ETH_MACFFR_PA 0x80000000 |
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/* Ethernet MAC MII address register ETH_MACMIIAR bits */ |
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#define ETH_MACMIIAR_MB 0x0001 |
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#define ETH_MACMIIAR_MW 0x0002 |
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/* Clock Range for MDC frequency */ |
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#define ETH_MACMIIAR_CR_MASK 0x001C |
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#define ETH_MACMIIAR_CR_HCLK_DIV_42 0x0000 /* For HCLK 60-72 MHz */ |
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#define ETH_MACMIIAR_CR_HCLK_DIV_16 0x0008 /* For HCLK 20-35 MHz */ |
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#define ETH_MACMIIAR_CR_HCLK_DIV_24 0x000C /* For HCLK 35-60 MHz */ |
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#define ETH_MACMIIAR_MR 0x07C0 |
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#define ETH_MACMIIAR_PA 0xF800 |
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/* Ethernet MAC flow control register ETH_MACFCR bits */ |
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#define ETH_MACFCR_FCB 0x00000001 |
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#define ETH_MACFCR_BPA 0x00000001 |
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#define ETH_MACFCR_TFCE 0x00000002 |
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#define ETH_MACFCR_RFCE 0x00000004 |
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#define ETH_MACFCR_UPFD 0x00000008 |
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#define ETH_MACFCR_PLT 0x00000030 |
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#define ETH_MACFCR_ZQPD 0x00000080 |
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#define ETH_MACFCR_PT 0xFFFF0000 |
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/* Ethernet MAC interrupt status regster ETH_MACSR bits */ |
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#define ETH_MACSR_PMTS 0x0008 |
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#define ETH_MACSR_MMCS 0x0010 |
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#define ETH_MACSR_MMCRS 0x0020 |
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#define ETH_MACSR_MMCTS 0x0040 |
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#define ETH_MACSR_TSTS 0x0200 |
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/* Ethernet MAC interrupt mask regster ETH_MACIMR bits */ |
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#define ETH_MACIMR_PMTIM 0x0008 |
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#define ETH_MACIMR_TSTIM 0x0200 |
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/* Ethernet DMA Register bit definitions */ |
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/* Ethernet DMA bus mode register ETH_DMABMR bits */ |
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#define ETH_DMABMR_SR 0x00000001 |
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#define ETH_DMABMR_DA 0x00000002 |
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#define ETH_DMABMR_DSL_MASK 0x0000007C |
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#define ETH_DMABMR_PBL_MASK 0x00003F00 |
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#define ETH_DMABMR_RTPR_MASK 0x0000C000 |
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#define ETH_DMABMR_RTPR_1TO1 0x00000000 |
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#define ETH_DMABMR_RTPR_2TO1 0x00004000 |
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#define ETH_DMABMR_RTPR_3TO1 0x00008000 |
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#define ETH_DMABMR_RTPR_4TO1 0x0000C000 |
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#define ETH_DMABMR_FB 0x00010000 |
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#define ETH_DMABMR_RDP_MASK 0x007E0000 |
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#define ETH_DMABMR_USP 0x00800000 |
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#define ETH_DMABMR_FPM 0x01000000 |
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#define ETH_DMABMR_AAB 0x02000000 |
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/* Ethernet DMA operation mode register ETH_DMAOMR bits */ |
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#define ETH_DMAOMR_SR 0x00000002 |
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#define ETH_DMAOMR_OSF 0x00000004 |
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#define ETH_DMAOMR_RTC_MASK 0x00000018 |
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#define ETH_DMAOMR_RTC_64 0x00000000 |
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#define ETH_DMAOMR_RTC_32 0x00000008 |
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#define ETH_DMAOMR_RTC_96 0x00000010 |
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#define ETH_DMAOMR_RTC_128 0x00000018 |
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#define ETH_DMAOMR_FUGF 0x00000040 |
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#define ETH_DMAOMR_FEF 0x00000080 |
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#define ETH_DMAOMR_ST 0x00002000 |
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#define ETH_DMAOMR_TTC_MASK 0x0001C000 |
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#define ETH_DMAOMR_FTF 0x00100000 |
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#define ETH_DMAOMR_TSF 0x00200000 |
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#define ETH_DMAOMR_DFRF 0x01000000 |
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#define ETH_DMAOMR_RSF 0x02000000 |
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#define ETH_DMAOMR_DTCEFD 0x04000000 |
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/* Ethernet DMA interrupt enable register ETH_DMAIER bits */ |
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#define ETH_DMAIER_TIE 0x00000001 |
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#define ETH_DMAIER_TPSIE 0x00000002 |
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#define ETH_DMAIER_TBUIE 0x00000004 |
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#define ETH_DMAIER_TJTIE 0x00000008 |
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#define ETH_DMAIER_ROIE 0x00000010 |
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#define ETH_DMAIER_TUIE 0x00000020 |
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#define ETH_DMAIER_RIE 0x00000040 |
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#define ETH_DMAIER_RBUIE 0x00000080 |
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#define ETH_DMAIER_RPSIE 0x00000100 |
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#define ETH_DMAIER_RWTIE 0x00000200 |
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#define ETH_DMAIER_ETIE 0x00000400 |
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#define ETH_DMAIER_FBEIE 0x00002000 |
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#define ETH_DMAIER_ERIE 0x00004000 |
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#define ETH_DMAIER_AISE 0x00008000 |
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#define ETH_DMAIER_NSIE 0x00010000 |
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#endif |
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@ -0,0 +1,53 @@ |
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/*
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* This file is part of the libopenstm32 project. |
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* |
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* Copyright (C) 2010 Gareth McMullin <gareth@blacksphere.co.nz> |
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* |
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* This program is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#include <libopenstm32/ethernet.h> |
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void eth_smi_write(u8 phy, u8 reg, u16 data) |
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{ |
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/* Set PHY and register addresses for write access. */ |
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*ETH_MACMIIAR &= ~(ETH_MACMIIAR_MR | ETH_MACMIIAR_PA); |
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*ETH_MACMIIAR |= (phy << 11) | (reg << 6) | ETH_MACMIIAR_MW; |
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/* Set register value. */ |
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*ETH_MACMIIDR = data; |
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/* Begin transaction. */ |
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*ETH_MACMIIAR |= ETH_MACMIIAR_MB; |
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/* Wait for not busy. */ |
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while (*ETH_MACMIIAR & ETH_MACMIIAR_MB); |
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} |
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u16 eth_smi_read(u8 phy, u8 reg) |
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{ |
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/* Set PHY and register addresses for write access. */ |
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*ETH_MACMIIAR &= ~(ETH_MACMIIAR_MR | ETH_MACMIIAR_PA | |
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ETH_MACMIAR_MW); |
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*ETH_MACMIIAR |= (phy << 11) | (reg << 6); |
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/* Begin transaction. */ |
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*ETH_MACMIIAR |= ETH_MACMIIAR_MB; |
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/* Wait for not busy. */ |
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while (*ETH_MACMIIAR & ETH_MACMIIAR_MB); |
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/* Set register value. */ |
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return (u16)(*ETH_MACMIIDR); |
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} |
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