Added rcc clock setup function for 16mhz crystal.

include/libopenstm32/rcc.h

@@ -400,5 +400,6 @@ void rcc_set_hpre(u32 hpre);
 u32 rcc_get_system_clock_source(int i);
 void rcc_clock_setup_in_hsi_out_64mhz(void);
 void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
+void rcc_clock_setup_in_hse_16mhz_out_72mhz(void);
 
 #endif

lib/rcc.c

@@ -424,3 +424,44 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
 	/* Select PLL as SYSCLK source. */
 	rcc_set_sysclk_source(SW_SYSCLKSEL_PLLCLK);
 }
+
+void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
+{
+        /* enable Internal High Speed Oscillator */
+        rcc_osc_on(HSI);
+        rcc_wait_for_osc_ready(HSI);
+
+        /* Select HSI as SYSCLK source. */
+        rcc_set_sysclk_source(SW_SYSCLKSEL_HSICLK);
+
+        /* enable External High Speed Oscillator 16MHz */
+        rcc_osc_on(HSE);
+        rcc_wait_for_osc_ready(HSE);
+        rcc_set_sysclk_source(SW_SYSCLKSEL_HSECLK);
+
+        /* set prescalers for ADC, ABP1, ABP2...  make this before touching the PLL */
+        rcc_set_hpre(HPRE_SYSCLK_NODIV); //prescales the AHB clock from the SYSCLK
+        rcc_set_adcpre(ADCPRE_PLCK2_DIV6); //prescales the ADC from the APB2 clock; max 14MHz
+        rcc_set_ppre1(PPRE1_HCLK_DIV2); //prescales the APB1 from the AHB clock; max 36MHz
+        rcc_set_ppre2(PPRE2_HCLK_NODIV); //prescales the APB2 from the AHB clock; max 72MHz
+
+        /* sysclk should run with 72MHz -> 2 Waitstates ; choose 0WS from 0-24MHz, 1WS from 24-48MHz, 2WS from 48-72MHz */
+        flash_set_ws(FLASH_LATENCY_2WS);
+
+        /* Set the PLL multiplication factor to 9. -> 16MHz (external) * 9 (multiplier) / 2 (PLLXTPRE_HSE_CLK_DIV2) = 72MHz */
+        rcc_set_pll_multiplication_factor(PLLMUL_PLL_CLK_MUL9);
+
+        /* Select HSI as PLL source. */
+        rcc_set_pll_source(PLLSRC_HSE_CLK);
+
+        /* divide external frequency by 2 before entering pll (only valid/needed for HSE) */
+        rcc_set_pllxtpre(PLLXTPRE_HSE_CLK_DIV2);
+
+        /* Enable PLL oscillator and wait for it to stabilize. */
+        rcc_osc_on(PLL);
+        rcc_wait_for_osc_ready(PLL);
+
+        /* Select PLL as SYSCLK source. */
+        rcc_set_sysclk_source(SW_SYSCLKSEL_PLLCLK);
+}
+