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Updates to a base set of includes to map to the h7 include files which are mainly based on the f7 versions for simple devices (e.g. SPI, USART, GPIO). Custom files that have been implemented from the datasheet/ref manual include the memory map, RCC, PWR definitions, and irq.json file for generation of nvic files for interrupt mapping. Additional functionality, especially PLL and tweaks for non-F7 compatible implementations coming in future commits. Added documentation tree configuration. Reviewed-by: Karl Palsson <karlp@tweak.net.au> Changed dmaX_streamX to dmaX_strX in a few places for consistencypull/1142/head
Brian Viele
5 years ago
committed by
Karl Palsson
Karl Palsson
30 changed files with 1276 additions and 1 deletions
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PREDEFINED += __ARM_ARCH_7EM__ |
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/** @defgroup dac_defines DAC Defines
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@brief <b>Defined Constants and Types for the STM32H7xx DAC</b> |
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@ingroup STM32H7xx_defines |
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@version 1.0.0 |
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@date 6 November 2019 |
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LGPL License Terms @ref lgpl_license |
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*/ |
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/*
|
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* This file is part of the libopencm3 project. |
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* |
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* This library is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU Lesser General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* This library is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public License |
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#ifndef LIBOPENCM3_DAC_H |
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#define LIBOPENCM3_DAC_H |
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#include <libopencm3/stm32/common/dac_common_all.h> |
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#endif |
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/** @defgroup flash_defines FLASH Defines
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* |
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* @ingroup STM32H7xx_defines |
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* |
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* @author @htmlonly © @endhtmlonly 2019 |
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* Brian Viele <vielster@allocor.tech> |
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* |
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*/ |
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/*
|
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* This file is part of the libopencm3 project. |
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* |
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* This library is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU Lesser General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* This library is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public License |
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#ifndef LIBOPENCM3_FLASH_H |
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#define LIBOPENCM3_FLASH_H |
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#include <libopencm3/stm32/common/flash_common_all.h> |
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#include <libopencm3/stm32/common/flash_common_f.h> |
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#include <libopencm3/stm32/common/flash_common_f24.h> |
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/**@{*/ |
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/** @addtogroup flash_acr_values FLASH_ACR_VALUES
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* @ingroup flash_registers |
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@{*/ |
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#define FLASH_ACR_WRHF_VOS1_70MHZ (0 << FLASH_ACR_WRHIGHFREQ_SHIFT) |
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#define FLASH_ACR_WRHF_VOS1_185MHZ (1 << FLASH_ACR_WRHIGHFREQ_SHIFT) |
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#define FLASH_ACR_WRHF_VOS1_225MHZ (2 << FLASH_ACR_WRHIGHFREQ_SHIFT) |
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#define FLASH_ACR_WRHF_VOS2_55MHZ (0 << FLASH_ACR_WRHIGHFREQ_SHIFT) |
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#define FLASH_ACR_WRHF_VOS2_165MHZ (1 << FLASH_ACR_WRHIGHFREQ_SHIFT) |
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#define FLASH_ACR_WRHF_VOS2_225MHZ (2 << FLASH_ACR_WRHIGHFREQ_SHIFT) |
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#define FLASH_ACR_WRHF_VOS3_45MHZ (0 << FLASH_ACR_WRHIGHFREQ_SHIFT) |
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#define FLASH_ACR_WRHF_VOS3_135MHZ (1 << FLASH_ACR_WRHIGHFREQ_SHIFT) |
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#define FLASH_ACR_WRHF_VOS3_225MHZ (2 << FLASH_ACR_WRHIGHFREQ_SHIFT) |
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/*@}*/ |
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#define FLASH_ACR_WRHIGHFREQ_MASK (0x3) |
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#define FLASH_ACR_WRHIGHFREQ_SHIFT (0x4) |
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/**@}*/ |
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#endif |
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/** @defgroup fmc_defines FMC Defines
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* @brief <b>Defined Constants and Types for the STM32H7xx Flexible Memory |
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* Controller</b> |
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* @ingroup STM32H7xx_defines |
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*/ |
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/*
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* This file is part of the libopencm3 project. |
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* |
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* This library is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU Lesser General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* This library is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public License |
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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/**@{*/ |
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#ifndef LIBOPENCM3_H7_FMC_H |
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#define LIBOPENCM3_H7_FMC_H |
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#ifndef LIBOPENCM3_FSMC_H |
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#error "This file should not be included directly, it is included with fsmc.h" |
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#endif |
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#include <libopencm3/stm32/common/fmc_common_f47.h> |
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/* --- Convenience macros -------------------------------------------------- */ |
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#define FSMC_BASE FMC_BASE |
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#endif |
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/**@}*/ |
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/** @defgroup gpio_defines GPIO Defines
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@brief <b>Defined Constants and Types for the STM32H7xx General Purpose I/O</b> |
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@ingroup STM32H7xx_defines |
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@version 1.0.0 |
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@date 6 November 2019 |
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|
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LGPL License Terms @ref lgpl_license |
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*/ |
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/*
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* This file is part of the libopencm3 project. |
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* |
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* This library is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU Lesser General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* This library is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public License |
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#ifndef LIBOPENCM3_GPIO_H |
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#define LIBOPENCM3_GPIO_H |
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#include <libopencm3/stm32/common/gpio_common_f24.h> |
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#endif |
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{ |
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"irqs": [ |
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"wwdg", |
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"pvd", |
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"tamp_stamp", |
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"rtc_wkup", |
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"flash", |
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"rcc", |
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"exti0", |
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"exti1", |
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"exti2", |
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"exti3", |
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"exti4", |
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"dma1_str0", |
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"dma1_str1", |
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"dma1_str2", |
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"dma1_str3", |
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"dma1_str4", |
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"dma1_str5", |
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"dma1_str6", |
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"adc1_2", |
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"fdcan1_it0", |
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"fdcan2_it0", |
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"fdcan1_it1", |
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"fdcan2_it2", |
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"exti9_5", |
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"tim1_brk_tim9", |
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"tim1_up_tim10", |
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"tim1_trg_com_tim11", |
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"tim1_cc", |
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"tim2", |
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"tim3", |
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"tim4", |
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"i2c1_ev", |
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"i2c1_er", |
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"i2c2_ev", |
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"i2c2_er", |
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"spi1", |
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"spi2", |
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"usart1", |
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"usart2", |
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"usart3", |
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"exti15_10", |
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"rtc_alarm", |
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"reserved1", |
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"tim8_brk_tim12", |
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"tim8_up_tim13", |
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"tim8_trg_com_tim14", |
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"tim8_cc", |
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"dma1_str7", |
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"fsmc", |
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"sdmmc1", |
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"tim5", |
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"spi3", |
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"uart4", |
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"uart5", |
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"tim6_dac", |
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"tim7", |
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"dma2_str0", |
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"dma2_str1", |
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"dma2_str2", |
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"dma2_str3", |
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"dma2_str4", |
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"eth", |
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"eth_wkup", |
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"fdcan_cal", |
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"cm7_sev", |
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"reserved2", |
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"reserved3", |
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"reserved4", |
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"dma2_str5", |
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"dma2_str6", |
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"dma2_str7", |
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"usart6", |
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"i2c3_ev", |
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"i2c3_er", |
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"otg_hs_ep1_out", |
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"otg_hs_ep1_in", |
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"otg_hs_wkup", |
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"otg_hs", |
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"dcmi", |
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"cryp", |
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"hash_rng", |
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"fpu", |
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"uart7", |
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"uart8", |
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"spi4", |
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"spi5", |
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"spi6", |
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"sai1", |
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"ltdc", |
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"ltdc_er", |
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"dma2d", |
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"sai2", |
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"quadspi", |
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"lp_tim1", |
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"cec", |
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"i2c4_ev", |
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"i2c4_er", |
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"spdifrx", |
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"otg_fs_ep1_out", |
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"otg_fs_ep1_in", |
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"otg_fs_wkup", |
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"otg_fs", |
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"dmamux1_ov", |
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"hrtim1_mst", |
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"hrtim1_tima", |
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"hrtim1_timb", |
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"hrtim1_timc", |
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"hrtim1_timd", |
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"hrtim1_time", |
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"hrtim1_flt", |
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"dfsdm1_it0", |
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"dfsdm1_it1", |
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"dfsdm1_it2", |
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"dfsdm1_it3", |
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"sai3", |
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"swpmi1", |
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"tim15", |
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"tim16", |
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"tim17", |
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"mdios_wkup", |
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"mdios", |
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"jpeg", |
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"mdma", |
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"reserved5", |
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"sdmmc2", |
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"hsem0", |
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"reserved6", |
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"adc3", |
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"dmamux2_ovr", |
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"bdma_ch0", |
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"bdma_ch1", |
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"bdma_ch2", |
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"bdma_ch3", |
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"bdma_ch4", |
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"bdma_ch5", |
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"bdma_ch6", |
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"bdma_ch7", |
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"comp", |
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"lptim2", |
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"lptim3", |
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"lptim4", |
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"lptim5", |
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"lpuart", |
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"wwdg1_rst", |
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"crs", |
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"ramecc1", |
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"sai4", |
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"reserved7", |
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"reserved8", |
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"wkup" |
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], |
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"partname_humanreadable": "STM32 H7 series", |
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"partname_doxygen": "STM32H7", |
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"includeguard": "LIBOPENCM3_STM32_H7_NVIC_H" |
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} |
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@ -0,0 +1,157 @@ |
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/*
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* This file is part of the libopencm3 project. |
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* |
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* This library is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU Lesser General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* This library is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public License |
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#ifndef LIBOPENCM3_MEMORYMAP_H |
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#define LIBOPENCM3_MEMORYMAP_H |
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#include <libopencm3/cm3/memorymap.h> |
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/* --- STM32H7 specific peripheral definitions ----------------------------- */ |
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/* Memory map for all busses */ |
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#define PERIPH_BASE 0x40000000U |
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#define PERIPH_BASE_APB1 0x40000000U |
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#define PERIPH_BASE_APB2 0x40010000U |
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#define PERIPH_BASE_APB3 0x50000000U |
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#define PERIPH_BASE_AHB1 0x40020000U |
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#define PERIPH_BASE_AHB2 0x48020000U |
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#define PERIPH_BASE_AHB3 0x51000000U |
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#define PERIPH_BASE_AHB4 0x58000000U |
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/* Table 8: Register boundary addresses */ |
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/* AHB4 Peripherals */ |
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#define GPIO_PORT_A_BASE 0x58020000U |
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#define GPIO_PORT_B_BASE 0x58020400U |
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#define GPIO_PORT_C_BASE 0x58020800U |
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#define GPIO_PORT_D_BASE 0x58020C00U |
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#define GPIO_PORT_E_BASE 0x58021000U |
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#define GPIO_PORT_F_BASE 0x58021400U |
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#define GPIO_PORT_G_BASE 0x58021800U |
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#define GPIO_PORT_H_BASE 0x58021C00U |
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#define GPIO_PORT_I_BASE 0x58022000U |
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#define GPIO_PORT_J_BASE 0x58022400U |
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#define GPIO_PORT_K_BASE 0x58022800U |
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#define RCC_BASE 0x58024400U |
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#define POWER_CONTROL_BASE 0x58024800U |
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#define CRC_BASE 0x58024C00U |
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#define BDMA_BASE 0x58025400U |
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#define DMAMUX2_BASE 0x58025800U |
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#define ADC3_BASE 0x58026000U |
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#define HSEM_BASE 0x58026400U |
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/* APB4 Peripherals */ |
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#define SAI4_BASE 0x58005400U |
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#define IWDG1_BASE 0x58004800U |
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#define RTC_BASE 0x58004000U |
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#define VREF_BASE 0x58003C00U |
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#define COMP1_BASE 0x58003800U |
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#define LPTIM5_BASE 0x58003000U |
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#define LPTIM4_BASE 0x58002C00U |
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#define LPTIM3_BASE 0x58002800U |
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#define LPTIM2_BASE 0x58002400U |
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#define I2C4_BASE 0x58001C00U |
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#define SPI6_BASE 0x58001400U |
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#define LPUART1_BASE 0x58000C00U |
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#define SYSCFG_BASE 0x58000400U |
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#define EXTI_BASE 0x58000000U |
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/* AHB3 Peripherals */ |
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#define DELAY_SDMMC1_BASE 0x52008000U |
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#define SDMMC1_BASE 0x52007000U |
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#define DELAY_QSPI_BASE 0x52006000U |
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#define QUADSPI_BASE 0x52005000U |
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#define FMC_BASE 0x52004000U |
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#define JPEG_BASE 0x52003000U |
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#define FLASH_MEM_INTERFACE_BASE 0x52002000U |
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#define CHROMART_BASE 0x52001000U |
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#define MDMA_BASE 0x52000000U |
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#define GPV_BASE 0x51000000U |
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|
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/* APB3 Peripherals */ |
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#define WWDG1_BASE 0x50003000U |
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#define LTDC_BASE 0x50001000U |
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/* AHB2 Peripherals */ |
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#define DELAY_SDMMC2_BASE 0x48022800U |
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#define SDMMC2_BASE 0x48022400U |
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#define RNG_BASE 0x48021800U |
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#define HASH_BASE 0x48021400U |
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#define CRYPTO_BASE 0x48021000U |
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#define DCMI_BASE 0x48020000U |
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|
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/* AHB1 Peripherals */ |
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#define USB2_OTG_FS_BASE 0x40080000U |
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#define USB1_OTG_HS_BASE 0x40040000U |
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#define ETHERNET_MAC_BASE 0x40028000U |
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#define ADC1_ADC2_BASE 0x40022000U |
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#define DMAMUX1_BASE 0x40020800U |
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#define DMA2_BASE 0x40020400U |
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#define DMA1_BASE 0x40020000U |
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|
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/* APB2 Peripherals */ |
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#define HRTIM_BASE 0x40017400U |
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#define DFSDM1_BASE 0x40017000U |
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#define SAI3_BASE 0x40016000U |
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#define SAI2_BASE 0x40015C00U |
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#define SAI1_BASE 0x40015800U |
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#define SPI5_BASE 0x40015000U |
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#define TIM17_BASE 0x40014800U |
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#define TIM16_BASE 0x40014400U |
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#define TIM15_BASE 0x40014000U |
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#define SPI4_BASE 0x40013400U |
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#define SPI1_BASE 0x40013000U |
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#define USART6_BASE 0x40011400U |
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#define USART1_BASE 0x40011000U |
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#define TIM8_BASE 0x40010400U |
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#define TIM1_BASE 0x40010000U |
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|
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/* APB1 Peripherals */ |
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#define CAN_MSG_BASE 0x4000AC00U |
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#define CAN_CCU_BASE 0x4000A800U |
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#define FDCAN2_BASE 0x4000A400U |
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#define FDCAN1_BASE 0x4000A000U |
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#define MDIOS_BASE 0x40009400U |
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#define OPAMP_BASE 0x40009000U |
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#define SWPMI_BASE 0x40008800U |
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#define CRS_BASE 0x40008400U |
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#define UART8_BASE 0x40007C00U |
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#define UART7_BASE 0x40007800U |
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#define DAC_BASE 0x40007400U |
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#define HDMI_CEC_BASE 0x40006C00U |
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#define I2C3_BASE 0x40005C00U |
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#define I2C2_BASE 0x40005800U |
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#define I2C1_BASE 0x40005400U |
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#define UART5_BASE 0x40005000U |
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#define UART4_BASE 0x40004C00U |
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#define USART3_BASE 0x40004800U |
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#define USART2_BASE 0x40004400U |
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#define SPDIFRX1_BASE 0x40004000U |
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#define SPI3_BASE 0x40003C00U |
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#define SPI2_BASE 0x40003800U |
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#define LPTIM1_BASE 0x40002400U |
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#define TIM14_BASE 0x40002000U |
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#define TIM13_BASE 0x40001C00U |
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#define TIM12_BASE 0x40001800U |
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#define TIM7_BASE 0x40001400U |
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#define TIM6_BASE 0x40001000U |
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#define TIM5_BASE 0x40000C00U |
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#define TIM4_BASE 0x40000800U |
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#define TIM3_BASE 0x40000400U |
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#define TIM2_BASE 0x40000000U |
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#endif |
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@ -0,0 +1,79 @@ |
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/*
|
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* This file is part of the libopencm3 project. |
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* |
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* Copyright (C) 2019 Brian Viele <vielster@allocor.tech> |
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* |
|||
* This library is free software: you can redistribute it and/or modify |
|||
* it under the terms of the GNU Lesser General Public License as published by |
|||
* the Free Software Foundation, either version 3 of the License, or |
|||
* (at your option) any later version. |
|||
* |
|||
* This library is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU Lesser General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU Lesser General Public License |
|||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|||
*/ |
|||
|
|||
#ifndef LIBOPENCM3_PWR_H |
|||
#define LIBOPENCM3_PWR_H |
|||
|
|||
/**@{*/ |
|||
|
|||
/** @defgroup pwr_registers PWR Registers
|
|||
* @ingroup STM32H_pwr_defines |
|||
@{*/ |
|||
/** Power control register. */ |
|||
#define PWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00) |
|||
|
|||
/** Power control/status register. */ |
|||
#define PWR_CSR1 MMIO32(POWER_CONTROL_BASE + 0x04) |
|||
|
|||
/** Power control register 2. */ |
|||
#define PWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x08) |
|||
|
|||
/** Power control register 3. */ |
|||
#define PWR_CR3 MMIO32(POWER_CONTROL_BASE + 0x0C) |
|||
|
|||
/** CPU Power control register 3. */ |
|||
#define PWR_CPUCR MMIO32(POWER_CONTROL_BASE + 0x10) |
|||
|
|||
/** D3 Domain Power Control register. */ |
|||
#define PWR_D3CR MMIO32(POWER_CONTROL_BASE + 0x18) |
|||
|
|||
/** Wakeup Domain Power Control register. */ |
|||
#define PWR_WKUPCR MMIO32(POWER_CONTROL_BASE + 0x20) |
|||
|
|||
/*@}*/ |
|||
|
|||
/** VOS[15:14]: Regulator voltage scaling output selection */ |
|||
#define PWR_CR1_SVOS_SHIFT 14 |
|||
#define PWR_CR1_SVOS_SCALE_3 (0x3) |
|||
#define PWR_CR1_SVOS_SCALE_4 (0x2) |
|||
#define PWR_CR1_SVOS_SCALE_5 (0x1) |
|||
#define PWR_CR1_SVOS_MASK (0x3) |
|||
|
|||
/** DBP[8]: Disable backup domain write protection. */ |
|||
#define PWR_CR1_DBP (1 << 8) |
|||
|
|||
/** PVDO: PVD output */ |
|||
#define PWR_CSR1_PVDO (1 << 4) |
|||
|
|||
/* --- Function prototypes ------------------------------------------------- */ |
|||
enum pwr_svos_scale { |
|||
PWR_SCALE3 = PWR_CR1_SVOS_SCALE_3 << PWR_CR1_SVOS_SHIFT, |
|||
PWR_SCALE4 = PWR_CR1_SVOS_SCALE_4 << PWR_CR1_SVOS_SHIFT, |
|||
PWR_SCALE5 = PWR_CR1_SVOS_SCALE_5 << PWR_CR1_SVOS_SHIFT, |
|||
}; |
|||
|
|||
BEGIN_DECLS |
|||
|
|||
void pwr_set_svos_scale(enum pwr_svos_scale scale); |
|||
|
|||
END_DECLS |
|||
|
|||
/**@}*/ |
|||
|
|||
#endif |
|||
@ -0,0 +1,430 @@ |
|||
/*
|
|||
* This file is part of the libopencm3 project. |
|||
* |
|||
* Copyright (C) 2019 Brian Viele <vielster@allocor.tech> |
|||
* |
|||
* This library is free software: you can redistribute it and/or modify |
|||
* it under the terms of the GNU Lesser General Public License as published by |
|||
* the Free Software Foundation, either version 3 of the License, or |
|||
* (at your option) any later version. |
|||
* |
|||
* This library is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU Lesser General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU Lesser General Public License |
|||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|||
*/ |
|||
|
|||
#ifndef LIBOPENCM3_RCC_H |
|||
#define LIBOPENCM3_RCC_H |
|||
|
|||
#include <libopencm3/stm32/h7/pwr.h> |
|||
|
|||
/**@{*/ |
|||
|
|||
/* --- RCC registers ------------------------------------------------------- */ |
|||
#define RCC_CR MMIO32(RCC_BASE + 0x000) |
|||
#define RCC_CFGR MMIO32(RCC_BASE + 0x010) |
|||
|
|||
/** @addtogroup rcc_cr_values RCC_CR_VALUES
|
|||
* @ingroup rcc_registers |
|||
@{*/ |
|||
#define RCC_CR_PLL3AIRDY (1 << 29) |
|||
#define RCC_CR_PLL3AION (1 << 28) |
|||
#define RCC_CR_PLL2RDY (1 << 27) |
|||
#define RCC_CR_PLL2ON (1 << 26) |
|||
#define RCC_CR_PLL1RDY (1 << 25) |
|||
#define RCC_CR_PLL1ON (1 << 24) |
|||
#define RCC_CR_HSECSSON (1 << 19) |
|||
#define RCC_CR_HSEBYP (1 << 18) |
|||
#define RCC_CR_HSERDY (1 << 17) |
|||
#define RCC_CR_HSEON (1 << 16) |
|||
#define RCC_CR_D2CKRDY (1 << 15) |
|||
#define RCC_CR_D1CKRDY (1 << 14) |
|||
#define RCC_CR_HSI48RDY (1 << 13) |
|||
#define RCC_CR_HSI48ON (1 << 12) |
|||
#define RCC_CR_CSIKERON (1 << 9) |
|||
#define RCC_CR_CSIRDY (1 << 8) |
|||
#define RCC_CR_CSION (1 << 7) |
|||
#define RCC_CR_HSIDIVF (1 << 5) |
|||
#define RCC_CR_HSIDIV_MASK (0x03) |
|||
#define RCC_CR_HSIDIV_SHIFT 3 |
|||
#define RCC_CR_HSIDIV(n) (((n) & RCC_CR_HSIDIV_MASK) << RCC_CR_HSIDIV_MASK) |
|||
#define RCC_CR_HSIRDY (1 << 2) |
|||
#define RCC_CR_HSIKERON (1 << 1) |
|||
#define RCC_CR_HSION (1 << 0) |
|||
/**@}*/ |
|||
|
|||
/** @addtogroup rcc_rstr_values RCC_RSTR_VALUES
|
|||
* @ingroup rcc_registers |
|||
@{*/ |
|||
#define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x080) |
|||
#define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x084) |
|||
#define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x07C) |
|||
#define RCC_AHB4RSTR MMIO32(RCC_BASE + 0x088) |
|||
#define RCC_APB1LRSTR MMIO32(RCC_BASE + 0x090) |
|||
#define RCC_APB1HRSTR MMIO32(RCC_BASE + 0x094) |
|||
#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x098) |
|||
#define RCC_APB3RSTR MMIO32(RCC_BASE + 0x08C) |
|||
#define RCC_APB4RSTR MMIO32(RCC_BASE + 0x09C) |
|||
#define RCC_AHB1ENR MMIO32(RCC_BASE + 0x0D8) |
|||
#define RCC_AHB2ENR MMIO32(RCC_BASE + 0x0DC) |
|||
#define RCC_AHB3ENR MMIO32(RCC_BASE + 0x0D4) |
|||
#define RCC_AHB4ENR MMIO32(RCC_BASE + 0x0E0) |
|||
#define RCC_APB1LENR MMIO32(RCC_BASE + 0x0E8) |
|||
#define RCC_APB1HENR MMIO32(RCC_BASE + 0x0EC) |
|||
#define RCC_APB2ENR MMIO32(RCC_BASE + 0x0F0) |
|||
#define RCC_APB3ENR MMIO32(RCC_BASE + 0x0E4) |
|||
#define RCC_APB4ENR MMIO32(RCC_BASE + 0x0F4) |
|||
#define RCC_AHB1LPENR MMIO32(RCC_BASE + 0x100) |
|||
#define RCC_AHB2LPENR MMIO32(RCC_BASE + 0x104) |
|||
#define RCC_AHB4LPENR MMIO32(RCC_BASE + 0x108) |
|||
#define RCC_APB1LLPENR MMIO32(RCC_BASE + 0x110) |
|||
#define RCC_APB1HLPENR MMIO32(RCC_BASE + 0x114) |
|||
#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x118) |
|||
#define RCC_APB3LPENR MMIO32(RCC_BASE + 0x10C) |
|||
#define RCC_APB4LPENR MMIO32(RCC_BASE + 0x11C) |
|||
#define RCC_BDCR MMIO32(RCC_BASE + 0x70) |
|||
#define RCC_CSR MMIO32(RCC_BASE + 0x74) |
|||
#define RCC_SSCGR MMIO32(RCC_BASE + 0x80) |
|||
#define RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84) |
|||
#define RCC_PLLSAICFGR MMIO32(RCC_BASE + 0x88) |
|||
#define RCC_DCKCFGR1 MMIO32(RCC_BASE + 0x8C) |
|||
#define RCC_DCKCFGR2 MMIO32(RCC_BASE + 0x90) |
|||
/**@}*/ |
|||
|
|||
/** @addtogroup rcc_cfgr_values RCC_CFGR_VALUES
|
|||
* @ingroup rcc_registers |
|||
@{*/ |
|||
/* MCO2: Microcontroller clock output 2 */ |
|||
#define RCC_CFGR_MCO2_MASK 0x7 |
|||
#define RCC_CFGR_MCO2_SHIFT 29 |
|||
#define RCC_CFGR_MCO2_SYSCLK 0x0 |
|||
#define RCC_CFGR_MCO2_PLL2 0x1 |
|||
#define RCC_CFGR_MCO2_HSE 0x2 |
|||
#define RCC_CFGR_MCO2_PLL1 0x3 |
|||
#define RCC_CFGR_MCO2_CSI 0x4 |
|||
#define RCC_CFGR_MCO2_LSI 0x5 |
|||
|
|||
/* MCO1/2PRE: MCO Prescalers */ |
|||
#define RCC_CFGR_MCOPRE_MASK 0xf |
|||
#define RCC_CFGR_MCO2PRE_SHIFT 25 |
|||
#define RCC_CFGR_MCO1PRE_SHIFT 18 |
|||
#define RCC_CFGR_MCOPRE_DIV_NONE 0x0 |
|||
#define RCC_CFGR_MCOPRE_DIV_BYP 0x1 |
|||
#define RCC_CFGR_MCOPRE_DIV_2 0x2 |
|||
#define RCC_CFGR_MCOPRE_DIV_3 0x3 |
|||
#define RCC_CFGR_MCOPRE_DIV_4 0x4 |
|||
/* Note: MCOPRE_DIV can go from 1 - 15 */ |
|||
|
|||
/* MCO1: Microcontroller clock output 1 */ |
|||
#define RCC_CFGR_MCO1_MASK 0x7 |
|||
#define RCC_CFGR_MCO1_SHIFT 22 |
|||
#define RCC_CFGR_MCO1_HSI 0x0 |
|||
#define RCC_CFGR_MCO1_LSE 0x1 |
|||
#define RCC_CFGR_MCO1_HSE 0x2 |
|||
#define RCC_CFGR_MCO1_PLL1 0x3 |
|||
#define RCC_CFGR_MCO1_HSI48 0x4 |
|||
#define RCC_CFGR_MCO_SHIFT RCC_CFGR_MCO1_SHIFT |
|||
#define RCC_CFGR_MCO_MASK RCC_CFGR_MCO1_MASK |
|||
|
|||
/* RTCPRE: HSE division factor for RTC clock */ |
|||
#define RCC_CFGR_RTCPRE_SHIFT 8 |
|||
#define RCC_CFGR_RTCPRE_MASK 0x3f |
|||
|
|||
/* SWS: System clock switch status */ |
|||
#define RCC_CFGR_SWS_SHIFT 3 |
|||
#define RCC_CFGR_SWS_MASK 0x7 |
|||
#define RCC_CFGR_SWS_HSI 0x0 |
|||
#define RCC_CFGR_SWS_CSI 0x1 |
|||
#define RCC_CFGR_SWS_HSE 0x2 |
|||
#define RCC_CFGR_SWS_PLL1 0x3 |
|||
|
|||
/* SW: System clock switch */ |
|||
#define RCC_CFGR_SW_SHIFT 0 |
|||
#define RCC_CFGR_SW_MASK 0x7 |
|||
#define RCC_CFGR_SW_HSI 0x0 |
|||
#define RCC_CFGR_SW_CSI 0x1 |
|||
#define RCC_CFGR_SW_HSE 0x2 |
|||
#define RCC_CFGR_SW_PLL1 0x3 |
|||
/**@}*/ |
|||
|
|||
|
|||
/** @addtogroup rcc_bdcr_values RCC_BDCR_VALUES
|
|||
* @ingroup rcc_registers |
|||
@{*/ |
|||
#define RCC_BDCR_BDRST (1 << 16) |
|||
#define RCC_BDCR_RTCEN (1 << 15) |
|||
#define RCC_BDCR_RTCSEL_MASK 0x3 |
|||
#define RCC_BDCR_RTCSEL_SHIFT 8 |
|||
#define RCC_BDCR_RTCSEL_NONE 0 |
|||
#define RCC_BDCR_RTCSEL_LSE 1 |
|||
#define RCC_BDCR_RTCSEL_LSI 2 |
|||
#define RCC_BDCR_RTCSEL_HSE 3 |
|||
#define RCC_BDCR_LSEDRV_MASK 0x3 |
|||
#define RCC_BDCR_LSEDRV_SHIFT 3 |
|||
#define RCC_BDCR_LSEDRV_LOW 0 |
|||
#define RCC_BDCR_LSEDRV_MEDH 1 /* good job st */ |
|||
#define RCC_BDCR_LSEDRV_MEDL 2 |
|||
#define RCC_BDCR_LSEDRV_HIGH 3 |
|||
#define RCC_BDCR_LSEBYP (1 << 2) |
|||
#define RCC_BDCR_LSERDY (1 << 1) |
|||
#define RCC_BDCR_LSEON (1 << 0) |
|||
/**@}*/ |
|||
|
|||
/** @addtogroup rcc_bdcr_values RCC_CSR_VALUES
|
|||
* @ingroup rcc_registers |
|||
@{*/ |
|||
#define RCC_CSR_LSIRDY (1 << 1) |
|||
#define RCC_CSR_LSION (1 << 0) |
|||
/**@}*/ |
|||
|
|||
extern uint32_t rcc_ahb_frequency; |
|||
extern uint32_t rcc_apb1_frequency; |
|||
extern uint32_t rcc_apb2_frequency; |
|||
|
|||
enum rcc_osc { |
|||
RCC_PLL, |
|||
RCC_HSE, |
|||
RCC_HSI, |
|||
RCC_LSE, |
|||
RCC_LSI |
|||
}; |
|||
|
|||
#define _REG_BIT(base, bit) (((base) << 5) + (bit)) |
|||
|
|||
enum rcc_periph_clken { |
|||
/* AHB1 peripherals */ |
|||
RCC_DMA1 = _REG_BIT(0xD8, 0), |
|||
RCC_DMA2 = _REG_BIT(0xD8, 1), |
|||
RCC_ADC12 = _REG_BIT(0xD8, 5), |
|||
RCC_ETH1MAC = _REG_BIT(0xD8, 15), |
|||
RCC_ETH1TX = _REG_BIT(0xD8, 16), |
|||
RCC_ETH1RX = _REG_BIT(0xD8, 17), |
|||
RCC_USB2OTGHSULPIEN = _REG_BIT(0xD8, 18), |
|||
RCC_USB1OTGHSEN = _REG_BIT(0xD8, 25), |
|||
RCC_USB1OTGHSULPIEN = _REG_BIT(0xD8, 26), |
|||
RCC_USB2OTGHSEN = _REG_BIT(0xD8, 27), |
|||
|
|||
/* AHB2 peripherals */ |
|||
RCC_DCMI = _REG_BIT(0xDC, 0), |
|||
RCC_CRYP = _REG_BIT(0xDC, 4), |
|||
RCC_HASH = _REG_BIT(0xDC, 5), |
|||
RCC_RNG = _REG_BIT(0xDC, 6), |
|||
RCC_SDMMC2 = _REG_BIT(0xDC, 9), |
|||
RCC_SRAM1 = _REG_BIT(0xDC, 29), |
|||
RCC_SRAM2 = _REG_BIT(0xDC, 30), |
|||
RCC_SRAM3 = _REG_BIT(0xDC, 31), |
|||
|
|||
/* AHB3 peripherals */ |
|||
RCC_MDMA = _REG_BIT(0xD4, 0), |
|||
RCC_DMA2D = _REG_BIT(0xD4, 4), |
|||
RCC_JPGDEC = _REG_BIT(0xD4, 5), |
|||
RCC_FMC = _REG_BIT(0xD4, 12), |
|||
RCC_QSPI = _REG_BIT(0xD4, 14), |
|||
RCC_SDMMC1 = _REG_BIT(0xD4, 16), |
|||
|
|||
/* AHB4 peripherals*/ |
|||
RCC_GPIOA = _REG_BIT(0xE0, 0), |
|||
RCC_GPIOB = _REG_BIT(0xE0, 1), |
|||
RCC_GPIOC = _REG_BIT(0xE0, 2), |
|||
RCC_GPIOD = _REG_BIT(0xE0, 3), |
|||
RCC_GPIOE = _REG_BIT(0xE0, 4), |
|||
RCC_GPIOF = _REG_BIT(0xE0, 5), |
|||
RCC_GPIOG = _REG_BIT(0xE0, 6), |
|||
RCC_GPIOH = _REG_BIT(0xE0, 7), |
|||
RCC_GPIOI = _REG_BIT(0xE0, 8), |
|||
RCC_GPIOJ = _REG_BIT(0xE0, 9), |
|||
RCC_GPIOK = _REG_BIT(0xE0, 10), |
|||
RCC_CRC = _REG_BIT(0xE0, 19), |
|||
RCC_BDMA = _REG_BIT(0xE0, 21), |
|||
RCC_ADC3 = _REG_BIT(0xE0, 24), |
|||
RCC_HSEM = _REG_BIT(0xE0, 25), |
|||
RCC_BKPSRAM = _REG_BIT(0xE0, 28), |
|||
|
|||
/* APB1L peripherals*/ |
|||
RCC_TIM2 = _REG_BIT(0xE8, 0), |
|||
RCC_TIM3 = _REG_BIT(0xE8, 1), |
|||
RCC_TIM4 = _REG_BIT(0xE8, 2), |
|||
RCC_TIM5 = _REG_BIT(0xE8, 3), |
|||
RCC_TIM6 = _REG_BIT(0xE8, 4), |
|||
RCC_TIM7 = _REG_BIT(0xE8, 5), |
|||
RCC_TIM12 = _REG_BIT(0xE8, 6), |
|||
RCC_TIM13 = _REG_BIT(0xE8, 7), |
|||
RCC_TIM14 = _REG_BIT(0xE8, 8), |
|||
RCC_LPTIM1 = _REG_BIT(0xE8, 9), |
|||
RCC_SPI2 = _REG_BIT(0xE8, 14), |
|||
RCC_SPI3 = _REG_BIT(0xE8, 15), |
|||
RCC_SPDIFRX = _REG_BIT(0xE8, 16), |
|||
RCC_USART2 = _REG_BIT(0xE8, 17), |
|||
RCC_USART3 = _REG_BIT(0xE8, 18), |
|||
RCC_UART4 = _REG_BIT(0xE8, 19), |
|||
RCC_UART5 = _REG_BIT(0xE8, 20), |
|||
RCC_I2C1 = _REG_BIT(0xE8, 21), |
|||
RCC_I2C2 = _REG_BIT(0xE8, 22), |
|||
RCC_I2C3 = _REG_BIT(0xE8, 23), |
|||
RCC_CEC = _REG_BIT(0xE8, 27), |
|||
RCC_DAC = _REG_BIT(0xE8, 29), |
|||
RCC_UART7 = _REG_BIT(0xE8, 30), |
|||
RCC_UART8 = _REG_BIT(0xE8, 31), |
|||
|
|||
/* APB1H peripherals*/ |
|||
RCC_CRS = _REG_BIT(0xEC, 1), |
|||
RCC_SWP = _REG_BIT(0xEC, 2), |
|||
RCC_OPAMP = _REG_BIT(0xEC, 4), |
|||
RCC_MDIO = _REG_BIT(0xEC, 5), |
|||
RCC_FDCAN = _REG_BIT(0xEC, 8), |
|||
|
|||
/* APB2 peripherals */ |
|||
RCC_TIM1 = _REG_BIT(0xF0, 0), |
|||
RCC_TIM8 = _REG_BIT(0xF0, 1), |
|||
RCC_USART1 = _REG_BIT(0xF0, 4), |
|||
RCC_USART6 = _REG_BIT(0xF0, 5), |
|||
RCC_SPI1 = _REG_BIT(0xF0, 12), |
|||
RCC_SPI4 = _REG_BIT(0xF0, 13), |
|||
RCC_TIM15 = _REG_BIT(0xF0, 16), |
|||
RCC_TIM16 = _REG_BIT(0xF0, 17), |
|||
RCC_TIM17 = _REG_BIT(0xF0, 18), |
|||
RCC_SPI5 = _REG_BIT(0xF0, 20), |
|||
RCC_SAI1 = _REG_BIT(0xF0, 22), |
|||
RCC_SAI2 = _REG_BIT(0xF0, 23), |
|||
RCC_SAI3 = _REG_BIT(0xF0, 24), |
|||
RCC_DFSDM = _REG_BIT(0xF0, 28), |
|||
RCC_HRTIM = _REG_BIT(0xF0, 29), |
|||
|
|||
/* APB3 peripherals */ |
|||
RCC_LTDCEN = _REG_BIT(0xE4, 3), |
|||
RCC_WWDG1EN = _REG_BIT(0xE4, 6), |
|||
|
|||
/* APB4 peripherals */ |
|||
RCC_SYSCFG = _REG_BIT(0xF4, 1), |
|||
RCC_LPUART1 = _REG_BIT(0xF4, 3), |
|||
RCC_SPI6 = _REG_BIT(0xF4, 5), |
|||
RCC_I2C4 = _REG_BIT(0xF4, 7), |
|||
RCC_LPTIM2 = _REG_BIT(0xF4, 9), |
|||
RCC_LPTIM3 = _REG_BIT(0xF4, 10), |
|||
RCC_LPTIM4 = _REG_BIT(0xF4, 11), |
|||
RCC_LPTIM5 = _REG_BIT(0xF4, 12), |
|||
RCC_COMP12 = _REG_BIT(0xF4, 14), |
|||
RCC_VREF = _REG_BIT(0xF4, 15), |
|||
RCC_RTCAPB = _REG_BIT(0xF4, 16), |
|||
RCC_SAI4 = _REG_BIT(0xF4, 21), |
|||
}; |
|||
|
|||
enum rcc_periph_rst { |
|||
/* AHB1 peripherals */ |
|||
RST_DMA1 = _REG_BIT(0x80, 0), |
|||
RST_DMA2 = _REG_BIT(0x80, 1), |
|||
RST_ADC12 = _REG_BIT(0x80, 5), |
|||
RST_ETH1MAC = _REG_BIT(0x80, 15), |
|||
RST_USB1OTGRST = _REG_BIT(0x80, 25), |
|||
RST_USB2OTGRST = _REG_BIT(0x80, 27), |
|||
|
|||
/* AHB2 peripherals */ |
|||
RST_DCMI = _REG_BIT(0xDC, 0), |
|||
RST_CRYP = _REG_BIT(0xDC, 4), |
|||
RST_HASH = _REG_BIT(0xDC, 5), |
|||
RST_RNG = _REG_BIT(0xDC, 6), |
|||
RST_SDMMC2 = _REG_BIT(0xDC, 9), |
|||
|
|||
/* AHB3 peripherals */ |
|||
RST_MDMA = _REG_BIT(0x7C, 0), |
|||
RST_DMA2D = _REG_BIT(0x7C, 4), |
|||
RST_JPGDEC = _REG_BIT(0x7C, 5), |
|||
RST_FMC = _REG_BIT(0x7C, 12), |
|||
RST_QSPI = _REG_BIT(0x7C, 14), |
|||
RST_SDMMC1 = _REG_BIT(0x7C, 16), |
|||
|
|||
/* AHB4 peripherals*/ |
|||
RST_GPIOA = _REG_BIT(0x88, 0), |
|||
RST_GPIOB = _REG_BIT(0x88, 1), |
|||
RST_GPIOC = _REG_BIT(0x88, 2), |
|||
RST_GPIOD = _REG_BIT(0x88, 3), |
|||
RST_GPIOE = _REG_BIT(0x88, 4), |
|||
RST_GPIOF = _REG_BIT(0x88, 5), |
|||
RST_GPIOG = _REG_BIT(0x88, 6), |
|||
RST_GPIOH = _REG_BIT(0x88, 7), |
|||
RST_GPIOI = _REG_BIT(0x88, 8), |
|||
RST_GPIOJ = _REG_BIT(0x88, 9), |
|||
RST_GPIOK = _REG_BIT(0x88, 10), |
|||
RST_CRC = _REG_BIT(0x88, 19), |
|||
RST_BDMA = _REG_BIT(0x88, 21), |
|||
RST_ADC3 = _REG_BIT(0x88, 24), |
|||
RST_HSEM = _REG_BIT(0x88, 25), |
|||
|
|||
/* APB1L peripherals*/ |
|||
RST_TIM2 = _REG_BIT(0x90, 0), |
|||
RST_TIM3 = _REG_BIT(0x90, 1), |
|||
RST_TIM4 = _REG_BIT(0x90, 2), |
|||
RST_TIM5 = _REG_BIT(0x90, 3), |
|||
RST_TIM6 = _REG_BIT(0x90, 4), |
|||
RST_TIM7 = _REG_BIT(0x90, 5), |
|||
RST_TIM12 = _REG_BIT(0x90, 6), |
|||
RST_TIM13 = _REG_BIT(0x90, 7), |
|||
RST_TIM14 = _REG_BIT(0x90, 8), |
|||
RST_LPTIM1 = _REG_BIT(0x90, 9), |
|||
RST_SPI2 = _REG_BIT(0x90, 14), |
|||
RST_SPI3 = _REG_BIT(0x90, 15), |
|||
RST_SPDIFRX = _REG_BIT(0x90, 16), |
|||
RST_USART2 = _REG_BIT(0x90, 17), |
|||
RST_USART3 = _REG_BIT(0x90, 18), |
|||
RST_UART4 = _REG_BIT(0x90, 19), |
|||
RST_UART5 = _REG_BIT(0x90, 20), |
|||
RST_I2C1 = _REG_BIT(0x90, 21), |
|||
RST_I2C2 = _REG_BIT(0x90, 22), |
|||
RST_I2C3 = _REG_BIT(0x90, 23), |
|||
RST_CEC = _REG_BIT(0x90, 27), |
|||
RST_DAC = _REG_BIT(0x90, 29), |
|||
RST_UART7 = _REG_BIT(0x90, 30), |
|||
RST_UART8 = _REG_BIT(0x90, 31), |
|||
|
|||
/* APB1H peripherals*/ |
|||
RST_CRS = _REG_BIT(0x94, 1), |
|||
RST_SWP = _REG_BIT(0x94, 2), |
|||
RST_OPAMP = _REG_BIT(0x94, 4), |
|||
RST_MDIO = _REG_BIT(0x94, 5), |
|||
RST_FDCAN = _REG_BIT(0x94, 8), |
|||
|
|||
/* APB2 peripherals */ |
|||
RST_TIM1 = _REG_BIT(0x98, 0), |
|||
RST_TIM8 = _REG_BIT(0x98, 1), |
|||
RST_USART1 = _REG_BIT(0x98, 4), |
|||
RST_USART6 = _REG_BIT(0x98, 5), |
|||
RST_SPI1 = _REG_BIT(0x98, 12), |
|||
RST_SPI4 = _REG_BIT(0x98, 13), |
|||
RST_TIM15 = _REG_BIT(0x98, 16), |
|||
RST_TIM16 = _REG_BIT(0x98, 17), |
|||
RST_TIM17 = _REG_BIT(0x98, 18), |
|||
RST_SPI5 = _REG_BIT(0x98, 20), |
|||
RST_SAI1 = _REG_BIT(0x98, 22), |
|||
RST_SAI2 = _REG_BIT(0x98, 23), |
|||
RST_SAI3 = _REG_BIT(0x98, 24), |
|||
RST_DFSDM = _REG_BIT(0x98, 28), |
|||
RST_HRTIM = _REG_BIT(0x98, 29), |
|||
|
|||
/* APB3 peripherals */ |
|||
RST_LTDCRST = _REG_BIT(0x8C, 3), |
|||
|
|||
/* APB4 peripherals */ |
|||
RST_SYSCFG = _REG_BIT(0x9C, 1), |
|||
RST_LPUART1 = _REG_BIT(0x9C, 3), |
|||
RST_SPI6 = _REG_BIT(0x9C, 5), |
|||
RST_I2C4 = _REG_BIT(0x9C, 7), |
|||
RST_LPTIM2 = _REG_BIT(0x9C, 9), |
|||
RST_LPTIM3 = _REG_BIT(0x9C, 10), |
|||
RST_LPTIM4 = _REG_BIT(0x9C, 11), |
|||
RST_LPTIM5 = _REG_BIT(0x9C, 12), |
|||
RST_COMP12 = _REG_BIT(0x9C, 14), |
|||
RST_VREF = _REG_BIT(0x9C, 15), |
|||
RST_SAI4 = _REG_BIT(0x9C, 21), |
|||
}; |
|||
|
|||
#undef _REG_BIT |
|||
|
|||
#include <libopencm3/stm32/common/rcc_common_all.h> |
|||
|
|||
/**@}*/ |
|||
|
|||
#endif |
|||
@ -0,0 +1,24 @@ |
|||
/*
|
|||
* This file is part of the libopencm3 project. |
|||
* |
|||
* This library is free software: you can redistribute it and/or modify |
|||
* it under the terms of the GNU Lesser General Public License as published by |
|||
* the Free Software Foundation, either version 3 of the License, or |
|||
* (at your option) any later version. |
|||
* |
|||
* This library is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU Lesser General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU Lesser General Public License |
|||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|||
*/ |
|||
|
|||
#ifndef LIBOPENCM3_SPI_H |
|||
#define LIBOPENCM3_SPI_H |
|||
|
|||
#include <libopencm3/stm32/common/spi_common_v2.h> |
|||
|
|||
#endif |
|||
|
|||
@ -0,0 +1,27 @@ |
|||
/*
|
|||
* This file is part of the libopencm3 project. |
|||
* |
|||
* This library is free software: you can redistribute it and/or modify |
|||
* it under the terms of the GNU Lesser General Public License as published by |
|||
* the Free Software Foundation, either version 3 of the License, or |
|||
* (at your option) any later version. |
|||
* |
|||
* This library is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU Lesser General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU Lesser General Public License |
|||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|||
*/ |
|||
|
|||
#ifndef LIBOPENCM3_TIMER_H |
|||
#define LIBOPENCM3_TIMER_H |
|||
|
|||
#include <libopencm3/stm32/common/timer_common_all.h> |
|||
|
|||
BEGIN_DECLS |
|||
|
|||
END_DECLS |
|||
|
|||
#endif |
|||
@ -0,0 +1,60 @@ |
|||
/** @defgroup usart_defines USART Defines
|
|||
* |
|||
* @brief <b>Defined Constants and Types for the STM32H7xx USART</b> |
|||
* |
|||
* @ingroup STM32H7xx_defines |
|||
* |
|||
* @version 1.0.0 |
|||
* |
|||
* @date 6 November 2019 |
|||
* |
|||
* LGPL License Terms @ref lgpl_license |
|||
*/ |
|||
|
|||
/*
|
|||
* This file is part of the libopencm3 project. |
|||
* |
|||
* This library is free software: you can redistribute it and/or modify |
|||
* it under the terms of the GNU Lesser General Public License as published by |
|||
* the Free Software Foundation, either version 3 of the License, or |
|||
* (at your option) any later version. |
|||
* |
|||
* This library is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU Lesser General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU Lesser General Public License |
|||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|||
*/ |
|||
|
|||
#ifndef LIBOPENCM3_USART_H |
|||
#define LIBOPENCM3_USART_H |
|||
|
|||
#include <libopencm3/stm32/common/usart_common_all.h> |
|||
#include <libopencm3/stm32/common/usart_common_v2.h> |
|||
|
|||
/**@{*/ |
|||
|
|||
/** @defgroup usart_reg_base USART register base addresses
|
|||
* Holds all the U(S)ART peripherals supported. |
|||
* @{ |
|||
*/ |
|||
#define USART1 USART1_BASE |
|||
#define USART2 USART2_BASE |
|||
#define USART3 USART3_BASE |
|||
#define UART4 UART4_BASE |
|||
#define UART5 UART5_BASE |
|||
#define USART6 USART6_BASE |
|||
#define UART7 UART7_BASE |
|||
#define UART8 UART8_BASE |
|||
/**@}*/ |
|||
|
|||
BEGIN_DECLS |
|||
|
|||
END_DECLS |
|||
|
|||
/**@}*/ |
|||
|
|||
#endif |
|||
|
|||
@ -0,0 +1,52 @@ |
|||
##
|
|||
## This file is part of the libopencm3 project.
|
|||
##
|
|||
## This library is free software: you can redistribute it and/or modify
|
|||
## it under the terms of the GNU Lesser General Public License as published by
|
|||
## the Free Software Foundation, either version 3 of the License, or
|
|||
## (at your option) any later version.
|
|||
##
|
|||
## This library is distributed in the hope that it will be useful,
|
|||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|||
## GNU Lesser General Public License for more details.
|
|||
##
|
|||
## You should have received a copy of the GNU Lesser General Public License
|
|||
## along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|||
##
|
|||
|
|||
LIBNAME = libopencm3_stm32h7 |
|||
SRCLIBDIR ?= ../.. |
|||
|
|||
CC = $(PREFIX)gcc |
|||
AR = $(PREFIX)ar |
|||
|
|||
# STM32H7 supports double precision FPU
|
|||
FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv5-d16 |
|||
|
|||
TGT_CFLAGS = -Os \
|
|||
-Wall -Wextra -Wimplicit-function-declaration \
|
|||
-Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
|
|||
-Wundef -Wshadow \
|
|||
-I../../../include -fno-common \
|
|||
-mcpu=cortex-m7 -mthumb $(FP_FLAGS) \
|
|||
-Wstrict-prototypes \
|
|||
-ffunction-sections -fdata-sections -MD -DSTM32H7 |
|||
TGT_CFLAGS += $(DEBUG_FLAGS) |
|||
TGT_CFLAGS += $(STANDARD_FLAGS) |
|||
|
|||
ARFLAGS = rcs |
|||
|
|||
OBJS += dac_common_all.o |
|||
OBJS += flash_common_all.o flash_common_f.o flash_common_f24.o |
|||
OBJS += fmc_common_f47.o |
|||
OBJS += gpio_common_all.o gpio_common_f0234.o |
|||
OBJS += pwr.o rcc.o |
|||
OBJS += rcc_common_all.o |
|||
OBJS += spi_common_all.o spi_common_v2.o |
|||
OBJS += timer_common_all.o |
|||
OBJS += usart_common_all.o usart_common_v2.o |
|||
|
|||
VPATH += ../../usb:../:../../cm3:../common |
|||
|
|||
include ../../Makefile.include |
|||
@ -0,0 +1,50 @@ |
|||
/** @defgroup pwr_file PWR peripheral API
|
|||
* |
|||
* @ingroup peripheral_apis |
|||
* |
|||
* @brief <b>libopencm3 STM32H7xx Power Control</b> |
|||
* |
|||
* @version 1.0.0 |
|||
* |
|||
* @author @htmlonly © @endhtmlonly 2011 Stephen Caudle <scaudle@doceme.com> |
|||
* @author @htmlonly © @endhtmlonly 2017 Matthew Lai <m@matthewlai.ca> |
|||
* |
|||
* @date 12 March 2017 |
|||
* |
|||
* This library supports the power control system for the |
|||
* STM32H7 series of ARM Cortex Microcontrollers by ST Microelectronics. |
|||
* |
|||
* LGPL License Terms @ref lgpl_license |
|||
*/ |
|||
/*
|
|||
* This file is part of the libopencm3 project. |
|||
* |
|||
* Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com> |
|||
* Copyright (C) 2017 Matthew Lai <m@matthewlai.ca> |
|||
* |
|||
* This library is free software: you can redistribute it and/or modify |
|||
* it under the terms of the GNU Lesser General Public License as published by |
|||
* the Free Software Foundation, either version 3 of the License, or |
|||
* (at your option) any later version. |
|||
* |
|||
* This library is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU Lesser General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU Lesser General Public License |
|||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|||
*/ |
|||
|
|||
#include <libopencm3/stm32/pwr.h> |
|||
|
|||
/**@{*/ |
|||
|
|||
void pwr_set_svos_scale(enum pwr_svos_scale scale) |
|||
{ |
|||
uint32_t pwr_cr1_reg = PWR_CR1; |
|||
pwr_cr1_reg = (pwr_cr1_reg & ~PWR_CR1_SVOS_MASK) | scale; |
|||
PWR_CR1 = pwr_cr1_reg; |
|||
} |
|||
|
|||
/**@}*/ |
|||
@ -0,0 +1,21 @@ |
|||
/** @defgroup rcc_file RCC peripheral API
|
|||
* |
|||
* @ingroup peripheral_apis |
|||
* This library supports the Reset and Clock Control System in the STM32 series |
|||
* of ARM Cortex Microcontrollers by ST Microelectronics. |
|||
* |
|||
* LGPL License Terms @ref lgpl_license |
|||
*/ |
|||
|
|||
#include <libopencm3/cm3/assert.h> |
|||
#include <libopencm3/stm32/rcc.h> |
|||
#include <libopencm3/stm32/pwr.h> |
|||
#include <libopencm3/stm32/flash.h> |
|||
|
|||
/**@{*/ |
|||
|
|||
uint32_t rcc_ahb_frequency = 64000000; |
|||
uint32_t rcc_apb1_frequency = 64000000; |
|||
uint32_t rcc_apb2_frequency = 64000000; |
|||
|
|||
/**@}*/ |
|||
@ -0,0 +1,27 @@ |
|||
/*
|
|||
* This file is part of the libopencm3 project. |
|||
* |
|||
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net> |
|||
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com> |
|||
* |
|||
* This library is free software: you can redistribute it and/or modify |
|||
* it under the terms of the GNU Lesser General Public License as published by |
|||
* the Free Software Foundation, either version 3 of the License, or |
|||
* (at your option) any later version. |
|||
* |
|||
* This library is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU Lesser General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU Lesser General Public License |
|||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|||
*/ |
|||
|
|||
#include <libopencm3/cm3/scb.h> |
|||
|
|||
static void pre_main(void) |
|||
{ |
|||
/* Enable access to Floating-Point coprocessor. */ |
|||
SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11); |
|||
} |
|||
Loading…
Reference in new issue