diff --git a/Makefile b/Makefile index 98f3d18d..67518ad8 100644 --- a/Makefile +++ b/Makefile @@ -29,6 +29,7 @@ SRCLIBDIR:= $(subst $(space),\$(space),$(realpath lib)) TARGETS ?= stm32/f0 stm32/f1 stm32/f2 stm32/f3 stm32/f4 stm32/f7 \ stm32/l0 stm32/l1 stm32/l4 \ stm32/g0 \ + stm32/h7 \ gd32/f1x0 \ lpc13xx lpc17xx lpc43xx/m4 lpc43xx/m0 \ lm3s lm4f msp432/e4 \ diff --git a/doc/Makefile b/doc/Makefile index 7695ebdc..4bc0db7a 100644 --- a/doc/Makefile +++ b/doc/Makefile @@ -4,7 +4,7 @@ # (C) Ken Sarkies # setup TARGETS if not set for legacy and ease of debug. -TARGETS ?= stm32/f0 stm32/f1 stm32/f2 stm32/f3 stm32/f4 stm32/f7 \ +TARGETS ?= stm32/f0 stm32/f1 stm32/f2 stm32/f3 stm32/f4 stm32/f7 stm32/h7 \ stm32/l0 stm32/l1 stm32/l4 \ stm32/g0 \ gd32/f1x0 \ diff --git a/doc/stm32h7/doxy.custom b/doc/stm32h7/doxy.custom new file mode 100644 index 00000000..4789a761 --- /dev/null +++ b/doc/stm32h7/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7EM__ diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index f2f65180..61a9c1d8 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -22,6 +22,8 @@ # include #elif defined(STM32G0) # include +#elif defined(STM32H7) +# include #elif defined(GD32F1X0) # include diff --git a/include/libopencm3/stm32/dac.h b/include/libopencm3/stm32/dac.h index 6a17a738..196d2e8e 100644 --- a/include/libopencm3/stm32/dac.h +++ b/include/libopencm3/stm32/dac.h @@ -36,6 +36,8 @@ # include #elif defined(STM32L4) # include +#elif defined(STM32H7) +# include #else # error "stm32 family not defined." #endif diff --git a/include/libopencm3/stm32/flash.h b/include/libopencm3/stm32/flash.h index b8057bef..7da5a697 100644 --- a/include/libopencm3/stm32/flash.h +++ b/include/libopencm3/stm32/flash.h @@ -40,6 +40,8 @@ # include #elif defined(STM32G0) # include +#elif defined(STM32H7) +# include #elif defined(GD32F1X0) # include #else diff --git a/include/libopencm3/stm32/fsmc.h b/include/libopencm3/stm32/fsmc.h index 73a666fb..c3a0aeeb 100644 --- a/include/libopencm3/stm32/fsmc.h +++ b/include/libopencm3/stm32/fsmc.h @@ -27,6 +27,8 @@ # include #elif defined(STM32F7) # include +#elif defined(STM32H7) +# include #endif /* --- Convenience macros -------------------------------------------------- */ diff --git a/include/libopencm3/stm32/gpio.h b/include/libopencm3/stm32/gpio.h index 14dd418a..95715123 100644 --- a/include/libopencm3/stm32/gpio.h +++ b/include/libopencm3/stm32/gpio.h @@ -40,6 +40,8 @@ # include #elif defined(STM32G0) # include +#elif defined(STM32H7) +# include #elif defined(GD32F1X0) # include #else diff --git a/include/libopencm3/stm32/h7/dac.h b/include/libopencm3/stm32/h7/dac.h new file mode 100644 index 00000000..3106378c --- /dev/null +++ b/include/libopencm3/stm32/h7/dac.h @@ -0,0 +1,36 @@ +/** @defgroup dac_defines DAC Defines + +@brief Defined Constants and Types for the STM32H7xx DAC + +@ingroup STM32H7xx_defines + +@version 1.0.0 + +@date 6 November 2019 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DAC_H +#define LIBOPENCM3_DAC_H + +#include + +#endif diff --git a/include/libopencm3/stm32/h7/flash.h b/include/libopencm3/stm32/h7/flash.h new file mode 100644 index 00000000..cfd83f7a --- /dev/null +++ b/include/libopencm3/stm32/h7/flash.h @@ -0,0 +1,54 @@ +/** @defgroup flash_defines FLASH Defines + * + * @ingroup STM32H7xx_defines + * + * @author @htmlonly © @endhtmlonly 2019 + * Brian Viele + * + */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_FLASH_H +#define LIBOPENCM3_FLASH_H + +#include +#include +#include + +/**@{*/ + +/** @addtogroup flash_acr_values FLASH_ACR_VALUES + * @ingroup flash_registers +@{*/ +#define FLASH_ACR_WRHF_VOS1_70MHZ (0 << FLASH_ACR_WRHIGHFREQ_SHIFT) +#define FLASH_ACR_WRHF_VOS1_185MHZ (1 << FLASH_ACR_WRHIGHFREQ_SHIFT) +#define FLASH_ACR_WRHF_VOS1_225MHZ (2 << FLASH_ACR_WRHIGHFREQ_SHIFT) +#define FLASH_ACR_WRHF_VOS2_55MHZ (0 << FLASH_ACR_WRHIGHFREQ_SHIFT) +#define FLASH_ACR_WRHF_VOS2_165MHZ (1 << FLASH_ACR_WRHIGHFREQ_SHIFT) +#define FLASH_ACR_WRHF_VOS2_225MHZ (2 << FLASH_ACR_WRHIGHFREQ_SHIFT) +#define FLASH_ACR_WRHF_VOS3_45MHZ (0 << FLASH_ACR_WRHIGHFREQ_SHIFT) +#define FLASH_ACR_WRHF_VOS3_135MHZ (1 << FLASH_ACR_WRHIGHFREQ_SHIFT) +#define FLASH_ACR_WRHF_VOS3_225MHZ (2 << FLASH_ACR_WRHIGHFREQ_SHIFT) +/*@}*/ +#define FLASH_ACR_WRHIGHFREQ_MASK (0x3) +#define FLASH_ACR_WRHIGHFREQ_SHIFT (0x4) + +/**@}*/ + +#endif + diff --git a/include/libopencm3/stm32/h7/fmc.h b/include/libopencm3/stm32/h7/fmc.h new file mode 100644 index 00000000..f969bac1 --- /dev/null +++ b/include/libopencm3/stm32/h7/fmc.h @@ -0,0 +1,38 @@ +/** @defgroup fmc_defines FMC Defines + * @brief Defined Constants and Types for the STM32H7xx Flexible Memory + * Controller + * @ingroup STM32H7xx_defines + */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ +/**@{*/ + +#ifndef LIBOPENCM3_H7_FMC_H +#define LIBOPENCM3_H7_FMC_H + +#ifndef LIBOPENCM3_FSMC_H +#error "This file should not be included directly, it is included with fsmc.h" +#endif + +#include + +/* --- Convenience macros -------------------------------------------------- */ +#define FSMC_BASE FMC_BASE + +#endif + +/**@}*/ diff --git a/include/libopencm3/stm32/h7/gpio.h b/include/libopencm3/stm32/h7/gpio.h new file mode 100644 index 00000000..7f9067e3 --- /dev/null +++ b/include/libopencm3/stm32/h7/gpio.h @@ -0,0 +1,37 @@ +/** @defgroup gpio_defines GPIO Defines + +@brief Defined Constants and Types for the STM32H7xx General Purpose I/O + +@ingroup STM32H7xx_defines + +@version 1.0.0 + +@date 6 November 2019 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_GPIO_H +#define LIBOPENCM3_GPIO_H + +#include + +#endif + diff --git a/include/libopencm3/stm32/h7/irq.json b/include/libopencm3/stm32/h7/irq.json new file mode 100644 index 00000000..70d8c06b --- /dev/null +++ b/include/libopencm3/stm32/h7/irq.json @@ -0,0 +1,157 @@ +{ + "irqs": [ + "wwdg", + "pvd", + "tamp_stamp", + "rtc_wkup", + "flash", + "rcc", + "exti0", + "exti1", + "exti2", + "exti3", + "exti4", + "dma1_str0", + "dma1_str1", + "dma1_str2", + "dma1_str3", + "dma1_str4", + "dma1_str5", + "dma1_str6", + "adc1_2", + "fdcan1_it0", + "fdcan2_it0", + "fdcan1_it1", + "fdcan2_it2", + "exti9_5", + "tim1_brk_tim9", + "tim1_up_tim10", + "tim1_trg_com_tim11", + "tim1_cc", + "tim2", + "tim3", + "tim4", + "i2c1_ev", + "i2c1_er", + "i2c2_ev", + "i2c2_er", + "spi1", + "spi2", + "usart1", + "usart2", + "usart3", + "exti15_10", + "rtc_alarm", + "reserved1", + "tim8_brk_tim12", + "tim8_up_tim13", + "tim8_trg_com_tim14", + "tim8_cc", + "dma1_str7", + "fsmc", + "sdmmc1", + "tim5", + "spi3", + "uart4", + "uart5", + "tim6_dac", + "tim7", + "dma2_str0", + "dma2_str1", + "dma2_str2", + "dma2_str3", + "dma2_str4", + "eth", + "eth_wkup", + "fdcan_cal", + "cm7_sev", + "reserved2", + "reserved3", + "reserved4", + "dma2_str5", + "dma2_str6", + "dma2_str7", + "usart6", + "i2c3_ev", + "i2c3_er", + "otg_hs_ep1_out", + "otg_hs_ep1_in", + "otg_hs_wkup", + "otg_hs", + "dcmi", + "cryp", + "hash_rng", + "fpu", + "uart7", + "uart8", + "spi4", + "spi5", + "spi6", + "sai1", + "ltdc", + "ltdc_er", + "dma2d", + "sai2", + "quadspi", + "lp_tim1", + "cec", + "i2c4_ev", + "i2c4_er", + "spdifrx", + "otg_fs_ep1_out", + "otg_fs_ep1_in", + "otg_fs_wkup", + "otg_fs", + "dmamux1_ov", + "hrtim1_mst", + "hrtim1_tima", + "hrtim1_timb", + "hrtim1_timc", + "hrtim1_timd", + "hrtim1_time", + "hrtim1_flt", + "dfsdm1_it0", + "dfsdm1_it1", + "dfsdm1_it2", + "dfsdm1_it3", + "sai3", + "swpmi1", + "tim15", + "tim16", + "tim17", + "mdios_wkup", + "mdios", + "jpeg", + "mdma", + "reserved5", + "sdmmc2", + "hsem0", + "reserved6", + "adc3", + "dmamux2_ovr", + "bdma_ch0", + "bdma_ch1", + "bdma_ch2", + "bdma_ch3", + "bdma_ch4", + "bdma_ch5", + "bdma_ch6", + "bdma_ch7", + "comp", + "lptim2", + "lptim3", + "lptim4", + "lptim5", + "lpuart", + "wwdg1_rst", + "crs", + "ramecc1", + "sai4", + "reserved7", + "reserved8", + "wkup" + ], + "partname_humanreadable": "STM32 H7 series", + "partname_doxygen": "STM32H7", + "includeguard": "LIBOPENCM3_STM32_H7_NVIC_H" +} diff --git a/include/libopencm3/stm32/h7/memorymap.h b/include/libopencm3/stm32/h7/memorymap.h new file mode 100644 index 00000000..ec892d21 --- /dev/null +++ b/include/libopencm3/stm32/h7/memorymap.h @@ -0,0 +1,157 @@ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_MEMORYMAP_H +#define LIBOPENCM3_MEMORYMAP_H + +#include + +/* --- STM32H7 specific peripheral definitions ----------------------------- */ + +/* Memory map for all busses */ +#define PERIPH_BASE 0x40000000U +#define PERIPH_BASE_APB1 0x40000000U +#define PERIPH_BASE_APB2 0x40010000U +#define PERIPH_BASE_APB3 0x50000000U +#define PERIPH_BASE_AHB1 0x40020000U +#define PERIPH_BASE_AHB2 0x48020000U +#define PERIPH_BASE_AHB3 0x51000000U +#define PERIPH_BASE_AHB4 0x58000000U + +/* Table 8: Register boundary addresses */ + +/* AHB4 Peripherals */ +#define GPIO_PORT_A_BASE 0x58020000U +#define GPIO_PORT_B_BASE 0x58020400U +#define GPIO_PORT_C_BASE 0x58020800U +#define GPIO_PORT_D_BASE 0x58020C00U +#define GPIO_PORT_E_BASE 0x58021000U +#define GPIO_PORT_F_BASE 0x58021400U +#define GPIO_PORT_G_BASE 0x58021800U +#define GPIO_PORT_H_BASE 0x58021C00U +#define GPIO_PORT_I_BASE 0x58022000U +#define GPIO_PORT_J_BASE 0x58022400U +#define GPIO_PORT_K_BASE 0x58022800U +#define RCC_BASE 0x58024400U +#define POWER_CONTROL_BASE 0x58024800U +#define CRC_BASE 0x58024C00U +#define BDMA_BASE 0x58025400U +#define DMAMUX2_BASE 0x58025800U +#define ADC3_BASE 0x58026000U +#define HSEM_BASE 0x58026400U + +/* APB4 Peripherals */ +#define SAI4_BASE 0x58005400U +#define IWDG1_BASE 0x58004800U +#define RTC_BASE 0x58004000U +#define VREF_BASE 0x58003C00U +#define COMP1_BASE 0x58003800U +#define LPTIM5_BASE 0x58003000U +#define LPTIM4_BASE 0x58002C00U +#define LPTIM3_BASE 0x58002800U +#define LPTIM2_BASE 0x58002400U +#define I2C4_BASE 0x58001C00U +#define SPI6_BASE 0x58001400U +#define LPUART1_BASE 0x58000C00U +#define SYSCFG_BASE 0x58000400U +#define EXTI_BASE 0x58000000U + +/* AHB3 Peripherals */ +#define DELAY_SDMMC1_BASE 0x52008000U +#define SDMMC1_BASE 0x52007000U +#define DELAY_QSPI_BASE 0x52006000U +#define QUADSPI_BASE 0x52005000U +#define FMC_BASE 0x52004000U +#define JPEG_BASE 0x52003000U +#define FLASH_MEM_INTERFACE_BASE 0x52002000U +#define CHROMART_BASE 0x52001000U +#define MDMA_BASE 0x52000000U +#define GPV_BASE 0x51000000U + +/* APB3 Peripherals */ +#define WWDG1_BASE 0x50003000U +#define LTDC_BASE 0x50001000U + +/* AHB2 Peripherals */ +#define DELAY_SDMMC2_BASE 0x48022800U +#define SDMMC2_BASE 0x48022400U +#define RNG_BASE 0x48021800U +#define HASH_BASE 0x48021400U +#define CRYPTO_BASE 0x48021000U +#define DCMI_BASE 0x48020000U + +/* AHB1 Peripherals */ +#define USB2_OTG_FS_BASE 0x40080000U +#define USB1_OTG_HS_BASE 0x40040000U +#define ETHERNET_MAC_BASE 0x40028000U +#define ADC1_ADC2_BASE 0x40022000U +#define DMAMUX1_BASE 0x40020800U +#define DMA2_BASE 0x40020400U +#define DMA1_BASE 0x40020000U + +/* APB2 Peripherals */ +#define HRTIM_BASE 0x40017400U +#define DFSDM1_BASE 0x40017000U +#define SAI3_BASE 0x40016000U +#define SAI2_BASE 0x40015C00U +#define SAI1_BASE 0x40015800U +#define SPI5_BASE 0x40015000U +#define TIM17_BASE 0x40014800U +#define TIM16_BASE 0x40014400U +#define TIM15_BASE 0x40014000U +#define SPI4_BASE 0x40013400U +#define SPI1_BASE 0x40013000U +#define USART6_BASE 0x40011400U +#define USART1_BASE 0x40011000U +#define TIM8_BASE 0x40010400U +#define TIM1_BASE 0x40010000U + +/* APB1 Peripherals */ +#define CAN_MSG_BASE 0x4000AC00U +#define CAN_CCU_BASE 0x4000A800U +#define FDCAN2_BASE 0x4000A400U +#define FDCAN1_BASE 0x4000A000U +#define MDIOS_BASE 0x40009400U +#define OPAMP_BASE 0x40009000U +#define SWPMI_BASE 0x40008800U +#define CRS_BASE 0x40008400U +#define UART8_BASE 0x40007C00U +#define UART7_BASE 0x40007800U +#define DAC_BASE 0x40007400U +#define HDMI_CEC_BASE 0x40006C00U +#define I2C3_BASE 0x40005C00U +#define I2C2_BASE 0x40005800U +#define I2C1_BASE 0x40005400U +#define UART5_BASE 0x40005000U +#define UART4_BASE 0x40004C00U +#define USART3_BASE 0x40004800U +#define USART2_BASE 0x40004400U +#define SPDIFRX1_BASE 0x40004000U +#define SPI3_BASE 0x40003C00U +#define SPI2_BASE 0x40003800U +#define LPTIM1_BASE 0x40002400U +#define TIM14_BASE 0x40002000U +#define TIM13_BASE 0x40001C00U +#define TIM12_BASE 0x40001800U +#define TIM7_BASE 0x40001400U +#define TIM6_BASE 0x40001000U +#define TIM5_BASE 0x40000C00U +#define TIM4_BASE 0x40000800U +#define TIM3_BASE 0x40000400U +#define TIM2_BASE 0x40000000U + +#endif diff --git a/include/libopencm3/stm32/h7/pwr.h b/include/libopencm3/stm32/h7/pwr.h new file mode 100644 index 00000000..8effcc42 --- /dev/null +++ b/include/libopencm3/stm32/h7/pwr.h @@ -0,0 +1,79 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2019 Brian Viele + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_PWR_H +#define LIBOPENCM3_PWR_H + +/**@{*/ + +/** @defgroup pwr_registers PWR Registers + * @ingroup STM32H_pwr_defines +@{*/ +/** Power control register. */ +#define PWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00) + +/** Power control/status register. */ +#define PWR_CSR1 MMIO32(POWER_CONTROL_BASE + 0x04) + +/** Power control register 2. */ +#define PWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x08) + +/** Power control register 3. */ +#define PWR_CR3 MMIO32(POWER_CONTROL_BASE + 0x0C) + +/** CPU Power control register 3. */ +#define PWR_CPUCR MMIO32(POWER_CONTROL_BASE + 0x10) + +/** D3 Domain Power Control register. */ +#define PWR_D3CR MMIO32(POWER_CONTROL_BASE + 0x18) + +/** Wakeup Domain Power Control register. */ +#define PWR_WKUPCR MMIO32(POWER_CONTROL_BASE + 0x20) + +/*@}*/ + +/** VOS[15:14]: Regulator voltage scaling output selection */ +#define PWR_CR1_SVOS_SHIFT 14 +#define PWR_CR1_SVOS_SCALE_3 (0x3) +#define PWR_CR1_SVOS_SCALE_4 (0x2) +#define PWR_CR1_SVOS_SCALE_5 (0x1) +#define PWR_CR1_SVOS_MASK (0x3) + +/** DBP[8]: Disable backup domain write protection. */ +#define PWR_CR1_DBP (1 << 8) + +/** PVDO: PVD output */ +#define PWR_CSR1_PVDO (1 << 4) + +/* --- Function prototypes ------------------------------------------------- */ +enum pwr_svos_scale { + PWR_SCALE3 = PWR_CR1_SVOS_SCALE_3 << PWR_CR1_SVOS_SHIFT, + PWR_SCALE4 = PWR_CR1_SVOS_SCALE_4 << PWR_CR1_SVOS_SHIFT, + PWR_SCALE5 = PWR_CR1_SVOS_SCALE_5 << PWR_CR1_SVOS_SHIFT, +}; + +BEGIN_DECLS + +void pwr_set_svos_scale(enum pwr_svos_scale scale); + +END_DECLS + +/**@}*/ + +#endif diff --git a/include/libopencm3/stm32/h7/rcc.h b/include/libopencm3/stm32/h7/rcc.h new file mode 100644 index 00000000..8beb90ad --- /dev/null +++ b/include/libopencm3/stm32/h7/rcc.h @@ -0,0 +1,430 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2019 Brian Viele + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_RCC_H +#define LIBOPENCM3_RCC_H + +#include + +/**@{*/ + +/* --- RCC registers ------------------------------------------------------- */ +#define RCC_CR MMIO32(RCC_BASE + 0x000) +#define RCC_CFGR MMIO32(RCC_BASE + 0x010) + +/** @addtogroup rcc_cr_values RCC_CR_VALUES + * @ingroup rcc_registers +@{*/ +#define RCC_CR_PLL3AIRDY (1 << 29) +#define RCC_CR_PLL3AION (1 << 28) +#define RCC_CR_PLL2RDY (1 << 27) +#define RCC_CR_PLL2ON (1 << 26) +#define RCC_CR_PLL1RDY (1 << 25) +#define RCC_CR_PLL1ON (1 << 24) +#define RCC_CR_HSECSSON (1 << 19) +#define RCC_CR_HSEBYP (1 << 18) +#define RCC_CR_HSERDY (1 << 17) +#define RCC_CR_HSEON (1 << 16) +#define RCC_CR_D2CKRDY (1 << 15) +#define RCC_CR_D1CKRDY (1 << 14) +#define RCC_CR_HSI48RDY (1 << 13) +#define RCC_CR_HSI48ON (1 << 12) +#define RCC_CR_CSIKERON (1 << 9) +#define RCC_CR_CSIRDY (1 << 8) +#define RCC_CR_CSION (1 << 7) +#define RCC_CR_HSIDIVF (1 << 5) +#define RCC_CR_HSIDIV_MASK (0x03) +#define RCC_CR_HSIDIV_SHIFT 3 +#define RCC_CR_HSIDIV(n) (((n) & RCC_CR_HSIDIV_MASK) << RCC_CR_HSIDIV_MASK) +#define RCC_CR_HSIRDY (1 << 2) +#define RCC_CR_HSIKERON (1 << 1) +#define RCC_CR_HSION (1 << 0) +/**@}*/ + +/** @addtogroup rcc_rstr_values RCC_RSTR_VALUES + * @ingroup rcc_registers +@{*/ +#define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x080) +#define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x084) +#define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x07C) +#define RCC_AHB4RSTR MMIO32(RCC_BASE + 0x088) +#define RCC_APB1LRSTR MMIO32(RCC_BASE + 0x090) +#define RCC_APB1HRSTR MMIO32(RCC_BASE + 0x094) +#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x098) +#define RCC_APB3RSTR MMIO32(RCC_BASE + 0x08C) +#define RCC_APB4RSTR MMIO32(RCC_BASE + 0x09C) +#define RCC_AHB1ENR MMIO32(RCC_BASE + 0x0D8) +#define RCC_AHB2ENR MMIO32(RCC_BASE + 0x0DC) +#define RCC_AHB3ENR MMIO32(RCC_BASE + 0x0D4) +#define RCC_AHB4ENR MMIO32(RCC_BASE + 0x0E0) +#define RCC_APB1LENR MMIO32(RCC_BASE + 0x0E8) +#define RCC_APB1HENR MMIO32(RCC_BASE + 0x0EC) +#define RCC_APB2ENR MMIO32(RCC_BASE + 0x0F0) +#define RCC_APB3ENR MMIO32(RCC_BASE + 0x0E4) +#define RCC_APB4ENR MMIO32(RCC_BASE + 0x0F4) +#define RCC_AHB1LPENR MMIO32(RCC_BASE + 0x100) +#define RCC_AHB2LPENR MMIO32(RCC_BASE + 0x104) +#define RCC_AHB4LPENR MMIO32(RCC_BASE + 0x108) +#define RCC_APB1LLPENR MMIO32(RCC_BASE + 0x110) +#define RCC_APB1HLPENR MMIO32(RCC_BASE + 0x114) +#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x118) +#define RCC_APB3LPENR MMIO32(RCC_BASE + 0x10C) +#define RCC_APB4LPENR MMIO32(RCC_BASE + 0x11C) +#define RCC_BDCR MMIO32(RCC_BASE + 0x70) +#define RCC_CSR MMIO32(RCC_BASE + 0x74) +#define RCC_SSCGR MMIO32(RCC_BASE + 0x80) +#define RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84) +#define RCC_PLLSAICFGR MMIO32(RCC_BASE + 0x88) +#define RCC_DCKCFGR1 MMIO32(RCC_BASE + 0x8C) +#define RCC_DCKCFGR2 MMIO32(RCC_BASE + 0x90) +/**@}*/ + +/** @addtogroup rcc_cfgr_values RCC_CFGR_VALUES + * @ingroup rcc_registers +@{*/ +/* MCO2: Microcontroller clock output 2 */ +#define RCC_CFGR_MCO2_MASK 0x7 +#define RCC_CFGR_MCO2_SHIFT 29 +#define RCC_CFGR_MCO2_SYSCLK 0x0 +#define RCC_CFGR_MCO2_PLL2 0x1 +#define RCC_CFGR_MCO2_HSE 0x2 +#define RCC_CFGR_MCO2_PLL1 0x3 +#define RCC_CFGR_MCO2_CSI 0x4 +#define RCC_CFGR_MCO2_LSI 0x5 + +/* MCO1/2PRE: MCO Prescalers */ +#define RCC_CFGR_MCOPRE_MASK 0xf +#define RCC_CFGR_MCO2PRE_SHIFT 25 +#define RCC_CFGR_MCO1PRE_SHIFT 18 +#define RCC_CFGR_MCOPRE_DIV_NONE 0x0 +#define RCC_CFGR_MCOPRE_DIV_BYP 0x1 +#define RCC_CFGR_MCOPRE_DIV_2 0x2 +#define RCC_CFGR_MCOPRE_DIV_3 0x3 +#define RCC_CFGR_MCOPRE_DIV_4 0x4 +/* Note: MCOPRE_DIV can go from 1 - 15 */ + +/* MCO1: Microcontroller clock output 1 */ +#define RCC_CFGR_MCO1_MASK 0x7 +#define RCC_CFGR_MCO1_SHIFT 22 +#define RCC_CFGR_MCO1_HSI 0x0 +#define RCC_CFGR_MCO1_LSE 0x1 +#define RCC_CFGR_MCO1_HSE 0x2 +#define RCC_CFGR_MCO1_PLL1 0x3 +#define RCC_CFGR_MCO1_HSI48 0x4 +#define RCC_CFGR_MCO_SHIFT RCC_CFGR_MCO1_SHIFT +#define RCC_CFGR_MCO_MASK RCC_CFGR_MCO1_MASK + +/* RTCPRE: HSE division factor for RTC clock */ +#define RCC_CFGR_RTCPRE_SHIFT 8 +#define RCC_CFGR_RTCPRE_MASK 0x3f + +/* SWS: System clock switch status */ +#define RCC_CFGR_SWS_SHIFT 3 +#define RCC_CFGR_SWS_MASK 0x7 +#define RCC_CFGR_SWS_HSI 0x0 +#define RCC_CFGR_SWS_CSI 0x1 +#define RCC_CFGR_SWS_HSE 0x2 +#define RCC_CFGR_SWS_PLL1 0x3 + +/* SW: System clock switch */ +#define RCC_CFGR_SW_SHIFT 0 +#define RCC_CFGR_SW_MASK 0x7 +#define RCC_CFGR_SW_HSI 0x0 +#define RCC_CFGR_SW_CSI 0x1 +#define RCC_CFGR_SW_HSE 0x2 +#define RCC_CFGR_SW_PLL1 0x3 +/**@}*/ + + +/** @addtogroup rcc_bdcr_values RCC_BDCR_VALUES + * @ingroup rcc_registers +@{*/ +#define RCC_BDCR_BDRST (1 << 16) +#define RCC_BDCR_RTCEN (1 << 15) +#define RCC_BDCR_RTCSEL_MASK 0x3 +#define RCC_BDCR_RTCSEL_SHIFT 8 +#define RCC_BDCR_RTCSEL_NONE 0 +#define RCC_BDCR_RTCSEL_LSE 1 +#define RCC_BDCR_RTCSEL_LSI 2 +#define RCC_BDCR_RTCSEL_HSE 3 +#define RCC_BDCR_LSEDRV_MASK 0x3 +#define RCC_BDCR_LSEDRV_SHIFT 3 +#define RCC_BDCR_LSEDRV_LOW 0 +#define RCC_BDCR_LSEDRV_MEDH 1 /* good job st */ +#define RCC_BDCR_LSEDRV_MEDL 2 +#define RCC_BDCR_LSEDRV_HIGH 3 +#define RCC_BDCR_LSEBYP (1 << 2) +#define RCC_BDCR_LSERDY (1 << 1) +#define RCC_BDCR_LSEON (1 << 0) +/**@}*/ + +/** @addtogroup rcc_bdcr_values RCC_CSR_VALUES + * @ingroup rcc_registers +@{*/ +#define RCC_CSR_LSIRDY (1 << 1) +#define RCC_CSR_LSION (1 << 0) +/**@}*/ + +extern uint32_t rcc_ahb_frequency; +extern uint32_t rcc_apb1_frequency; +extern uint32_t rcc_apb2_frequency; + +enum rcc_osc { + RCC_PLL, + RCC_HSE, + RCC_HSI, + RCC_LSE, + RCC_LSI +}; + +#define _REG_BIT(base, bit) (((base) << 5) + (bit)) + +enum rcc_periph_clken { + /* AHB1 peripherals */ + RCC_DMA1 = _REG_BIT(0xD8, 0), + RCC_DMA2 = _REG_BIT(0xD8, 1), + RCC_ADC12 = _REG_BIT(0xD8, 5), + RCC_ETH1MAC = _REG_BIT(0xD8, 15), + RCC_ETH1TX = _REG_BIT(0xD8, 16), + RCC_ETH1RX = _REG_BIT(0xD8, 17), + RCC_USB2OTGHSULPIEN = _REG_BIT(0xD8, 18), + RCC_USB1OTGHSEN = _REG_BIT(0xD8, 25), + RCC_USB1OTGHSULPIEN = _REG_BIT(0xD8, 26), + RCC_USB2OTGHSEN = _REG_BIT(0xD8, 27), + + /* AHB2 peripherals */ + RCC_DCMI = _REG_BIT(0xDC, 0), + RCC_CRYP = _REG_BIT(0xDC, 4), + RCC_HASH = _REG_BIT(0xDC, 5), + RCC_RNG = _REG_BIT(0xDC, 6), + RCC_SDMMC2 = _REG_BIT(0xDC, 9), + RCC_SRAM1 = _REG_BIT(0xDC, 29), + RCC_SRAM2 = _REG_BIT(0xDC, 30), + RCC_SRAM3 = _REG_BIT(0xDC, 31), + + /* AHB3 peripherals */ + RCC_MDMA = _REG_BIT(0xD4, 0), + RCC_DMA2D = _REG_BIT(0xD4, 4), + RCC_JPGDEC = _REG_BIT(0xD4, 5), + RCC_FMC = _REG_BIT(0xD4, 12), + RCC_QSPI = _REG_BIT(0xD4, 14), + RCC_SDMMC1 = _REG_BIT(0xD4, 16), + + /* AHB4 peripherals*/ + RCC_GPIOA = _REG_BIT(0xE0, 0), + RCC_GPIOB = _REG_BIT(0xE0, 1), + RCC_GPIOC = _REG_BIT(0xE0, 2), + RCC_GPIOD = _REG_BIT(0xE0, 3), + RCC_GPIOE = _REG_BIT(0xE0, 4), + RCC_GPIOF = _REG_BIT(0xE0, 5), + RCC_GPIOG = _REG_BIT(0xE0, 6), + RCC_GPIOH = _REG_BIT(0xE0, 7), + RCC_GPIOI = _REG_BIT(0xE0, 8), + RCC_GPIOJ = _REG_BIT(0xE0, 9), + RCC_GPIOK = _REG_BIT(0xE0, 10), + RCC_CRC = _REG_BIT(0xE0, 19), + RCC_BDMA = _REG_BIT(0xE0, 21), + RCC_ADC3 = _REG_BIT(0xE0, 24), + RCC_HSEM = _REG_BIT(0xE0, 25), + RCC_BKPSRAM = _REG_BIT(0xE0, 28), + + /* APB1L peripherals*/ + RCC_TIM2 = _REG_BIT(0xE8, 0), + RCC_TIM3 = _REG_BIT(0xE8, 1), + RCC_TIM4 = _REG_BIT(0xE8, 2), + RCC_TIM5 = _REG_BIT(0xE8, 3), + RCC_TIM6 = _REG_BIT(0xE8, 4), + RCC_TIM7 = _REG_BIT(0xE8, 5), + RCC_TIM12 = _REG_BIT(0xE8, 6), + RCC_TIM13 = _REG_BIT(0xE8, 7), + RCC_TIM14 = _REG_BIT(0xE8, 8), + RCC_LPTIM1 = _REG_BIT(0xE8, 9), + RCC_SPI2 = _REG_BIT(0xE8, 14), + RCC_SPI3 = _REG_BIT(0xE8, 15), + RCC_SPDIFRX = _REG_BIT(0xE8, 16), + RCC_USART2 = _REG_BIT(0xE8, 17), + RCC_USART3 = _REG_BIT(0xE8, 18), + RCC_UART4 = _REG_BIT(0xE8, 19), + RCC_UART5 = _REG_BIT(0xE8, 20), + RCC_I2C1 = _REG_BIT(0xE8, 21), + RCC_I2C2 = _REG_BIT(0xE8, 22), + RCC_I2C3 = _REG_BIT(0xE8, 23), + RCC_CEC = _REG_BIT(0xE8, 27), + RCC_DAC = _REG_BIT(0xE8, 29), + RCC_UART7 = _REG_BIT(0xE8, 30), + RCC_UART8 = _REG_BIT(0xE8, 31), + + /* APB1H peripherals*/ + RCC_CRS = _REG_BIT(0xEC, 1), + RCC_SWP = _REG_BIT(0xEC, 2), + RCC_OPAMP = _REG_BIT(0xEC, 4), + RCC_MDIO = _REG_BIT(0xEC, 5), + RCC_FDCAN = _REG_BIT(0xEC, 8), + + /* APB2 peripherals */ + RCC_TIM1 = _REG_BIT(0xF0, 0), + RCC_TIM8 = _REG_BIT(0xF0, 1), + RCC_USART1 = _REG_BIT(0xF0, 4), + RCC_USART6 = _REG_BIT(0xF0, 5), + RCC_SPI1 = _REG_BIT(0xF0, 12), + RCC_SPI4 = _REG_BIT(0xF0, 13), + RCC_TIM15 = _REG_BIT(0xF0, 16), + RCC_TIM16 = _REG_BIT(0xF0, 17), + RCC_TIM17 = _REG_BIT(0xF0, 18), + RCC_SPI5 = _REG_BIT(0xF0, 20), + RCC_SAI1 = _REG_BIT(0xF0, 22), + RCC_SAI2 = _REG_BIT(0xF0, 23), + RCC_SAI3 = _REG_BIT(0xF0, 24), + RCC_DFSDM = _REG_BIT(0xF0, 28), + RCC_HRTIM = _REG_BIT(0xF0, 29), + + /* APB3 peripherals */ + RCC_LTDCEN = _REG_BIT(0xE4, 3), + RCC_WWDG1EN = _REG_BIT(0xE4, 6), + + /* APB4 peripherals */ + RCC_SYSCFG = _REG_BIT(0xF4, 1), + RCC_LPUART1 = _REG_BIT(0xF4, 3), + RCC_SPI6 = _REG_BIT(0xF4, 5), + RCC_I2C4 = _REG_BIT(0xF4, 7), + RCC_LPTIM2 = _REG_BIT(0xF4, 9), + RCC_LPTIM3 = _REG_BIT(0xF4, 10), + RCC_LPTIM4 = _REG_BIT(0xF4, 11), + RCC_LPTIM5 = _REG_BIT(0xF4, 12), + RCC_COMP12 = _REG_BIT(0xF4, 14), + RCC_VREF = _REG_BIT(0xF4, 15), + RCC_RTCAPB = _REG_BIT(0xF4, 16), + RCC_SAI4 = _REG_BIT(0xF4, 21), +}; + +enum rcc_periph_rst { + /* AHB1 peripherals */ + RST_DMA1 = _REG_BIT(0x80, 0), + RST_DMA2 = _REG_BIT(0x80, 1), + RST_ADC12 = _REG_BIT(0x80, 5), + RST_ETH1MAC = _REG_BIT(0x80, 15), + RST_USB1OTGRST = _REG_BIT(0x80, 25), + RST_USB2OTGRST = _REG_BIT(0x80, 27), + + /* AHB2 peripherals */ + RST_DCMI = _REG_BIT(0xDC, 0), + RST_CRYP = _REG_BIT(0xDC, 4), + RST_HASH = _REG_BIT(0xDC, 5), + RST_RNG = _REG_BIT(0xDC, 6), + RST_SDMMC2 = _REG_BIT(0xDC, 9), + + /* AHB3 peripherals */ + RST_MDMA = _REG_BIT(0x7C, 0), + RST_DMA2D = _REG_BIT(0x7C, 4), + RST_JPGDEC = _REG_BIT(0x7C, 5), + RST_FMC = _REG_BIT(0x7C, 12), + RST_QSPI = _REG_BIT(0x7C, 14), + RST_SDMMC1 = _REG_BIT(0x7C, 16), + + /* AHB4 peripherals*/ + RST_GPIOA = _REG_BIT(0x88, 0), + RST_GPIOB = _REG_BIT(0x88, 1), + RST_GPIOC = _REG_BIT(0x88, 2), + RST_GPIOD = _REG_BIT(0x88, 3), + RST_GPIOE = _REG_BIT(0x88, 4), + RST_GPIOF = _REG_BIT(0x88, 5), + RST_GPIOG = _REG_BIT(0x88, 6), + RST_GPIOH = _REG_BIT(0x88, 7), + RST_GPIOI = _REG_BIT(0x88, 8), + RST_GPIOJ = _REG_BIT(0x88, 9), + RST_GPIOK = _REG_BIT(0x88, 10), + RST_CRC = _REG_BIT(0x88, 19), + RST_BDMA = _REG_BIT(0x88, 21), + RST_ADC3 = _REG_BIT(0x88, 24), + RST_HSEM = _REG_BIT(0x88, 25), + + /* APB1L peripherals*/ + RST_TIM2 = _REG_BIT(0x90, 0), + RST_TIM3 = _REG_BIT(0x90, 1), + RST_TIM4 = _REG_BIT(0x90, 2), + RST_TIM5 = _REG_BIT(0x90, 3), + RST_TIM6 = _REG_BIT(0x90, 4), + RST_TIM7 = _REG_BIT(0x90, 5), + RST_TIM12 = _REG_BIT(0x90, 6), + RST_TIM13 = _REG_BIT(0x90, 7), + RST_TIM14 = _REG_BIT(0x90, 8), + RST_LPTIM1 = _REG_BIT(0x90, 9), + RST_SPI2 = _REG_BIT(0x90, 14), + RST_SPI3 = _REG_BIT(0x90, 15), + RST_SPDIFRX = _REG_BIT(0x90, 16), + RST_USART2 = _REG_BIT(0x90, 17), + RST_USART3 = _REG_BIT(0x90, 18), + RST_UART4 = _REG_BIT(0x90, 19), + RST_UART5 = _REG_BIT(0x90, 20), + RST_I2C1 = _REG_BIT(0x90, 21), + RST_I2C2 = _REG_BIT(0x90, 22), + RST_I2C3 = _REG_BIT(0x90, 23), + RST_CEC = _REG_BIT(0x90, 27), + RST_DAC = _REG_BIT(0x90, 29), + RST_UART7 = _REG_BIT(0x90, 30), + RST_UART8 = _REG_BIT(0x90, 31), + + /* APB1H peripherals*/ + RST_CRS = _REG_BIT(0x94, 1), + RST_SWP = _REG_BIT(0x94, 2), + RST_OPAMP = _REG_BIT(0x94, 4), + RST_MDIO = _REG_BIT(0x94, 5), + RST_FDCAN = _REG_BIT(0x94, 8), + + /* APB2 peripherals */ + RST_TIM1 = _REG_BIT(0x98, 0), + RST_TIM8 = _REG_BIT(0x98, 1), + RST_USART1 = _REG_BIT(0x98, 4), + RST_USART6 = _REG_BIT(0x98, 5), + RST_SPI1 = _REG_BIT(0x98, 12), + RST_SPI4 = _REG_BIT(0x98, 13), + RST_TIM15 = _REG_BIT(0x98, 16), + RST_TIM16 = _REG_BIT(0x98, 17), + RST_TIM17 = _REG_BIT(0x98, 18), + RST_SPI5 = _REG_BIT(0x98, 20), + RST_SAI1 = _REG_BIT(0x98, 22), + RST_SAI2 = _REG_BIT(0x98, 23), + RST_SAI3 = _REG_BIT(0x98, 24), + RST_DFSDM = _REG_BIT(0x98, 28), + RST_HRTIM = _REG_BIT(0x98, 29), + + /* APB3 peripherals */ + RST_LTDCRST = _REG_BIT(0x8C, 3), + + /* APB4 peripherals */ + RST_SYSCFG = _REG_BIT(0x9C, 1), + RST_LPUART1 = _REG_BIT(0x9C, 3), + RST_SPI6 = _REG_BIT(0x9C, 5), + RST_I2C4 = _REG_BIT(0x9C, 7), + RST_LPTIM2 = _REG_BIT(0x9C, 9), + RST_LPTIM3 = _REG_BIT(0x9C, 10), + RST_LPTIM4 = _REG_BIT(0x9C, 11), + RST_LPTIM5 = _REG_BIT(0x9C, 12), + RST_COMP12 = _REG_BIT(0x9C, 14), + RST_VREF = _REG_BIT(0x9C, 15), + RST_SAI4 = _REG_BIT(0x9C, 21), +}; + +#undef _REG_BIT + +#include + +/**@}*/ + +#endif diff --git a/include/libopencm3/stm32/h7/spi.h b/include/libopencm3/stm32/h7/spi.h new file mode 100644 index 00000000..f1697b55 --- /dev/null +++ b/include/libopencm3/stm32/h7/spi.h @@ -0,0 +1,24 @@ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_SPI_H +#define LIBOPENCM3_SPI_H + +#include + +#endif + diff --git a/include/libopencm3/stm32/h7/timer.h b/include/libopencm3/stm32/h7/timer.h new file mode 100644 index 00000000..9dd27b9b --- /dev/null +++ b/include/libopencm3/stm32/h7/timer.h @@ -0,0 +1,27 @@ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_TIMER_H +#define LIBOPENCM3_TIMER_H + +#include + +BEGIN_DECLS + +END_DECLS + +#endif diff --git a/include/libopencm3/stm32/h7/usart.h b/include/libopencm3/stm32/h7/usart.h new file mode 100644 index 00000000..991a645e --- /dev/null +++ b/include/libopencm3/stm32/h7/usart.h @@ -0,0 +1,60 @@ +/** @defgroup usart_defines USART Defines + * + * @brief Defined Constants and Types for the STM32H7xx USART + * + * @ingroup STM32H7xx_defines + * + * @version 1.0.0 + * + * @date 6 November 2019 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_USART_H +#define LIBOPENCM3_USART_H + +#include +#include + +/**@{*/ + +/** @defgroup usart_reg_base USART register base addresses + * Holds all the U(S)ART peripherals supported. + * @{ + */ +#define USART1 USART1_BASE +#define USART2 USART2_BASE +#define USART3 USART3_BASE +#define UART4 UART4_BASE +#define UART5 UART5_BASE +#define USART6 USART6_BASE +#define UART7 UART7_BASE +#define UART8 UART8_BASE +/**@}*/ + +BEGIN_DECLS + +END_DECLS + +/**@}*/ + +#endif + diff --git a/include/libopencm3/stm32/memorymap.h b/include/libopencm3/stm32/memorymap.h index a5b64138..679fbd70 100644 --- a/include/libopencm3/stm32/memorymap.h +++ b/include/libopencm3/stm32/memorymap.h @@ -40,6 +40,8 @@ # include #elif defined(STM32G0) # include +#elif defined(STM32H7) +# include #elif defined(GD32F1X0) # include #else diff --git a/include/libopencm3/stm32/pwr.h b/include/libopencm3/stm32/pwr.h index 066dec65..69547eef 100644 --- a/include/libopencm3/stm32/pwr.h +++ b/include/libopencm3/stm32/pwr.h @@ -40,6 +40,8 @@ # include #elif defined(STM32G0) # include +#elif defined(STM32H7) +# include #else # error "stm32 family not defined." #endif diff --git a/include/libopencm3/stm32/rcc.h b/include/libopencm3/stm32/rcc.h index 0b520173..1a3d0d59 100644 --- a/include/libopencm3/stm32/rcc.h +++ b/include/libopencm3/stm32/rcc.h @@ -40,6 +40,8 @@ # include #elif defined(STM32G0) # include +#elif defined(STM32H7) +# include #elif defined(GD32F1X0) # include #else diff --git a/include/libopencm3/stm32/spi.h b/include/libopencm3/stm32/spi.h index f4082bc9..c0a27301 100644 --- a/include/libopencm3/stm32/spi.h +++ b/include/libopencm3/stm32/spi.h @@ -40,6 +40,8 @@ # include #elif defined(STM32G0) # include +#elif defined(STM32H7) +# include #else # error "stm32 family not defined." #endif diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h index 4d1afc7a..32ddd157 100644 --- a/include/libopencm3/stm32/timer.h +++ b/include/libopencm3/stm32/timer.h @@ -42,6 +42,8 @@ # include #elif defined(STM32G0) # include +#elif defined(STM32H7) +# include #else # error "stm32 family not defined." #endif diff --git a/include/libopencm3/stm32/usart.h b/include/libopencm3/stm32/usart.h index 7b22d4bf..c6cb5f96 100644 --- a/include/libopencm3/stm32/usart.h +++ b/include/libopencm3/stm32/usart.h @@ -40,6 +40,8 @@ # include #elif defined(STM32G0) # include +#elif defined(STM32H7) +# include #else # error "stm32 family not defined." #endif diff --git a/lib/dispatch/vector_nvic.c b/lib/dispatch/vector_nvic.c index cf545b84..93da5b4b 100644 --- a/lib/dispatch/vector_nvic.c +++ b/lib/dispatch/vector_nvic.c @@ -18,6 +18,8 @@ # include "../stm32/l4/vector_nvic.c" #elif defined(STM32G0) # include "../stm32/g0/vector_nvic.c" +#elif defined(STM32H7) +# include "../stm32/h7/vector_nvic.c" #elif defined(GD32F1X0) # include "../gd32/f1x0/vector_nvic.c" diff --git a/lib/stm32/h7/Makefile b/lib/stm32/h7/Makefile new file mode 100644 index 00000000..fa17af8c --- /dev/null +++ b/lib/stm32/h7/Makefile @@ -0,0 +1,52 @@ +## +## This file is part of the libopencm3 project. +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +LIBNAME = libopencm3_stm32h7 +SRCLIBDIR ?= ../.. + +CC = $(PREFIX)gcc +AR = $(PREFIX)ar + +# STM32H7 supports double precision FPU +FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv5-d16 + +TGT_CFLAGS = -Os \ + -Wall -Wextra -Wimplicit-function-declaration \ + -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ + -Wundef -Wshadow \ + -I../../../include -fno-common \ + -mcpu=cortex-m7 -mthumb $(FP_FLAGS) \ + -Wstrict-prototypes \ + -ffunction-sections -fdata-sections -MD -DSTM32H7 +TGT_CFLAGS += $(DEBUG_FLAGS) +TGT_CFLAGS += $(STANDARD_FLAGS) + +ARFLAGS = rcs + +OBJS += dac_common_all.o +OBJS += flash_common_all.o flash_common_f.o flash_common_f24.o +OBJS += fmc_common_f47.o +OBJS += gpio_common_all.o gpio_common_f0234.o +OBJS += pwr.o rcc.o +OBJS += rcc_common_all.o +OBJS += spi_common_all.o spi_common_v2.o +OBJS += timer_common_all.o +OBJS += usart_common_all.o usart_common_v2.o + +VPATH += ../../usb:../:../../cm3:../common + +include ../../Makefile.include diff --git a/lib/stm32/h7/pwr.c b/lib/stm32/h7/pwr.c new file mode 100644 index 00000000..4afeb909 --- /dev/null +++ b/lib/stm32/h7/pwr.c @@ -0,0 +1,50 @@ +/** @defgroup pwr_file PWR peripheral API + * + * @ingroup peripheral_apis + * + * @brief libopencm3 STM32H7xx Power Control + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2011 Stephen Caudle + * @author @htmlonly © @endhtmlonly 2017 Matthew Lai + * + * @date 12 March 2017 + * + * This library supports the power control system for the + * STM32H7 series of ARM Cortex Microcontrollers by ST Microelectronics. + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Stephen Caudle + * Copyright (C) 2017 Matthew Lai + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +/**@{*/ + +void pwr_set_svos_scale(enum pwr_svos_scale scale) +{ + uint32_t pwr_cr1_reg = PWR_CR1; + pwr_cr1_reg = (pwr_cr1_reg & ~PWR_CR1_SVOS_MASK) | scale; + PWR_CR1 = pwr_cr1_reg; +} + +/**@}*/ \ No newline at end of file diff --git a/lib/stm32/h7/rcc.c b/lib/stm32/h7/rcc.c new file mode 100644 index 00000000..5069cc88 --- /dev/null +++ b/lib/stm32/h7/rcc.c @@ -0,0 +1,21 @@ +/** @defgroup rcc_file RCC peripheral API + * + * @ingroup peripheral_apis + * This library supports the Reset and Clock Control System in the STM32 series + * of ARM Cortex Microcontrollers by ST Microelectronics. + * + * LGPL License Terms @ref lgpl_license + */ + +#include +#include +#include +#include + +/**@{*/ + +uint32_t rcc_ahb_frequency = 64000000; +uint32_t rcc_apb1_frequency = 64000000; +uint32_t rcc_apb2_frequency = 64000000; + +/**@}*/ diff --git a/lib/stm32/h7/vector_chipset.c b/lib/stm32/h7/vector_chipset.c new file mode 100644 index 00000000..145be057 --- /dev/null +++ b/lib/stm32/h7/vector_chipset.c @@ -0,0 +1,27 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2011 Fergus Noble + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +static void pre_main(void) +{ + /* Enable access to Floating-Point coprocessor. */ + SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11); +}