mcu
/
libopencm3
mirror of https://github.com/libopencm3/libopencm3.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
Browse Source

stm32l1: rcc: drop magic numbers in favour of defines 

Use the same mask/shift defines as other families.
pull/688/head
Karl Palsson 8 years ago
parent
cf7d0a08ca
commit
543ac0f23c
2 changed files with 18 additions and 10 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 8
      include/libopencm3/stm32/l1/rcc.h
  2. 20
      lib/stm32/l1/rcc.c

8
include/libopencm3/stm32/l1/rcc.h
View File

@ -164,6 +164,8 @@
#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5
#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6
#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7
#define RCC_CFGR_PPRE2_MASK 0x7
#define RCC_CFGR_PPRE2_SHIFT 11
/* PPRE1: APB low-speed prescaler (APB1) */
#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0
@ -171,6 +173,8 @@
#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5
#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6
#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7
#define RCC_CFGR_PPRE1_MASK 0x7
#define RCC_CFGR_PPRE1_SHIFT 8
/* HPRE: AHB prescaler */
#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0
@ -182,6 +186,8 @@
#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd
#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe
#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf
#define RCC_CFGR_HPRE_MASK 0xf
#define RCC_CFGR_HPRE_SHIFT 4
/* SWS: System clock switch status */
#define RCC_CFGR_SWS_SYSCLKSEL_MSICLK 0x0
@ -196,6 +202,8 @@
#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x1
#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x2
#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x3
#define RCC_CFGR_SW_MASK 0x3
#define RCC_CFGR_SW_SHIFT 0
/* --- RCC_CIR values ------------------------------------------------------ */

20
lib/stm32/l1/rcc.c
View File

@ -376,8 +376,8 @@ void rcc_set_sysclk_source(uint32_t clk)
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 1) | (1 << 0));
RCC_CFGR = (reg32 | clk);
reg32 &= ~(RCC_CFGR_SW_MASK << RCC_CFGR_SW_SHIFT);
RCC_CFGR = (reg32 | clk << RCC_CFGR_SW_SHIFT);
}
void rcc_set_pll_configuration(uint32_t source, uint32_t multiplier,
@ -409,8 +409,8 @@ void rcc_set_ppre2(uint32_t ppre2)
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 13) | (1 << 12) | (1 << 11));
RCC_CFGR = (reg32 | (ppre2 << 11));
reg32 &= ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
RCC_CFGR = (reg32 | (ppre2 << RCC_CFGR_PPRE2_SHIFT));
}
void rcc_set_ppre1(uint32_t ppre1)
@ -418,8 +418,8 @@ void rcc_set_ppre1(uint32_t ppre1)
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 10) | (1 << 9) | (1 << 8));
RCC_CFGR = (reg32 | (ppre1 << 8));
reg32 &= ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
RCC_CFGR = (reg32 | (ppre1 << RCC_CFGR_PPRE1_SHIFT));
}
void rcc_set_hpre(uint32_t hpre)
@ -427,8 +427,8 @@ void rcc_set_hpre(uint32_t hpre)
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
RCC_CFGR = (reg32 | (hpre << 4));
reg32 &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
RCC_CFGR = (reg32 | (hpre << RCC_CFGR_HPRE_SHIFT));
}
void rcc_set_rtcpre(uint32_t rtcpre)
@ -436,8 +436,8 @@ void rcc_set_rtcpre(uint32_t rtcpre)
uint32_t reg32;
reg32 = RCC_CR;
reg32 &= ~((1 << 30) | (1 << 29));
RCC_CR = (reg32 | (rtcpre << 29));
reg32 &= ~(RCC_CR_RTCPRE_MASK << RCC_CR_RTCPRE_SHIFT);
RCC_CR = (reg32 | (rtcpre << RCC_CR_RTCPRE_SHIFT));
}
uint32_t rcc_system_clock_source(void)

Write Preview
Loading…
Cancel
Save