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Fix bug with F4 clock settings, change HPRE to PPRE.

pull/2/merge
Fergus Noble 13 years ago
committed by Uwe Hermann
parent
fae83c43c1
commit
5dce4172a8
1 changed files with 4 additions and 4 deletions
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  1. 8
      lib/stm32/f4/rcc.c

8
lib/stm32/f4/rcc.c
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@ -35,8 +35,8 @@ const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] =
.pllp = 2, .pllp = 2,
.pllq = 5, .pllq = 5,
.hpre = RCC_CFGR_HPRE_DIV_NONE, .hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_HPRE_DIV_4, .ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_HPRE_DIV_2, .ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1, .power_save = 1,
.flash_config = FLASH_ICE | FLASH_DCE | FLASH_LATENCY_3WS, .flash_config = FLASH_ICE | FLASH_DCE | FLASH_LATENCY_3WS,
.apb1_frequency = 30000000, .apb1_frequency = 30000000,
@ -48,8 +48,8 @@ const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] =
.pllp = 2, .pllp = 2,
.pllq = 7, .pllq = 7,
.hpre = RCC_CFGR_HPRE_DIV_NONE, .hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_HPRE_DIV_4, .ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_HPRE_DIV_2, .ppre2 = RCC_CFGR_PPRE_DIV_2,
.flash_config = FLASH_ICE | FLASH_DCE | FLASH_LATENCY_5WS, .flash_config = FLASH_ICE | FLASH_DCE | FLASH_LATENCY_5WS,
.apb1_frequency = 42000000, .apb1_frequency = 42000000,
.apb2_frequency = 84000000, .apb2_frequency = 84000000,

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