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f2/dma.h: Whitespace and coding-style fixes.

pull/2/merge
Uwe Hermann 13 years ago
parent
9949b5dcf4
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5f82f28d01
1 changed files with 308 additions and 308 deletions
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  1. 616
      include/libopencm3/stm32/f2/dma.h

616
include/libopencm3/stm32/f2/dma.h
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@ -30,347 +30,347 @@
#define DMA2 DMA2_BASE #define DMA2 DMA2_BASE
/* DMA stream base addresses (for convenience) */ /* DMA stream base addresses (for convenience) */
#define DMA_STREAM(port, n) (port + 0x10 + 24*n) #define DMA_STREAM(port, n) ((port) + 0x10 + (24 * (n)))
#define DMA1_STREAM(n) DMA_STREAM(DMA1, n) #define DMA1_STREAM(n) DMA_STREAM(DMA1, n)
#define DMA2_STREAM(n) DMA_STREAM(DMA2, n) #define DMA2_STREAM(n) DMA_STREAM(DMA2, n)
#define DMA1_STREAM0 DMA1_STREAM(0) #define DMA1_STREAM0 DMA1_STREAM(0)
#define DMA1_STREAM1 DMA1_STREAM(1) #define DMA1_STREAM1 DMA1_STREAM(1)
#define DMA1_STREAM2 DMA1_STREAM(2) #define DMA1_STREAM2 DMA1_STREAM(2)
#define DMA1_STREAM3 DMA1_STREAM(3) #define DMA1_STREAM3 DMA1_STREAM(3)
#define DMA1_STREAM4 DMA1_STREAM(4) #define DMA1_STREAM4 DMA1_STREAM(4)
#define DMA1_STREAM5 DMA1_STREAM(5) #define DMA1_STREAM5 DMA1_STREAM(5)
#define DMA1_STREAM6 DMA1_STREAM(6) #define DMA1_STREAM6 DMA1_STREAM(6)
#define DMA1_STREAM7 DMA1_STREAM(7) #define DMA1_STREAM7 DMA1_STREAM(7)
#define DMA2_STREAM0 DMA2_STREAM(0) #define DMA2_STREAM0 DMA2_STREAM(0)
#define DMA2_STREAM1 DMA2_STREAM(1) #define DMA2_STREAM1 DMA2_STREAM(1)
#define DMA2_STREAM2 DMA2_STREAM(2) #define DMA2_STREAM2 DMA2_STREAM(2)
#define DMA2_STREAM3 DMA2_STREAM(3) #define DMA2_STREAM3 DMA2_STREAM(3)
#define DMA2_STREAM4 DMA2_STREAM(4) #define DMA2_STREAM4 DMA2_STREAM(4)
#define DMA2_STREAM5 DMA2_STREAM(5) #define DMA2_STREAM5 DMA2_STREAM(5)
#define DMA2_STREAM6 DMA2_STREAM(6) #define DMA2_STREAM6 DMA2_STREAM(6)
#define DMA2_STREAM7 DMA2_STREAM(7) #define DMA2_STREAM7 DMA2_STREAM(7)
/* --- DMA controller registers -------------------------------------------- */ /* --- DMA controller registers -------------------------------------------- */
/* DMA low interrupt status register (DMAx_LISR) */ /* DMA low interrupt status register (DMAx_LISR) */
#define DMA_LISR(port) MMIO32(port + 0x00) #define DMA_LISR(port) MMIO32(port + 0x00)
#define DMA1_LISR DMA_LISR(DMA1) #define DMA1_LISR DMA_LISR(DMA1)
#define DMA2_LISR DMA_LISR(DMA2) #define DMA2_LISR DMA_LISR(DMA2)
/* DMA high interrupt status register (DMAx_HISR) */ /* DMA high interrupt status register (DMAx_HISR) */
#define DMA_HISR(port) MMIO32(port + 0x04) #define DMA_HISR(port) MMIO32(port + 0x04)
#define DMA1_HISR DMA_HISR(DMA1) #define DMA1_HISR DMA_HISR(DMA1)
#define DMA2_HISR DMA_HISR(DMA2) #define DMA2_HISR DMA_HISR(DMA2)
/* DMA low interrupt flag clear register (DMAx_LIFCR) */ /* DMA low interrupt flag clear register (DMAx_LIFCR) */
#define DMA_LIFCR(port) MMIO32(port + 0x08) #define DMA_LIFCR(port) MMIO32(port + 0x08)
#define DMA1_LIFCR DMA_LIFCR(DMA1) #define DMA1_LIFCR DMA_LIFCR(DMA1)
#define DMA2_LIFCR DMA_LIFCR(DMA2) #define DMA2_LIFCR DMA_LIFCR(DMA2)
/* DMA high interrupt flag clear register (DMAx_HIFCR) */ /* DMA high interrupt flag clear register (DMAx_HIFCR) */
#define DMA_HIFCR(port) MMIO32(port + 0x0C) #define DMA_HIFCR(port) MMIO32(port + 0x0C)
#define DMA1_HIFCR DMA_HIFCR(DMA1) #define DMA1_HIFCR DMA_HIFCR(DMA1)
#define DMA2_HIFCR DMA_HIFCR(DMA2) #define DMA2_HIFCR DMA_HIFCR(DMA2)
/* --- DMA stream registers ------------------------------------------------ */ /* --- DMA stream registers ------------------------------------------------ */
/* DMA Stream x configuration register (DMA_SxCR) */ /* DMA Stream x configuration register (DMA_SxCR) */
#define DMA_SCR(port, n) MMIO32(DMA_STREAM(port, n) + 0x00) #define DMA_SCR(port, n) MMIO32(DMA_STREAM(port, n) + 0x00)
#define DMA1_SCR(n) DMA_SCR(DMA1, n) #define DMA1_SCR(n) DMA_SCR(DMA1, n)
#define DMA2_SCR(n) DMA_SCR(DMA2, n) #define DMA2_SCR(n) DMA_SCR(DMA2, n)
#define DMA1_S0CR DMA1_SCR(0) #define DMA1_S0CR DMA1_SCR(0)
#define DMA1_S1CR DMA1_SCR(1) #define DMA1_S1CR DMA1_SCR(1)
#define DMA1_S2CR DMA1_SCR(2) #define DMA1_S2CR DMA1_SCR(2)
#define DMA1_S3CR DMA1_SCR(3) #define DMA1_S3CR DMA1_SCR(3)
#define DMA1_S4CR DMA1_SCR(4) #define DMA1_S4CR DMA1_SCR(4)
#define DMA1_S5CR DMA1_SCR(5) #define DMA1_S5CR DMA1_SCR(5)
#define DMA1_S6CR DMA1_SCR(6) #define DMA1_S6CR DMA1_SCR(6)
#define DMA1_S7CR DMA1_SCR(7) #define DMA1_S7CR DMA1_SCR(7)
#define DMA2_S0CR DMA2_SCR(0) #define DMA2_S0CR DMA2_SCR(0)
#define DMA2_S1CR DMA2_SCR(1) #define DMA2_S1CR DMA2_SCR(1)
#define DMA2_S2CR DMA2_SCR(2) #define DMA2_S2CR DMA2_SCR(2)
#define DMA2_S3CR DMA2_SCR(3) #define DMA2_S3CR DMA2_SCR(3)
#define DMA2_S4CR DMA2_SCR(4) #define DMA2_S4CR DMA2_SCR(4)
#define DMA2_S5CR DMA2_SCR(5) #define DMA2_S5CR DMA2_SCR(5)
#define DMA2_S6CR DMA2_SCR(6) #define DMA2_S6CR DMA2_SCR(6)
#define DMA2_S7CR DMA2_SCR(7) #define DMA2_S7CR DMA2_SCR(7)
/* DMA Stream x number of data register (DMA_SxNDTR) */ /* DMA Stream x number of data register (DMA_SxNDTR) */
#define DMA_SNDTR(port, n) MMIO32(DMA_STREAM(port, n) + 0x04) #define DMA_SNDTR(port, n) MMIO32(DMA_STREAM(port, n) + 0x04)
#define DMA1_SNDTR(n) DMA_SNDTR(DMA1, n) #define DMA1_SNDTR(n) DMA_SNDTR(DMA1, n)
#define DMA2_SNDTR(n) DMA_SNDTR(DMA2, n) #define DMA2_SNDTR(n) DMA_SNDTR(DMA2, n)
#define DMA1_S0NDTR DMA1_SNDTR(0) #define DMA1_S0NDTR DMA1_SNDTR(0)
#define DMA1_S1NDTR DMA1_SNDTR(1) #define DMA1_S1NDTR DMA1_SNDTR(1)
#define DMA1_S2NDTR DMA1_SNDTR(2) #define DMA1_S2NDTR DMA1_SNDTR(2)
#define DMA1_S3NDTR DMA1_SNDTR(3) #define DMA1_S3NDTR DMA1_SNDTR(3)
#define DMA1_S4NDTR DMA1_SNDTR(4) #define DMA1_S4NDTR DMA1_SNDTR(4)
#define DMA1_S5NDTR DMA1_SNDTR(5) #define DMA1_S5NDTR DMA1_SNDTR(5)
#define DMA1_S6NDTR DMA1_SNDTR(6) #define DMA1_S6NDTR DMA1_SNDTR(6)
#define DMA1_S7NDTR DMA1_SNDTR(7) #define DMA1_S7NDTR DMA1_SNDTR(7)
#define DMA2_S0NDTR DMA2_SNDTR(0) #define DMA2_S0NDTR DMA2_SNDTR(0)
#define DMA2_S1NDTR DMA2_SNDTR(1) #define DMA2_S1NDTR DMA2_SNDTR(1)
#define DMA2_S2NDTR DMA2_SNDTR(2) #define DMA2_S2NDTR DMA2_SNDTR(2)
#define DMA2_S3NDTR DMA2_SNDTR(3) #define DMA2_S3NDTR DMA2_SNDTR(3)
#define DMA2_S4NDTR DMA2_SNDTR(4) #define DMA2_S4NDTR DMA2_SNDTR(4)
#define DMA2_S5NDTR DMA2_SNDTR(5) #define DMA2_S5NDTR DMA2_SNDTR(5)
#define DMA2_S6NDTR DMA2_SNDTR(6) #define DMA2_S6NDTR DMA2_SNDTR(6)
#define DMA2_S7NDTR DMA2_SNDTR(7) #define DMA2_S7NDTR DMA2_SNDTR(7)
/* DMA Stream x peripheral address register (DMA_SxPAR) */ /* DMA Stream x peripheral address register (DMA_SxPAR) */
#define DMA_SPAR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x08) #define DMA_SPAR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x08)
#define DMA1_SPAR(n) DMA_SPAR(DMA1, n) #define DMA1_SPAR(n) DMA_SPAR(DMA1, n)
#define DMA2_SPAR(n) DMA_SPAR(DMA2, n) #define DMA2_SPAR(n) DMA_SPAR(DMA2, n)
#define DMA1_S0PAR DMA1_SPAR(0) #define DMA1_S0PAR DMA1_SPAR(0)
#define DMA1_S1PAR DMA1_SPAR(1) #define DMA1_S1PAR DMA1_SPAR(1)
#define DMA1_S2PAR DMA1_SPAR(2) #define DMA1_S2PAR DMA1_SPAR(2)
#define DMA1_S3PAR DMA1_SPAR(3) #define DMA1_S3PAR DMA1_SPAR(3)
#define DMA1_S4PAR DMA1_SPAR(4) #define DMA1_S4PAR DMA1_SPAR(4)
#define DMA1_S5PAR DMA1_SPAR(5) #define DMA1_S5PAR DMA1_SPAR(5)
#define DMA1_S6PAR DMA1_SPAR(6) #define DMA1_S6PAR DMA1_SPAR(6)
#define DMA1_S7PAR DMA1_SPAR(7) #define DMA1_S7PAR DMA1_SPAR(7)
#define DMA2_S0PAR DMA2_SPAR(0) #define DMA2_S0PAR DMA2_SPAR(0)
#define DMA2_S1PAR DMA2_SPAR(1) #define DMA2_S1PAR DMA2_SPAR(1)
#define DMA2_S2PAR DMA2_SPAR(2) #define DMA2_S2PAR DMA2_SPAR(2)
#define DMA2_S3PAR DMA2_SPAR(3) #define DMA2_S3PAR DMA2_SPAR(3)
#define DMA2_S4PAR DMA2_SPAR(4) #define DMA2_S4PAR DMA2_SPAR(4)
#define DMA2_S5PAR DMA2_SPAR(5) #define DMA2_S5PAR DMA2_SPAR(5)
#define DMA2_S6PAR DMA2_SPAR(6) #define DMA2_S6PAR DMA2_SPAR(6)
#define DMA2_S7PAR DMA2_SPAR(7) #define DMA2_S7PAR DMA2_SPAR(7)
/* DMA Stream x memory address 0 register (DMA_SxM0AR) */ /* DMA Stream x memory address 0 register (DMA_SxM0AR) */
#define DMA_SM0AR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x0C) #define DMA_SM0AR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x0c)
#define DMA1_SM0AR(n) DMA_SM0AR(DMA1, n) #define DMA1_SM0AR(n) DMA_SM0AR(DMA1, n)
#define DMA2_SM0AR(n) DMA_SM0AR(DMA2, n) #define DMA2_SM0AR(n) DMA_SM0AR(DMA2, n)
#define DMA1_S0M0AR DMA1_SM0AR(0) #define DMA1_S0M0AR DMA1_SM0AR(0)
#define DMA1_S1M0AR DMA1_SM0AR(1) #define DMA1_S1M0AR DMA1_SM0AR(1)
#define DMA1_S2M0AR DMA1_SM0AR(2) #define DMA1_S2M0AR DMA1_SM0AR(2)
#define DMA1_S3M0AR DMA1_SM0AR(3) #define DMA1_S3M0AR DMA1_SM0AR(3)
#define DMA1_S4M0AR DMA1_SM0AR(4) #define DMA1_S4M0AR DMA1_SM0AR(4)
#define DMA1_S5M0AR DMA1_SM0AR(5) #define DMA1_S5M0AR DMA1_SM0AR(5)
#define DMA1_S6M0AR DMA1_SM0AR(6) #define DMA1_S6M0AR DMA1_SM0AR(6)
#define DMA1_S7M0AR DMA1_SM0AR(7) #define DMA1_S7M0AR DMA1_SM0AR(7)
#define DMA2_S0M0AR DMA2_SM0AR(0) #define DMA2_S0M0AR DMA2_SM0AR(0)
#define DMA2_S1M0AR DMA2_SM0AR(1) #define DMA2_S1M0AR DMA2_SM0AR(1)
#define DMA2_S2M0AR DMA2_SM0AR(2) #define DMA2_S2M0AR DMA2_SM0AR(2)
#define DMA2_S3M0AR DMA2_SM0AR(3) #define DMA2_S3M0AR DMA2_SM0AR(3)
#define DMA2_S4M0AR DMA2_SM0AR(4) #define DMA2_S4M0AR DMA2_SM0AR(4)
#define DMA2_S5M0AR DMA2_SM0AR(5) #define DMA2_S5M0AR DMA2_SM0AR(5)
#define DMA2_S6M0AR DMA2_SM0AR(6) #define DMA2_S6M0AR DMA2_SM0AR(6)
#define DMA2_S7M0AR DMA2_SM0AR(7) #define DMA2_S7M0AR DMA2_SM0AR(7)
/* DMA Stream x memory address 1 register (DMA_SxM1AR) */ /* DMA Stream x memory address 1 register (DMA_SxM1AR) */
#define DMA_SM1AR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x10) #define DMA_SM1AR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x10)
#define DMA1_SM1AR(n) DMA_SM1AR(DMA1, n) #define DMA1_SM1AR(n) DMA_SM1AR(DMA1, n)
#define DMA2_SM1AR(n) DMA_SM1AR(DMA2, n) #define DMA2_SM1AR(n) DMA_SM1AR(DMA2, n)
#define DMA1_S0M1AR DMA1_SM1AR(0) #define DMA1_S0M1AR DMA1_SM1AR(0)
#define DMA1_S1M1AR DMA1_SM1AR(1) #define DMA1_S1M1AR DMA1_SM1AR(1)
#define DMA1_S2M1AR DMA1_SM1AR(2) #define DMA1_S2M1AR DMA1_SM1AR(2)
#define DMA1_S3M1AR DMA1_SM1AR(3) #define DMA1_S3M1AR DMA1_SM1AR(3)
#define DMA1_S4M1AR DMA1_SM1AR(4) #define DMA1_S4M1AR DMA1_SM1AR(4)
#define DMA1_S5M1AR DMA1_SM1AR(5) #define DMA1_S5M1AR DMA1_SM1AR(5)
#define DMA1_S6M1AR DMA1_SM1AR(6) #define DMA1_S6M1AR DMA1_SM1AR(6)
#define DMA1_S7M1AR DMA1_SM1AR(7) #define DMA1_S7M1AR DMA1_SM1AR(7)
#define DMA2_S0M1AR DMA2_SM1AR(0) #define DMA2_S0M1AR DMA2_SM1AR(0)
#define DMA2_S1M1AR DMA2_SM1AR(1) #define DMA2_S1M1AR DMA2_SM1AR(1)
#define DMA2_S2M1AR DMA2_SM1AR(2) #define DMA2_S2M1AR DMA2_SM1AR(2)
#define DMA2_S3M1AR DMA2_SM1AR(3) #define DMA2_S3M1AR DMA2_SM1AR(3)
#define DMA2_S4M1AR DMA2_SM1AR(4) #define DMA2_S4M1AR DMA2_SM1AR(4)
#define DMA2_S5M1AR DMA2_SM1AR(5) #define DMA2_S5M1AR DMA2_SM1AR(5)
#define DMA2_S6M1AR DMA2_SM1AR(6) #define DMA2_S6M1AR DMA2_SM1AR(6)
#define DMA2_S7M1AR DMA2_SM1AR(7) #define DMA2_S7M1AR DMA2_SM1AR(7)
/* DMA Stream x FIFO control register (DMA_SxFCR) */ /* DMA Stream x FIFO control register (DMA_SxFCR) */
#define DMA_SFCR(port, n) MMIO32(DMA_STREAM(port, n) + 0x10) #define DMA_SFCR(port, n) MMIO32(DMA_STREAM(port, n) + 0x10)
#define DMA1_SFCR(n) DMA_SFCR(DMA1, n) #define DMA1_SFCR(n) DMA_SFCR(DMA1, n)
#define DMA2_SFCR(n) DMA_SFCR(DMA2, n) #define DMA2_SFCR(n) DMA_SFCR(DMA2, n)
#define DMA1_S0FCR DMA1_SFCR(0) #define DMA1_S0FCR DMA1_SFCR(0)
#define DMA1_S1FCR DMA1_SFCR(1) #define DMA1_S1FCR DMA1_SFCR(1)
#define DMA1_S2FCR DMA1_SFCR(2) #define DMA1_S2FCR DMA1_SFCR(2)
#define DMA1_S3FCR DMA1_SFCR(3) #define DMA1_S3FCR DMA1_SFCR(3)
#define DMA1_S4FCR DMA1_SFCR(4) #define DMA1_S4FCR DMA1_SFCR(4)
#define DMA1_S5FCR DMA1_SFCR(5) #define DMA1_S5FCR DMA1_SFCR(5)
#define DMA1_S6FCR DMA1_SFCR(6) #define DMA1_S6FCR DMA1_SFCR(6)
#define DMA1_S7FCR DMA1_SFCR(7) #define DMA1_S7FCR DMA1_SFCR(7)
#define DMA2_S0FCR DMA2_SFCR(0) #define DMA2_S0FCR DMA2_SFCR(0)
#define DMA2_S1FCR DMA2_SFCR(1) #define DMA2_S1FCR DMA2_SFCR(1)
#define DMA2_S2FCR DMA2_SFCR(2) #define DMA2_S2FCR DMA2_SFCR(2)
#define DMA2_S3FCR DMA2_SFCR(3) #define DMA2_S3FCR DMA2_SFCR(3)
#define DMA2_S4FCR DMA2_SFCR(4) #define DMA2_S4FCR DMA2_SFCR(4)
#define DMA2_S5FCR DMA2_SFCR(5) #define DMA2_S5FCR DMA2_SFCR(5)
#define DMA2_S6FCR DMA2_SFCR(6) #define DMA2_S6FCR DMA2_SFCR(6)
#define DMA2_S7FCR DMA2_SFCR(7) #define DMA2_S7FCR DMA2_SFCR(7)
/* --- DMA_LISR values ----------------------------------------------------- */ /* --- DMA_LISR values ----------------------------------------------------- */
#define DMA_LISR_FEIF0 (1<<0) #define DMA_LISR_FEIF0 (1 << 0)
#define DMA_LISR_DMEIF0 (1<<2) #define DMA_LISR_DMEIF0 (1 << 2)
#define DMA_LISR_TEIF0 (1<<3) #define DMA_LISR_TEIF0 (1 << 3)
#define DMA_LISR_HTIF0 (1<<4) #define DMA_LISR_HTIF0 (1 << 4)
#define DMA_LISR_TCIF0 (1<<5) #define DMA_LISR_TCIF0 (1 << 5)
#define DMA_LISR_FEIF1 (1<<6) #define DMA_LISR_FEIF1 (1 << 6)
#define DMA_LISR_DMEIF1 (1<<8) #define DMA_LISR_DMEIF1 (1 << 8)
#define DMA_LISR_TEIF1 (1<<9) #define DMA_LISR_TEIF1 (1 << 9)
#define DMA_LISR_HTIF1 (1<<10) #define DMA_LISR_HTIF1 (1 << 10)
#define DMA_LISR_TCIF1 (1<<11) #define DMA_LISR_TCIF1 (1 << 11)
#define DMA_LISR_FEIF2 (1<<16) #define DMA_LISR_FEIF2 (1 << 16)
#define DMA_LISR_DMEIF2 (1<<18) #define DMA_LISR_DMEIF2 (1 << 18)
#define DMA_LISR_TEIF2 (1<<19) #define DMA_LISR_TEIF2 (1 << 19)
#define DMA_LISR_HTIF2 (1<<20) #define DMA_LISR_HTIF2 (1 << 20)
#define DMA_LISR_TCIF2 (1<<21) #define DMA_LISR_TCIF2 (1 << 21)
#define DMA_LISR_FEIF3 (1<<22) #define DMA_LISR_FEIF3 (1 << 22)
#define DMA_LISR_DMEIF3 (1<<24) #define DMA_LISR_DMEIF3 (1 << 24)
#define DMA_LISR_TEIF3 (1<<25) #define DMA_LISR_TEIF3 (1 << 25)
#define DMA_LISR_HTIF3 (1<<26) #define DMA_LISR_HTIF3 (1 << 26)
#define DMA_LISR_TCIF3 (1<<27) #define DMA_LISR_TCIF3 (1 << 27)
/* --- DMA_HISR values ----------------------------------------------------- */ /* --- DMA_HISR values ----------------------------------------------------- */
#define DMA_HISR_FEIF4 (1<<0) #define DMA_HISR_FEIF4 (1 << 0)
#define DMA_HISR_DMEIF4 (1<<2) #define DMA_HISR_DMEIF4 (1 << 2)
#define DMA_HISR_TEIF4 (1<<3) #define DMA_HISR_TEIF4 (1 << 3)
#define DMA_HISR_HTIF4 (1<<4) #define DMA_HISR_HTIF4 (1 << 4)
#define DMA_HISR_TCIF4 (1<<5) #define DMA_HISR_TCIF4 (1 << 5)
#define DMA_HISR_FEIF5 (1<<6) #define DMA_HISR_FEIF5 (1 << 6)
#define DMA_HISR_DMEIF5 (1<<8) #define DMA_HISR_DMEIF5 (1 << 8)
#define DMA_HISR_TEIF5 (1<<9) #define DMA_HISR_TEIF5 (1 << 9)
#define DMA_HISR_HTIF5 (1<<10) #define DMA_HISR_HTIF5 (1 << 10)
#define DMA_HISR_TCIF5 (1<<11) #define DMA_HISR_TCIF5 (1 << 11)
#define DMA_HISR_FEIF6 (1<<16) #define DMA_HISR_FEIF6 (1 << 16)
#define DMA_HISR_DMEIF6 (1<<18) #define DMA_HISR_DMEIF6 (1 << 18)
#define DMA_HISR_TEIF6 (1<<19) #define DMA_HISR_TEIF6 (1 << 19)
#define DMA_HISR_HTIF6 (1<<20) #define DMA_HISR_HTIF6 (1 << 20)
#define DMA_HISR_TCIF6 (1<<21) #define DMA_HISR_TCIF6 (1 << 21)
#define DMA_HISR_FEIF7 (1<<22) #define DMA_HISR_FEIF7 (1 << 22)
#define DMA_HISR_DMEIF7 (1<<24) #define DMA_HISR_DMEIF7 (1 << 24)
#define DMA_HISR_TEIF7 (1<<25) #define DMA_HISR_TEIF7 (1 << 25)
#define DMA_HISR_HTIF7 (1<<26) #define DMA_HISR_HTIF7 (1 << 26)
#define DMA_HISR_TCIF7 (1<<27) #define DMA_HISR_TCIF7 (1 << 27)
/* --- DMA_LIFCR values ----------------------------------------------------- */ /* --- DMA_LIFCR values ----------------------------------------------------- */
#define DMA_LIFCR_CFEIF0 (1<<0) #define DMA_LIFCR_CFEIF0 (1 << 0)
#define DMA_LIFCR_CDMEIF0 (1<<2) #define DMA_LIFCR_CDMEIF0 (1 << 2)
#define DMA_LIFCR_CTEIF0 (1<<3) #define DMA_LIFCR_CTEIF0 (1 << 3)
#define DMA_LIFCR_CHTIF0 (1<<4) #define DMA_LIFCR_CHTIF0 (1 << 4)
#define DMA_LIFCR_CTCIF0 (1<<5) #define DMA_LIFCR_CTCIF0 (1 << 5)
#define DMA_LIFCR_CFEIF1 (1<<6) #define DMA_LIFCR_CFEIF1 (1 << 6)
#define DMA_LIFCR_CDMEIF1 (1<<8) #define DMA_LIFCR_CDMEIF1 (1 << 8)
#define DMA_LIFCR_CTEIF1 (1<<9) #define DMA_LIFCR_CTEIF1 (1 << 9)
#define DMA_LIFCR_CHTIF1 (1<<10) #define DMA_LIFCR_CHTIF1 (1 << 10)
#define DMA_LIFCR_CTCIF1 (1<<11) #define DMA_LIFCR_CTCIF1 (1 << 11)
#define DMA_LIFCR_CFEIF2 (1<<16) #define DMA_LIFCR_CFEIF2 (1 << 16)
#define DMA_LIFCR_CDMEIF2 (1<<18) #define DMA_LIFCR_CDMEIF2 (1 << 18)
#define DMA_LIFCR_CTEIF2 (1<<19) #define DMA_LIFCR_CTEIF2 (1 << 19)
#define DMA_LIFCR_CHTIF2 (1<<20) #define DMA_LIFCR_CHTIF2 (1 << 20)
#define DMA_LIFCR_CTCIF2 (1<<21) #define DMA_LIFCR_CTCIF2 (1 << 21)
#define DMA_LIFCR_CFEIF3 (1<<22) #define DMA_LIFCR_CFEIF3 (1 << 22)
#define DMA_LIFCR_CDMEIF3 (1<<24) #define DMA_LIFCR_CDMEIF3 (1 << 24)
#define DMA_LIFCR_CTEIF3 (1<<25) #define DMA_LIFCR_CTEIF3 (1 << 25)
#define DMA_LIFCR_CHTIF3 (1<<26) #define DMA_LIFCR_CHTIF3 (1 << 26)
#define DMA_LIFCR_CTCIF3 (1<<27) #define DMA_LIFCR_CTCIF3 (1 << 27)
/* --- DMA_HIFCR values ----------------------------------------------------- */ /* --- DMA_HIFCR values ----------------------------------------------------- */
#define DMA_HIFCR_CFEIF4 (1<<0) #define DMA_HIFCR_CFEIF4 (1 << 0)
#define DMA_HIFCR_CDMEIF4 (1<<2) #define DMA_HIFCR_CDMEIF4 (1 << 2)
#define DMA_HIFCR_CTEIF4 (1<<3) #define DMA_HIFCR_CTEIF4 (1 << 3)
#define DMA_HIFCR_CHTIF4 (1<<4) #define DMA_HIFCR_CHTIF4 (1 << 4)
#define DMA_HIFCR_CTCIF4 (1<<5) #define DMA_HIFCR_CTCIF4 (1 << 5)
#define DMA_HIFCR_CFEIF5 (1<<6) #define DMA_HIFCR_CFEIF5 (1 << 6)
#define DMA_HIFCR_CDMEIF5 (1<<8) #define DMA_HIFCR_CDMEIF5 (1 << 8)
#define DMA_HIFCR_CTEIF5 (1<<9) #define DMA_HIFCR_CTEIF5 (1 << 9)
#define DMA_HIFCR_CHTIF5 (1<<10) #define DMA_HIFCR_CHTIF5 (1 << 10)
#define DMA_HIFCR_CTCIF5 (1<<11) #define DMA_HIFCR_CTCIF5 (1 << 11)
#define DMA_HIFCR_CFEIF6 (1<<16) #define DMA_HIFCR_CFEIF6 (1 << 16)
#define DMA_HIFCR_CDMEIF6 (1<<18) #define DMA_HIFCR_CDMEIF6 (1 << 18)
#define DMA_HIFCR_CTEIF6 (1<<19) #define DMA_HIFCR_CTEIF6 (1 << 19)
#define DMA_HIFCR_CHTIF6 (1<<20) #define DMA_HIFCR_CHTIF6 (1 << 20)
#define DMA_HIFCR_CTCIF6 (1<<21) #define DMA_HIFCR_CTCIF6 (1 << 21)
#define DMA_HIFCR_CFEIF7 (1<<22) #define DMA_HIFCR_CFEIF7 (1 << 22)
#define DMA_HIFCR_CDMEIF7 (1<<24) #define DMA_HIFCR_CDMEIF7 (1 << 24)
#define DMA_HIFCR_CTEIF7 (1<<25) #define DMA_HIFCR_CTEIF7 (1 << 25)
#define DMA_HIFCR_CHTIF7 (1<<26) #define DMA_HIFCR_CHTIF7 (1 << 26)
#define DMA_HIFCR_CTCIF7 (1<<27) #define DMA_HIFCR_CTCIF7 (1 << 27)
/* --- DMA_SxCR values ----------------------------------------------------- */ /* --- DMA_SxCR values ----------------------------------------------------- */
#define DMA_SxCR_EN (1<<0) #define DMA_SxCR_EN (1 << 0)
#define DMA_SxCR_DMEIE (1<<1) #define DMA_SxCR_DMEIE (1 << 1)
#define DMA_SxCR_TEIE (1<<2) #define DMA_SxCR_TEIE (1 << 2)
#define DMA_SxCR_HTIE (1<<3) #define DMA_SxCR_HTIE (1 << 3)
#define DMA_SxCR_TCIE (1<<4) #define DMA_SxCR_TCIE (1 << 4)
#define DMA_SxCR_PFCTRL (1<<5) #define DMA_SxCR_PFCTRL (1 << 5)
#define DMA_SxCR_DIR_SHIFT 6 #define DMA_SxCR_DIR_SHIFT 6
#define DMA_SxCR_DIR_PERIPHERAL_TO_MEM (0<<6) #define DMA_SxCR_DIR_PERIPHERAL_TO_MEM (0 << 6)
#define DMA_SxCR_DIR_MEM_TO_PERIPHERAL (1<<6) #define DMA_SxCR_DIR_MEM_TO_PERIPHERAL (1 << 6)
#define DMA_SxCR_DIR_MEM_TO_MEM (2<<6) #define DMA_SxCR_DIR_MEM_TO_MEM (2 << 6)
#define DMA_SxCR_CIRC (1<<8) #define DMA_SxCR_CIRC (1 << 8)
#define DMA_SxCR_PINC (1<<9) #define DMA_SxCR_PINC (1 << 9)
#define DMA_SxCR_MINC (1<<10) #define DMA_SxCR_MINC (1 << 10)
#define DMA_SxCR_PSIZE_SHIFT 11 #define DMA_SxCR_PSIZE_SHIFT 11
#define DMA_SxCR_PSIZE_8BIT (0<<11) #define DMA_SxCR_PSIZE_8BIT (0 << 11)
#define DMA_SxCR_PSIZE_16BIT (1<<11) #define DMA_SxCR_PSIZE_16BIT (1 << 11)
#define DMA_SxCR_PSIZE_32BIT (2<<11) #define DMA_SxCR_PSIZE_32BIT (2 << 11)
#define DMA_SxCR_MSIZE_SHIFT 13 #define DMA_SxCR_MSIZE_SHIFT 13
#define DMA_SxCR_MSIZE_8BIT (0<<13) #define DMA_SxCR_MSIZE_8BIT (0 << 13)
#define DMA_SxCR_MSIZE_16BIT (1<<13) #define DMA_SxCR_MSIZE_16BIT (1 << 13)
#define DMA_SxCR_MSIZE_32BIT (2<<13) #define DMA_SxCR_MSIZE_32BIT (2 << 13)
#define DMA_SxCR_PINCOS (1<<15) #define DMA_SxCR_PINCOS (1 << 15)
#define DMA_SxCR_PL_SHIFT 16 #define DMA_SxCR_PL_SHIFT 16
#define DMA_SxCR_PL_LOW (0<<16) #define DMA_SxCR_PL_LOW (0 << 16)
#define DMA_SxCR_PL_MEDIUM (1<<16) #define DMA_SxCR_PL_MEDIUM (1 << 16)
#define DMA_SxCR_PL_HIGH (2<<16) #define DMA_SxCR_PL_HIGH (2 << 16)
#define DMA_SxCR_PL_VERY_HIGH (3<<16) #define DMA_SxCR_PL_VERY_HIGH (3 << 16)
#define DMA_SxCR_DBM (1<<18) #define DMA_SxCR_DBM (1 << 18)
#define DMA_SxCR_CT (1<<18) #define DMA_SxCR_CT (1 << 18)
#define DMA_SxCR_PBURST_SHIFT 21 #define DMA_SxCR_PBURST_SHIFT 21
#define DMA_SxCR_PBURST_SINGLE (0<<21) #define DMA_SxCR_PBURST_SINGLE (0 << 21)
#define DMA_SxCR_PBURST_INCR4 (1<<21) #define DMA_SxCR_PBURST_INCR4 (1 << 21)
#define DMA_SxCR_PBURST_INCR8 (2<<21) #define DMA_SxCR_PBURST_INCR8 (2 << 21)
#define DMA_SxCR_PBURST_INCR16 (3<<21) #define DMA_SxCR_PBURST_INCR16 (3 << 21)
#define DMA_SxCR_MBURST_SHIFT 23 #define DMA_SxCR_MBURST_SHIFT 23
#define DMA_SxCR_MBURST_SINGLE (0<<23) #define DMA_SxCR_MBURST_SINGLE (0 << 23)
#define DMA_SxCR_MBURST_INCR4 (1<<23) #define DMA_SxCR_MBURST_INCR4 (1 << 23)
#define DMA_SxCR_MBURST_INCR8 (2<<23) #define DMA_SxCR_MBURST_INCR8 (2 << 23)
#define DMA_SxCR_MBURST_INCR16 (3<<23) #define DMA_SxCR_MBURST_INCR16 (3 << 23)
#define DMA_SxCR_CHSEL_SHIFT 25 #define DMA_SxCR_CHSEL_SHIFT 25
#define DMA_SxCR_CHSEL(n) (n<<25) #define DMA_SxCR_CHSEL(n) (n << 25)
/* --- DMA_SxNDTR values --------------------------------------------------- */ /* --- DMA_SxNDTR values --------------------------------------------------- */
@ -390,22 +390,22 @@
/* --- DMA_SxFCR values ---------------------------------------------------- */ /* --- DMA_SxFCR values ---------------------------------------------------- */
#define DMA_SxFCR_FTH_SHIFT 0 #define DMA_SxFCR_FTH_SHIFT 0
#define DMA_SxFCR_FTH_1_4_FULL (0<<0) #define DMA_SxFCR_FTH_1_4_FULL (0 << 0)
#define DMA_SxFCR_FTH_2_4_FULL (1<<0) #define DMA_SxFCR_FTH_2_4_FULL (1 << 0)
#define DMA_SxFCR_FTH_3_4_FULL (2<<0) #define DMA_SxFCR_FTH_3_4_FULL (2 << 0)
#define DMA_SxFCR_FTH_4_4_FULL (3<<0) #define DMA_SxFCR_FTH_4_4_FULL (3 << 0)
#define DMA_SxFCR_DMDIS (1<<2) #define DMA_SxFCR_DMDIS (1 << 2)
#define DMA_SxFCR_FS_SHIFT 3 #define DMA_SxFCR_FS_SHIFT 3
#define DMA_SxFCR_FS_LT_1_4_FULL (0<<0) #define DMA_SxFCR_FS_LT_1_4_FULL (0 << 0)
#define DMA_SxFCR_FS_LT_2_4_FULL (1<<0) #define DMA_SxFCR_FS_LT_2_4_FULL (1 << 0)
#define DMA_SxFCR_FS_LT_3_4_FULL (2<<0) #define DMA_SxFCR_FS_LT_3_4_FULL (2 << 0)
#define DMA_SxFCR_FS_LT_4_4_FULL (3<<0) #define DMA_SxFCR_FS_LT_4_4_FULL (3 << 0)
#define DMA_SxFCR_FS_FULL (4<<3) #define DMA_SxFCR_FS_FULL (4 << 3)
#define DMA_SxFCR_FS_EMPTY (5<<3) #define DMA_SxFCR_FS_EMPTY (5 << 3)
#define DMA_SxFCR_FEIE (1<<7) #define DMA_SxFCR_FEIE (1 << 7)
#endif #endif

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