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@ -38,7 +38,7 @@ int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst) |
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reg32 |= SPI_CR1_MSTR; /* Configure SPI as master. */ |
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reg32 |= br; /* Set BAUD rate bits. */ |
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reg32 |= br; /* Set baud rate bits. */ |
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reg32 |= cpol; /* Set CPOL value. */ |
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reg32 |= cpha; /* Set CPHA value. */ |
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reg32 |= dff; /* Set data format (8 or 16 bits). */ |
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@ -62,9 +62,9 @@ void spi_disable(u32 spi) |
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{ |
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u32 reg32; |
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/* TODO: Follow procedure from section 23.3.8 in the techref manual. */ |
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/* TODO: Follow procedure from section 23.3.8 in the TRM. */ |
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reg32 = SPI_CR1(spi); |
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reg32 &= ~(SPI_CR1_SPE); /* Disable SPI. */ |
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reg32 &= ~(SPI_CR1_SPE); /* Disable SPI. */ |
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SPI_CR1(spi) = reg32; |
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} |
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@ -76,17 +76,19 @@ void spi_write(u32 spi, u16 data) |
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void spi_send(u32 spi, u16 data) |
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{ |
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/* wait for transfer finished */ |
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while (!(SPI_SR(spi) & SPI_SR_TXE )); |
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/* Wait for transfer finished. */ |
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while (!(SPI_SR(spi) & SPI_SR_TXE)) |
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; |
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/* Write data (8 or 16 bits, depending on DFF) into DR. */ |
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SPI_DR(spi) = data; |
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} |
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u16 spi_read(u32 spi) |
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{ |
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/* wait for transfer finished */ |
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while (!(SPI_SR(spi) & SPI_SR_RXNE )); |
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/* Wait for transfer finished. */ |
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while (!(SPI_SR(spi) & SPI_SR_RXNE)) |
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; |
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/* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ |
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return SPI_DR(spi); |
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@ -94,10 +96,11 @@ u16 spi_read(u32 spi) |
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u16 spi_xfer(u32 spi, u16 data) |
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{ |
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spi_write(spi, data); |
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spi_write(spi, data); |
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/* wait for transfer finished */ |
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while (!(SPI_SR(spi) & SPI_SR_RXNE )); |
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/* Wait for transfer finished. */ |
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while (!(SPI_SR(spi) & SPI_SR_RXNE)) |
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; |
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/* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ |
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return SPI_DR(spi); |
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@ -199,10 +202,10 @@ void spi_set_baudrate_prescaler(u32 spi, u8 baudrate) |
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{ |
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u32 reg32; |
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if (baudrate > 7) |
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if (baudrate > 7) |
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return; |
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reg32 = ( SPI_CR1(spi) & 0xffc7 ); /* clear bits [5:3] */ |
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reg32 = (SPI_CR1(spi) & 0xffc7); /* Clear bits [5:3]. */ |
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reg32 |= (baudrate << 3); |
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SPI_CR1(spi) = reg32; |
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} |
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