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@ -66,6 +66,19 @@ |
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#define ADC_CFGR2_CKMODE_PCLK_DIV4 (2 << ADC_CFGR2_CKMODE_SHIFT) |
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#define ADC_CFGR2_CKMODE_PCLK (3 << ADC_CFGR2_CKMODE_SHIFT) |
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/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels
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@ingroup adc_defines |
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@{*/ |
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#define ADC_SMPR_SMP_1DOT5CYC 0x0 |
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#define ADC_SMPR_SMP_3DOT5CYC 0x1 |
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#define ADC_SMPR_SMP_7DOT5CYC 0x2 |
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#define ADC_SMPR_SMP_12DOT5CYC 0x3 |
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#define ADC_SMPR_SMP_19DOT5CYC 0x4 |
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#define ADC_SMPR_SMP_39DOT5CYC 0x5 |
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#define ADC_SMPR_SMP_79DOT5CYC 0x6 |
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#define ADC_SMPR_SMP_160DOT5CYC 0x7 |
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/**@}*/ |
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BEGIN_DECLS |
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