stm32:f0/g0/l0: adc: Add EXTSEL defines

Add definitions for all the specific options, as is done for other
families.

Reviewed-by: Karl Palsson <karlp@tweak.au>
(Added extra g0 definitions that were missed)

include/libopencm3/stm32/f0/adc.h

@@ -80,6 +80,14 @@
 #define ADC_CFGR1_EXTSEL_SHIFT		6
 #define ADC_CFGR1_EXTSEL		(0x7 << ADC_CFGR1_EXTSEL_SHIFT)
 #define ADC_CFGR1_EXTSEL_VAL(x)		((x) << ADC_CFGR1_EXTSEL_SHIFT)
+/** @defgroup adc_cfgr1_extsel ADC external trigger selection values
+ *@{*/
+#define ADC_CFGR1_EXTSEL_TIM1_TRGO	0x0
+#define ADC_CFGR1_EXTSEL_TIM1_CC4	0x1
+#define ADC_CFGR1_EXTSEL_TIM2_TRGO	0x2
+#define ADC_CFGR1_EXTSEL_TIM3_TRGO	0x3
+#define ADC_CFGR1_EXTSEL_TIM15_TRGO	0x4
+/**@}*/
 
 /* ADC_CFGR2 Values ---------------------------------------------------------*/
 

include/libopencm3/stm32/g0/adc.h

@@ -125,6 +125,17 @@
 #define ADC_CFGR1_EXTSEL_SHIFT			6
 #define ADC_CFGR1_EXTSEL			(0x7 << ADC_CFGR1_EXTSEL_SHIFT)
 #define ADC_CFGR1_EXTSEL_VAL(x)			((x) << ADC_CFGR1_EXTSEL_SHIFT)
+/** @defgroup adc_cfgr1_extsel ADC external trigger selection values
+ *@{*/
+#define ADC_CFGR1_EXTSEL_TIM1_TRGO2	0x0
+#define ADC_CFGR1_EXTSEL_TIM1_CC4	0x1
+#define ADC_CFGR1_EXTSEL_TIM2_TRGO	0x2
+#define ADC_CFGR1_EXTSEL_TIM3_TRGO	0x3
+#define ADC_CFGR1_EXTSEL_TIM15_TRGO	0x4
+#define ADC_CFGR1_EXTSEL_TIM6_TRGO	0x5
+#define ADC_CFGR1_EXTSEL_TIM4_TRGO	0x6
+#define ADC_CFGR1_EXTSEL_EXTI11		0x7
+/**@}*/
 
 /** CHSELRMOD: Mode Selection of the ADC_CHSELR register */
 #define ADC_CFGR1_CHSELRMOD			(1 << 21)

include/libopencm3/stm32/l0/adc.h

@@ -67,6 +67,19 @@
 #define ADC_CFGR1_EXTSEL		(0x7 << ADC_CFGR1_EXTSEL_SHIFT)
 #define ADC_CFGR1_EXTSEL_VAL(x)		((x) << ADC_CFGR1_EXTSEL_SHIFT)
 
+/** @defgroup adc_cfgr1_extsel ADC external trigger selection values
+ *@{*/
+#define ADC_CFGR1_EXTSEL_TIM6_TRGO	0x0
+#define ADC_CFGR1_EXTSEL_TIM21_CH2	0x1
+#define ADC_CFGR1_EXTSEL_TIM2_TRGO	0x2
+#define ADC_CFGR1_EXTSEL_TIM2_CH4	0x3
+#define ADC_CFGR1_EXTSEL_TIM21_TRGO	0x4
+#define ADC_CFGR1_EXTSEL_TIM22_TRGO	0x4
+#define ADC_CFGR1_EXTSEL_TIM2_CH3	0x5
+#define ADC_CFGR1_EXTSEL_TIM3_TRGO	0x6
+#define ADC_CFGR1_EXTSEL_EXTI11		0x7
+/**@}*/
+
 /* ADC_CFGR2 Values ---------------------------------------------------------*/
 
 #define ADC_CFGR2_CKMODE_SHIFT		30