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Merge pull request #84 "Pr flash reg rename" 

Merge remote-tracking branch 'karlp/pr_flash-reg-rename'

Conflicts:
	include/libopencm3/stm32/l1/flash.h
pull/88/merge
Piotr Esden-Tempski 12 years ago
parent
f980f197ca 40d9d630f0
commit
6eef01ce26
12 changed files with 312 additions and 311 deletions
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  1. 56
      include/libopencm3/stm32/f1/flash.h
  2. 112
      include/libopencm3/stm32/f2/flash.h
  3. 112
      include/libopencm3/stm32/f4/flash.h
  4. 98
      include/libopencm3/stm32/l1/flash.h
  5. 63
      lib/stm32/f1/flash.c
  6. 16
      lib/stm32/f1/rcc.c
  7. 72
      lib/stm32/f2/flash.c
  8. 2
      lib/stm32/f2/rcc.c
  9. 74
      lib/stm32/f4/flash.c
  10. 4
      lib/stm32/f4/rcc.c
  11. 8
      lib/stm32/l1/flash.c
  12. 6
      lib/stm32/l1/rcc.c

56
include/libopencm3/stm32/f1/flash.h
View File

@ -44,48 +44,48 @@
/* --- FLASH_ACR values ---------------------------------------------------- */
#define FLASH_PRFTBS (1 << 5)
#define FLASH_PRFTBE (1 << 4)
#define FLASH_HLFCYA (1 << 3)
#define FLASH_LATENCY_0WS 0x00
#define FLASH_LATENCY_1WS 0x01
#define FLASH_LATENCY_2WS 0x02
#define FLASH_ACR_PRFTBS (1 << 5)
#define FLASH_ACR_PRFTBE (1 << 4)
#define FLASH_ACR_HLFCYA (1 << 3)
#define FLASH_ACR_LATENCY_0WS 0x00
#define FLASH_ACR_LATENCY_1WS 0x01
#define FLASH_ACR_LATENCY_2WS 0x02
/* --- FLASH_SR values ----------------------------------------------------- */
#define FLASH_EOP (1 << 5)
#define FLASH_WRPRTERR (1 << 4)
#define FLASH_PGERR (1 << 2)
#define FLASH_BSY (1 << 0)
#define FLASH_SR_EOP (1 << 5)
#define FLASH_SR_WRPRTERR (1 << 4)
#define FLASH_SR_PGERR (1 << 2)
#define FLASH_SR_BSY (1 << 0)
/* --- FLASH_CR values ----------------------------------------------------- */
#define FLASH_EOPIE (1 << 12)
#define FLASH_ERRIE (1 << 10)
#define FLASH_OPTWRE (1 << 9)
#define FLASH_LOCK (1 << 7)
#define FLASH_STRT (1 << 6)
#define FLASH_OPTER (1 << 5)
#define FLASH_OPTPG (1 << 4)
#define FLASH_MER (1 << 2)
#define FLASH_PER (1 << 1)
#define FLASH_PG (1 << 0)
#define FLASH_CR_EOPIE (1 << 12)
#define FLASH_CR_ERRIE (1 << 10)
#define FLASH_CR_OPTWRE (1 << 9)
#define FLASH_CR_LOCK (1 << 7)
#define FLASH_CR_STRT (1 << 6)
#define FLASH_CR_OPTER (1 << 5)
#define FLASH_CR_OPTPG (1 << 4)
#define FLASH_CR_MER (1 << 2)
#define FLASH_CR_PER (1 << 1)
#define FLASH_CR_PG (1 << 0)
/* --- FLASH_OBR values ---------------------------------------------------- */
/* FLASH_OBR[25:18]: Data1 */
/* FLASH_OBR[17:10]: Data0 */
#define FLASH_NRST_STDBY (1 << 4)
#define FLASH_NRST_STOP (1 << 3)
#define FLASH_WDG_SW (1 << 2)
#define FLASH_RDPRT (1 << 1)
#define FLASH_OPTERR (1 << 0)
#define FLASH_OBR_NRST_STDBY (1 << 4)
#define FLASH_OBR_NRST_STOP (1 << 3)
#define FLASH_OBR_WDG_SW (1 << 2)
#define FLASH_OBR_RDPRT (1 << 1)
#define FLASH_OBR_OPTERR (1 << 0)
/* --- FLASH Keys -----------------------------------------------------------*/
#define RDP_KEY ((u16)0x00a5)
#define FLASH_KEY1 ((u32)0x45670123)
#define FLASH_KEY2 ((u32)0xcdef89ab)
#define FLASH_RDP_KEY ((u16)0x00a5)
#define FLASH_KEYR_KEY1 ((u32)0x45670123)
#define FLASH_KEYR_KEY2 ((u32)0xcdef89ab)
/* --- Function prototypes ------------------------------------------------- */

112
include/libopencm3/stm32/f2/flash.h
View File

@ -43,76 +43,76 @@
/* --- FLASH_ACR values ---------------------------------------------------- */
#define FLASH_DCRST (1 << 12)
#define FLASH_ICRST (1 << 11)
#define FLASH_DCE (1 << 10)
#define FLASH_ICE (1 << 9)
#define FLASH_PRFTEN (1 << 8)
#define FLASH_LATENCY_0WS 0x00
#define FLASH_LATENCY_1WS 0x01
#define FLASH_LATENCY_2WS 0x02
#define FLASH_LATENCY_3WS 0x03
#define FLASH_LATENCY_4WS 0x04
#define FLASH_LATENCY_5WS 0x05
#define FLASH_LATENCY_6WS 0x06
#define FLASH_LATENCY_7WS 0x07
#define FLASH_ACR_DCRST (1 << 12)
#define FLASH_ACR_ICRST (1 << 11)
#define FLASH_ACR_DCE (1 << 10)
#define FLASH_ACR_ICE (1 << 9)
#define FLASH_ACR_PRFTEN (1 << 8)
#define FLASH_ACR_LATENCY_0WS 0x00
#define FLASH_ACR_LATENCY_1WS 0x01
#define FLASH_ACR_LATENCY_2WS 0x02
#define FLASH_ACR_LATENCY_3WS 0x03
#define FLASH_ACR_LATENCY_4WS 0x04
#define FLASH_ACR_LATENCY_5WS 0x05
#define FLASH_ACR_LATENCY_6WS 0x06
#define FLASH_ACR_LATENCY_7WS 0x07
/* --- FLASH_SR values ----------------------------------------------------- */
#define FLASH_BSY (1 << 16)
#define FLASH_PGSERR (1 << 7)
#define FLASH_PGPERR (1 << 6)
#define FLASH_PGAERR (1 << 5)
#define FLASH_WRPERR (1 << 4)
#define FLASH_OPERR (1 << 1)
#define FLASH_EOP (1 << 0)
#define FLASH_SR_BSY (1 << 16)
#define FLASH_SR_PGSERR (1 << 7)
#define FLASH_SR_PGPERR (1 << 6)
#define FLASH_SR_PGAERR (1 << 5)
#define FLASH_SR_WRPERR (1 << 4)
#define FLASH_SR_OPERR (1 << 1)
#define FLASH_SR_EOP (1 << 0)
/* --- FLASH_CR values ----------------------------------------------------- */
#define FLASH_LOCK (1 << 31)
#define FLASH_ERRIE (1 << 25)
#define FLASH_EOPIE (1 << 24)
#define FLASH_STRT (1 << 16)
#define FLASH_MER (1 << 2)
#define FLASH_SER (1 << 1)
#define FLASH_PG (1 << 0)
#define FLASH_SECTOR_0 (0x00 << 3)
#define FLASH_SECTOR_1 (0x01 << 3)
#define FLASH_SECTOR_2 (0x02 << 3)
#define FLASH_SECTOR_3 (0x03 << 3)
#define FLASH_SECTOR_4 (0x04 << 3)
#define FLASH_SECTOR_5 (0x05 << 3)
#define FLASH_SECTOR_6 (0x06 << 3)
#define FLASH_SECTOR_7 (0x07 << 3)
#define FLASH_SECTOR_8 (0x08 << 3)
#define FLASH_SECTOR_9 (0x09 << 3)
#define FLASH_SECTOR_10 (0x0a << 3)
#define FLASH_SECTOR_11 (0x0b << 3)
#define FLASH_PROGRAM_X8 (0x00 << 8)
#define FLASH_PROGRAM_X16 (0x01 << 8)
#define FLASH_PROGRAM_X32 (0x02 << 8)
#define FLASH_PROGRAM_X64 (0x03 << 8)
#define FLASH_CR_LOCK (1 << 31)
#define FLASH_CR_ERRIE (1 << 25)
#define FLASH_CR_EOPIE (1 << 24)
#define FLASH_CR_STRT (1 << 16)
#define FLASH_CR_MER (1 << 2)
#define FLASH_CR_SER (1 << 1)
#define FLASH_CR_PG (1 << 0)
#define FLASH_CR_SECTOR_0 (0x00 << 3)
#define FLASH_CR_SECTOR_1 (0x01 << 3)
#define FLASH_CR_SECTOR_2 (0x02 << 3)
#define FLASH_CR_SECTOR_3 (0x03 << 3)
#define FLASH_CR_SECTOR_4 (0x04 << 3)
#define FLASH_CR_SECTOR_5 (0x05 << 3)
#define FLASH_CR_SECTOR_6 (0x06 << 3)
#define FLASH_CR_SECTOR_7 (0x07 << 3)
#define FLASH_CR_SECTOR_8 (0x08 << 3)
#define FLASH_CR_SECTOR_9 (0x09 << 3)
#define FLASH_CR_SECTOR_10 (0x0a << 3)
#define FLASH_CR_SECTOR_11 (0x0b << 3)
#define FLASH_CR_PROGRAM_X8 (0x00 << 8)
#define FLASH_CR_PROGRAM_X16 (0x01 << 8)
#define FLASH_CR_PROGRAM_X32 (0x02 << 8)
#define FLASH_CR_PROGRAM_X64 (0x03 << 8)
/* --- FLASH_OPTCR values -------------------------------------------------- */
/* FLASH_OPTCR[27:16]: nWRP */
/* FLASH_OBR[15:8]: RDP */
#define FLASH_NRST_STDBY (1 << 7)
#define FLASH_NRST_STOP (1 << 6)
#define FLASH_WDG_SW (1 << 5)
#define FLASH_OPTSTRT (1 << 1)
#define FLASH_OPTLOCK (1 << 0)
#define FLASH_BOR_LEVEL_3 (0x00 << 2)
#define FLASH_BOR_LEVEL_2 (0x01 << 2)
#define FLASH_BOR_LEVEL_1 (0x02 << 2)
#define FLASH_BOR_OFF (0x03 << 2)
#define FLASH_OPTCR_NRST_STDBY (1 << 7)
#define FLASH_OPTCR_NRST_STOP (1 << 6)
#define FLASH_OPTCR_WDG_SW (1 << 5)
#define FLASH_OPTCR_OPTSTRT (1 << 1)
#define FLASH_OPTCR_OPTLOCK (1 << 0)
#define FLASH_OPTCR_BOR_LEVEL_3 (0x00 << 2)
#define FLASH_OPTCR_BOR_LEVEL_2 (0x01 << 2)
#define FLASH_OPTCR_BOR_LEVEL_1 (0x02 << 2)
#define FLASH_OPTCR_BOR_OFF (0x03 << 2)
/* --- FLASH Keys -----------------------------------------------------------*/
#define FLASH_KEY1 ((u32)0x45670123)
#define FLASH_KEY2 ((u32)0xcdef89ab)
#define FLASH_OPTKEY1 ((u32)0x08192a3b)
#define FLASH_OPTKEY2 ((u32)0x4c5d6e7f)
#define FLASH_KEYR_KEY1 ((u32)0x45670123)
#define FLASH_KEYR_KEY2 ((u32)0xcdef89ab)
#define FLASH_OPTKEYR_KEY1 ((u32)0x08192a3b)
#define FLASH_OPTKEYR_KEY2 ((u32)0x4c5d6e7f)
/* --- Function prototypes ------------------------------------------------- */

112
include/libopencm3/stm32/f4/flash.h
View File

@ -42,76 +42,76 @@
/* --- FLASH_ACR values ---------------------------------------------------- */
#define FLASH_DCRST (1 << 12)
#define FLASH_ICRST (1 << 11)
#define FLASH_DCE (1 << 10)
#define FLASH_ICE (1 << 9)
#define FLASH_PRFTEN (1 << 8)
#define FLASH_LATENCY_0WS 0x00
#define FLASH_LATENCY_1WS 0x01
#define FLASH_LATENCY_2WS 0x02
#define FLASH_LATENCY_3WS 0x03
#define FLASH_LATENCY_4WS 0x04
#define FLASH_LATENCY_5WS 0x05
#define FLASH_LATENCY_6WS 0x06
#define FLASH_LATENCY_7WS 0x07
#define FLASH_ACR_DCRST (1 << 12)
#define FLASH_ACR_ICRST (1 << 11)
#define FLASH_ACR_DCE (1 << 10)
#define FLASH_ACR_ICE (1 << 9)
#define FLASH_ACR_PRFTEN (1 << 8)
#define FLASH_ACR_LATENCY_0WS 0x00
#define FLASH_ACR_LATENCY_1WS 0x01
#define FLASH_ACR_LATENCY_2WS 0x02
#define FLASH_ACR_LATENCY_3WS 0x03
#define FLASH_ACR_LATENCY_4WS 0x04
#define FLASH_ACR_LATENCY_5WS 0x05
#define FLASH_ACR_LATENCY_6WS 0x06
#define FLASH_ACR_LATENCY_7WS 0x07
/* --- FLASH_SR values ----------------------------------------------------- */
#define FLASH_BSY (1 << 16)
#define FLASH_PGSERR (1 << 7)
#define FLASH_PGPERR (1 << 6)
#define FLASH_PGAERR (1 << 5)
#define FLASH_WRPERR (1 << 4)
#define FLASH_OPERR (1 << 1)
#define FLASH_EOP (1 << 0)
#define FLASH_SR_BSY (1 << 16)
#define FLASH_SR_PGSERR (1 << 7)
#define FLASH_SR_PGPERR (1 << 6)
#define FLASH_SR_PGAERR (1 << 5)
#define FLASH_SR_WRPERR (1 << 4)
#define FLASH_SR_OPERR (1 << 1)
#define FLASH_SR_EOP (1 << 0)
/* --- FLASH_CR values ----------------------------------------------------- */
#define FLASH_LOCK (1 << 31)
#define FLASH_ERRIE (1 << 25)
#define FLASH_EOPIE (1 << 24)
#define FLASH_STRT (1 << 16)
#define FLASH_MER (1 << 2)
#define FLASH_SER (1 << 1)
#define FLASH_PG (1 << 0)
#define FLASH_SECTOR_0 (0x00 << 3)
#define FLASH_SECTOR_1 (0x01 << 3)
#define FLASH_SECTOR_2 (0x02 << 3)
#define FLASH_SECTOR_3 (0x03 << 3)
#define FLASH_SECTOR_4 (0x04 << 3)
#define FLASH_SECTOR_5 (0x05 << 3)
#define FLASH_SECTOR_6 (0x06 << 3)
#define FLASH_SECTOR_7 (0x07 << 3)
#define FLASH_SECTOR_8 (0x08 << 3)
#define FLASH_SECTOR_9 (0x09 << 3)
#define FLASH_SECTOR_10 (0x0a << 3)
#define FLASH_SECTOR_11 (0x0b << 3)
#define FLASH_PROGRAM_X8 (0x00 << 8)
#define FLASH_PROGRAM_X16 (0x01 << 8)
#define FLASH_PROGRAM_X32 (0x02 << 8)
#define FLASH_PROGRAM_X64 (0x03 << 8)
#define FLASH_CR_LOCK (1 << 31)
#define FLASH_CR_ERRIE (1 << 25)
#define FLASH_CR_EOPIE (1 << 24)
#define FLASH_CR_STRT (1 << 16)
#define FLASH_CR_MER (1 << 2)
#define FLASH_CR_SER (1 << 1)
#define FLASH_CR_PG (1 << 0)
#define FLASH_CR_SECTOR_0 (0x00 << 3)
#define FLASH_CR_SECTOR_1 (0x01 << 3)
#define FLASH_CR_SECTOR_2 (0x02 << 3)
#define FLASH_CR_SECTOR_3 (0x03 << 3)
#define FLASH_CR_SECTOR_4 (0x04 << 3)
#define FLASH_CR_SECTOR_5 (0x05 << 3)
#define FLASH_CR_SECTOR_6 (0x06 << 3)
#define FLASH_CR_SECTOR_7 (0x07 << 3)
#define FLASH_CR_SECTOR_8 (0x08 << 3)
#define FLASH_CR_SECTOR_9 (0x09 << 3)
#define FLASH_CR_SECTOR_10 (0x0a << 3)
#define FLASH_CR_SECTOR_11 (0x0b << 3)
#define FLASH_CR_PROGRAM_X8 (0x00 << 8)
#define FLASH_CR_PROGRAM_X16 (0x01 << 8)
#define FLASH_CR_PROGRAM_X32 (0x02 << 8)
#define FLASH_CR_PROGRAM_X64 (0x03 << 8)
/* --- FLASH_OPTCR values -------------------------------------------------- */
/* FLASH_OPTCR[27:16]: nWRP */
/* FLASH_OBR[15:8]: RDP */
#define FLASH_NRST_STDBY (1 << 7)
#define FLASH_NRST_STOP (1 << 6)
#define FLASH_WDG_SW (1 << 5)
#define FLASH_OPTSTRT (1 << 1)
#define FLASH_OPTLOCK (1 << 0)
#define FLASH_BOR_LEVEL_3 (0x00 << 2)
#define FLASH_BOR_LEVEL_2 (0x01 << 2)
#define FLASH_BOR_LEVEL_1 (0x02 << 2)
#define FLASH_BOR_OFF (0x03 << 2)
#define FLASH_OPTCR_NRST_STDBY (1 << 7)
#define FLASH_OPTCR_NRST_STOP (1 << 6)
#define FLASH_OPTCR_WDG_SW (1 << 5)
#define FLASH_OPTCR_OPTSTRT (1 << 1)
#define FLASH_OPTCR_OPTLOCK (1 << 0)
#define FLASH_OPTCR_BOR_LEVEL_3 (0x00 << 2)
#define FLASH_OPTCR_BOR_LEVEL_2 (0x01 << 2)
#define FLASH_OPTCR_BOR_LEVEL_1 (0x02 << 2)
#define FLASH_OPTCR_BOR_OFF (0x03 << 2)
/* --- FLASH Keys -----------------------------------------------------------*/
#define FLASH_KEY1 ((u32)0x45670123)
#define FLASH_KEY2 ((u32)0xcdef89ab)
#define FLASH_OPTKEY1 ((u32)0x08192a3b)
#define FLASH_OPTKEY2 ((u32)0x4c5d6e7f)
#define FLASH_KEYR_KEY1 ((u32)0x45670123)
#define FLASH_KEYR_KEY2 ((u32)0xcdef89ab)
#define FLASH_OPTKEYR_KEY1 ((u32)0x08192a3b)
#define FLASH_OPTKEYR_KEY2 ((u32)0x4c5d6e7f)
/* --- Function prototypes ------------------------------------------------- */

98
include/libopencm3/stm32/l1/flash.h
View File

@ -45,70 +45,70 @@
/* --- FLASH_ACR values ---------------------------------------------------- */
#define FLASH_RUNPD (1 << 4)
#define FLASH_SLEEPPD (1 << 3)
#define FLASH_ACC64 (1 << 2)
#define FLASH_PRFTEN (1 << 1)
#define FLASH_LATENCY_0WS 0x00
#define FLASH_LATENCY_1WS 0x01
#define FLASH_ACR_RUNPD (1 << 4)
#define FLASH_ACR_SLEEPPD (1 << 3)
#define FLASH_ACR_ACC64 (1 << 2)
#define FLASH_ACR_PRFTEN (1 << 1)
#define FLASH_ACR_LATENCY_0WS 0x00
#define FLASH_ACR_LATENCY_1WS 0x01
/* --- FLASH_PECR values. Program/erase control register */
#define FLASH_OBL_LAUNCH (1 << 18)
#define FLASH_ERRIE (1 << 17)
#define FLASH_EOPIE (1 << 16)
#define FLASH_PARALLBANK (1 << 15)
#define FLASH_FPRG (1 << 10)
#define FLASH_ERASE (1 << 9)
#define FLASH_FTDW (1 << 8)
#define FLASH_FTDW (1 << 8)
#define FLASH_DATA (1 << 4)
#define FLASH_PROG (1 << 3)
#define FLASH_OPTLOCK (1 << 2)
#define FLASH_PRGLOCK (1 << 1)
#define FLASH_PELOCK (1 << 0)
#define FLASH_PECR_OBL_LAUNCH (1 << 18)
#define FLASH_PECR_ERRIE (1 << 17)
#define FLASH_PECR_EOPIE (1 << 16)
#define FLASH_PECR_PARALLBANK (1 << 15)
#define FLASH_PECR_FPRG (1 << 10)
#define FLASH_PECR_ERASE (1 << 9)
#define FLASH_PECR_FTDW (1 << 8)
#define FLASH_PECR_FTDW (1 << 8)
#define FLASH_PECR_DATA (1 << 4)
#define FLASH_PECR_PROG (1 << 3)
#define FLASH_PECR_OPTLOCK (1 << 2)
#define FLASH_PECR_PRGLOCK (1 << 1)
#define FLASH_PECR_PELOCK (1 << 0)
/* Power down key register (FLASH_PDKEYR) */
#define FLASH_PDKEY1 ((u32)0x04152637)
#define FLASH_PDKEY2 ((u32)0xFAFBFCFD)
#define FLASH_PDKEYR_PDKEY1 ((u32)0x04152637)
#define FLASH_PDKEYR_PDKEY2 ((u32)0xFAFBFCFD)
/* Program/erase key register (FLASH_PEKEYR) */
#define FLASH_PEKEY1 ((u32)0x89ABCDEF)
#define FLASH_PEKEY2 ((u32)0x02030405)
#define FLASH_PEKEYR_PEKEY1 ((u32)0x89ABCDEF)
#define FLASH_PEKEYR_PEKEY2 ((u32)0x02030405)
/* Program memory key register (FLASH_PRGKEYR) */
#define FLASH_PRGKEY1 ((u32)0x8C9DAEBF)
#define FLASH_PRGKEY2 ((u32)0x13141516)
#define FLASH_PRGKEYR_PRGKEY1 ((u32)0x8C9DAEBF)
#define FLASH_PRGKEYR_PRGKEY2 ((u32)0x13141516)
/* Option byte key register (FLASH_OPTKEYR) */
#define FLASH_OPTKEY1 ((u32)0xFBEAD9C8)
#define FLASH_OPTKEY2 ((u32)0x24252627)
#define FLASH_OPTKEYR_OPTKEY1 ((u32)0xFBEAD9C8)
#define FLASH_OPTKEYR_OPTKEY2 ((u32)0x24252627)
/* --- FLASH_SR values ----------------------------------------------------- */
#define FLASH_OPTVERRUSR (1 << 12)
#define FLASH_OPTVERR (1 << 11)
#define FLASH_SIZEERR (1 << 10)
#define FLASH_PGAERR (1 << 9)
#define FLASH_WRPERR (1 << 8)
#define FLASH_READY (1 << 3)
#define FLASH_ENDHV (1 << 2)
#define FLASH_EOP (1 << 1)
#define FLASH_BSY (1 << 0)
#define FLASH_SR_OPTVERRUSR (1 << 12)
#define FLASH_SR_OPTVERR (1 << 11)
#define FLASH_SR_SIZEERR (1 << 10)
#define FLASH_SR_PGAERR (1 << 9)
#define FLASH_SR_WRPERR (1 << 8)
#define FLASH_SR_READY (1 << 3)
#define FLASH_SR_ENDHV (1 << 2)
#define FLASH_SR_EOP (1 << 1)
#define FLASH_SR_BSY (1 << 0)
/* --- FLASH_OBR values ----------------------------------------------------- */
#define FLASH_BFB2 (1 << 23)
#define FLASH_NRST_STDBY (1 << 22)
#define FLASH_NRST_STOP (1 << 21)
#define FLASH_IWDG_SW (1 << 20)
#define FLASH_BOR_OFF (0x0 << 16)
#define FLASH_BOR_LEVEL_1 (0x8 << 16)
#define FLASH_BOR_LEVEL_2 (0x9 << 16)
#define FLASH_BOR_LEVEL_3 (0xa << 16)
#define FLASH_BOR_LEVEL_4 (0xb << 16)
#define FLASH_BOR_LEVEL_5 (0xc << 16)
#define FLASH_RDPRT_LEVEL_0 (0xaa)
#define FLASH_RDPRT_LEVEL_1 (0x00)
#define FLASH_RDPRT_LEVEL_2 (0xcc)
#define FLASH_OBR_BFB2 (1 << 23)
#define FLASH_OBR_NRST_STDBY (1 << 22)
#define FLASH_OBR_NRST_STOP (1 << 21)
#define FLASH_OBR_IWDG_SW (1 << 20)
#define FLASH_OBR_BOR_OFF (0x0 << 16)
#define FLASH_OBR_BOR_LEVEL_1 (0x8 << 16)
#define FLASH_OBR_BOR_LEVEL_2 (0x9 << 16)
#define FLASH_OBR_BOR_LEVEL_3 (0xa << 16)
#define FLASH_OBR_BOR_LEVEL_4 (0xb << 16)
#define FLASH_OBR_BOR_LEVEL_5 (0xc << 16)
#define FLASH_OBR_RDPRT_LEVEL_0 (0xaa)
#define FLASH_OBR_RDPRT_LEVEL_1 (0x00)
#define FLASH_OBR_RDPRT_LEVEL_2 (0xcc)
/* --- Function prototypes ------------------------------------------------- */

63
lib/stm32/f1/flash.c
View File

@ -22,22 +22,22 @@
void flash_prefetch_buffer_enable(void)
{
FLASH_ACR |= FLASH_PRFTBE;
FLASH_ACR |= FLASH_ACR_PRFTBE;
}
void flash_prefetch_buffer_disable(void)
{
FLASH_ACR &= ~FLASH_PRFTBE;
FLASH_ACR &= ~FLASH_ACR_PRFTBE;
}
void flash_halfcycle_enable(void)
{
FLASH_ACR |= FLASH_HLFCYA;
FLASH_ACR |= FLASH_ACR_HLFCYA;
}
void flash_halfcycle_disable(void)
{
FLASH_ACR &= ~FLASH_HLFCYA;
FLASH_ACR &= ~FLASH_ACR_HLFCYA;
}
void flash_set_ws(u32 ws)
@ -53,33 +53,33 @@ void flash_set_ws(u32 ws)
void flash_unlock(void)
{
/* Authorize the FPEC access. */
FLASH_KEYR = FLASH_KEY1;
FLASH_KEYR = FLASH_KEY2;
FLASH_KEYR = FLASH_KEYR_KEY1;
FLASH_KEYR = FLASH_KEYR_KEY2;
}
void flash_lock(void)
{
FLASH_CR |= FLASH_LOCK;
FLASH_CR |= FLASH_CR_LOCK;
}
void flash_clear_pgerr_flag(void)
{
FLASH_SR |= FLASH_PGERR;
FLASH_SR |= FLASH_SR_PGERR;
}
void flash_clear_eop_flag(void)
{
FLASH_SR |= FLASH_EOP;
FLASH_SR |= FLASH_SR_EOP;
}
void flash_clear_wrprterr_flag(void)
{
FLASH_SR |= FLASH_WRPRTERR;
FLASH_SR |= FLASH_SR_WRPRTERR;
}
void flash_clear_bsy_flag(void)
{
FLASH_SR &= ~FLASH_BSY;
FLASH_SR &= ~FLASH_SR_BSY;
}
void flash_clear_status_flags(void)
@ -92,13 +92,14 @@ void flash_clear_status_flags(void)
void flash_unlock_option_bytes(void)
{
FLASH_OPTKEYR = FLASH_KEY1;
FLASH_OPTKEYR = FLASH_KEY2;
/* F1 uses same keys for flash and option */
FLASH_OPTKEYR = FLASH_KEYR_KEY1;
FLASH_OPTKEYR = FLASH_KEYR_KEY2;
}
void flash_wait_for_last_operation(void)
{
while ((FLASH_SR & FLASH_BSY) == FLASH_BSY)
while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY)
;
}
@ -108,7 +109,7 @@ void flash_program_word(u32 address, u32 data)
flash_wait_for_last_operation();
/* Enable writes to flash. */
FLASH_CR |= FLASH_PG;
FLASH_CR |= FLASH_CR_PG;
/* Program the first half of the word. */
(*(volatile u16 *)address) = (u16)data;
@ -123,67 +124,67 @@ void flash_program_word(u32 address, u32 data)
flash_wait_for_last_operation();
/* Disable writes to flash. */
FLASH_CR &= ~FLASH_PG;
FLASH_CR &= ~FLASH_CR_PG;
}
void flash_program_half_word(u32 address, u16 data)
{
flash_wait_for_last_operation();
FLASH_CR |= FLASH_PG;
FLASH_CR |= FLASH_CR_PG;
(*(volatile u16 *)address) = data;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */
FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
}
void flash_erase_page(u32 page_address)
{
flash_wait_for_last_operation();
FLASH_CR |= FLASH_PER;
FLASH_CR |= FLASH_CR_PER;
FLASH_AR = page_address;
FLASH_CR |= FLASH_STRT;
FLASH_CR |= FLASH_CR_STRT;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_PER;
FLASH_CR &= ~FLASH_CR_PER;
}
void flash_erase_all_pages(void)
{
flash_wait_for_last_operation();
FLASH_CR |= FLASH_MER; /* Enable mass erase. */
FLASH_CR |= FLASH_STRT; /* Trigger the erase. */
FLASH_CR |= FLASH_CR_MER; /* Enable mass erase. */
FLASH_CR |= FLASH_CR_STRT; /* Trigger the erase. */
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_MER; /* Disable mass erase. */
FLASH_CR &= ~FLASH_CR_MER; /* Disable mass erase. */
}
void flash_erase_option_bytes(void)
{
flash_wait_for_last_operation();
if ((FLASH_CR & FLASH_OPTWRE) == 0)
if ((FLASH_CR & FLASH_CR_OPTWRE) == 0)
flash_unlock_option_bytes();
FLASH_CR |= FLASH_OPTER; /* Enable option byte erase. */
FLASH_CR |= FLASH_STRT;
FLASH_CR |= FLASH_CR_OPTER; /* Enable option byte erase. */
FLASH_CR |= FLASH_CR_STRT;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_OPTER; /* Disable option byte erase. */
FLASH_CR &= ~FLASH_CR_OPTER; /* Disable option byte erase. */
}
void flash_program_option_bytes(u32 address, u16 data)
{
flash_wait_for_last_operation();
if ((FLASH_CR & FLASH_OPTWRE) == 0)
if ((FLASH_CR & FLASH_CR_OPTWRE) == 0)
flash_unlock_option_bytes();
FLASH_CR |= FLASH_OPTPG; /* Enable option byte programming. */
FLASH_CR |= FLASH_CR_OPTPG; /* Enable option byte programming. */
(*(volatile u16 *)address) = data;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_OPTPG; /* Disable option byte programming. */
FLASH_CR &= ~FLASH_CR_OPTPG; /* Disable option byte programming. */
}

16
lib/stm32/f1/rcc.c
View File

@ -761,7 +761,7 @@ void rcc_clock_setup_in_hsi_out_64mhz(void)
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
flash_set_ws(FLASH_LATENCY_2WS);
flash_set_ws(FLASH_ACR_LATENCY_2WS);
/*
* Set the PLL multiplication factor to 16.
@ -814,7 +814,7 @@ void rcc_clock_setup_in_hsi_out_48mhz(void)
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
flash_set_ws(FLASH_LATENCY_1WS);
flash_set_ws(FLASH_ACR_LATENCY_1WS);
/*
* Set the PLL multiplication factor to 12.
@ -865,7 +865,7 @@ void rcc_clock_setup_in_hsi_out_24mhz(void) {
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
flash_set_ws(FLASH_LATENCY_0WS);
flash_set_ws(FLASH_ACR_LATENCY_0WS);
/*
* Set the PLL multiplication factor to 6.
@ -922,7 +922,7 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void)
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
flash_set_ws(FLASH_LATENCY_0WS);
flash_set_ws(FLASH_ACR_LATENCY_0WS);
/*
* Set the PLL multiplication factor to 3.
@ -985,7 +985,7 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
flash_set_ws(FLASH_LATENCY_2WS);
flash_set_ws(FLASH_ACR_LATENCY_2WS);
/*
* Set the PLL multiplication factor to 9.
@ -1048,7 +1048,7 @@ void rcc_clock_setup_in_hse_12mhz_out_72mhz(void)
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
flash_set_ws(FLASH_LATENCY_2WS);
flash_set_ws(FLASH_ACR_LATENCY_2WS);
/*
* Set the PLL multiplication factor to 9.
@ -1111,7 +1111,7 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
flash_set_ws(FLASH_LATENCY_2WS);
flash_set_ws(FLASH_ACR_LATENCY_2WS);
/*
* Set the PLL multiplication factor to 9.
@ -1158,7 +1158,7 @@ void rcc_clock_setup_in_hse_25mhz_out_72mhz(void)
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
flash_set_ws(FLASH_LATENCY_2WS);
flash_set_ws(FLASH_ACR_LATENCY_2WS);
/*
* Set prescalers for AHB, ADC, ABP1, ABP2.

72
lib/stm32/f2/flash.c
View File

@ -28,42 +28,42 @@ static inline void flash_set_program_size(u32 psize)
void flash_data_cache_enable(void)
{
FLASH_ACR |= FLASH_DCE;
FLASH_ACR |= FLASH_ACR_DCE;
}
void flash_dcache_disable(void)
{
FLASH_ACR &= ~FLASH_DCE;
FLASH_ACR &= ~FLASH_ACR_DCE;
}
void flash_icache_enable(void)
{
FLASH_ACR |= FLASH_ICE;
FLASH_ACR |= FLASH_ACR_ICE;
}
void flash_icache_disable(void)
{
FLASH_ACR &= ~FLASH_ICE;
FLASH_ACR &= ~FLASH_ACR_ICE;
}
void flash_prefetch_enable(void)
{
FLASH_ACR |= FLASH_PRFTEN;
FLASH_ACR |= FLASH_ACR_PRFTEN;
}
void flash_prefetch_disable(void)
{
FLASH_ACR &= ~FLASH_PRFTEN;
FLASH_ACR &= ~FLASH_ACR_PRFTEN;
}
void flash_dcache_reset(void)
{
FLASH_ACR |= FLASH_DCRST;
FLASH_ACR |= FLASH_ACR_DCRST;
}
void flash_icache_reset(void)
{
FLASH_ACR |= FLASH_ICRST;
FLASH_ACR |= FLASH_ACR_ICRST;
}
void flash_set_ws(u32 ws)
@ -79,43 +79,43 @@ void flash_set_ws(u32 ws)
void flash_unlock(void)
{
/* Authorize the FPEC access. */
FLASH_KEYR = FLASH_KEY1;
FLASH_KEYR = FLASH_KEY2;
FLASH_KEYR = FLASH_KEYR_KEY1;
FLASH_KEYR = FLASH_KEYR_KEY2;
}
void flash_lock(void)
{
FLASH_CR |= FLASH_LOCK;
FLASH_CR |= FLASH_CR_LOCK;
}
void flash_clear_pgserr_flag(void)
{
FLASH_SR |= FLASH_PGSERR;
FLASH_SR |= FLASH_SR_PGSERR;
}
void flash_clear_pgperr_flag(void)
{
FLASH_SR |= FLASH_PGPERR;
FLASH_SR |= FLASH_SR_PGPERR;
}
void flash_clear_pgaerr_flag(void)
{
FLASH_SR |= FLASH_PGAERR;
FLASH_SR |= FLASH_SR_PGAERR;
}
void flash_clear_eop_flag(void)
{
FLASH_SR |= FLASH_EOP;
FLASH_SR |= FLASH_SR_EOP;
}
void flash_clear_wrperr_flag(void)
{
FLASH_SR |= FLASH_WRPERR;
FLASH_SR |= FLASH_SR_WRPERR;
}
void flash_clear_bsy_flag(void)
{
FLASH_SR &= ~FLASH_BSY;
FLASH_SR &= ~FLASH_SR_BSY;
}
void flash_clear_status_flags(void)
@ -130,18 +130,18 @@ void flash_clear_status_flags(void)
void flash_unlock_option_bytes(void)
{
FLASH_OPTKEYR = FLASH_OPTKEY1;
FLASH_OPTKEYR = FLASH_OPTKEY2;
FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1;
FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2;
}
void flash_lock_option_bytes(void)
{
FLASH_OPTCR |= FLASH_OPTLOCK;
FLASH_OPTCR |= FLASH_OPTCR_OPTLOCK;
}
void flash_wait_for_last_operation(void)
{
while ((FLASH_SR & FLASH_BSY) == FLASH_BSY)
while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY)
;
}
@ -152,7 +152,7 @@ void flash_program_double_word(u32 address, u64 data, u32 program_size)
flash_set_program_size(program_size);
/* Enable writes to flash. */
FLASH_CR |= FLASH_PG;
FLASH_CR |= FLASH_CR_PG;
/* Program the first half of the word. */
MMIO64(address) = data;
@ -161,7 +161,7 @@ void flash_program_double_word(u32 address, u64 data, u32 program_size)
flash_wait_for_last_operation();
/* Disable writes to flash. */
FLASH_CR &= ~FLASH_PG;
FLASH_CR &= ~FLASH_CR_PG;
}
void flash_program_word(u32 address, u32 data, u32 program_size)
@ -171,7 +171,7 @@ void flash_program_word(u32 address, u32 data, u32 program_size)
flash_set_program_size(program_size);
/* Enable writes to flash. */
FLASH_CR |= FLASH_PG;
FLASH_CR |= FLASH_CR_PG;
/* Program the first half of the word. */
MMIO32(address) = data;
@ -180,7 +180,7 @@ void flash_program_word(u32 address, u32 data, u32 program_size)
flash_wait_for_last_operation();
/* Disable writes to flash. */
FLASH_CR &= ~FLASH_PG;
FLASH_CR &= ~FLASH_CR_PG;
}
void flash_program_half_word(u32 address, u16 data, u32 program_size)
@ -188,13 +188,13 @@ void flash_program_half_word(u32 address, u16 data, u32 program_size)
flash_wait_for_last_operation();
flash_set_program_size(program_size);
FLASH_CR |= FLASH_PG;
FLASH_CR |= FLASH_CR_PG;
MMIO16(address) = data;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */
FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
}
void flash_program_byte(u32 address, u8 data, u32 program_size)
@ -202,13 +202,13 @@ void flash_program_byte(u32 address, u8 data, u32 program_size)
flash_wait_for_last_operation();
flash_set_program_size(program_size);
FLASH_CR |= FLASH_PG;
FLASH_CR |= FLASH_CR_PG;
MMIO8(address) = data;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */
FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
}
void flash_erase_sector(u32 sector, u32 program_size)
@ -218,10 +218,10 @@ void flash_erase_sector(u32 sector, u32 program_size)
FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3);
FLASH_CR |= sector;
FLASH_CR |= FLASH_STRT;
FLASH_CR |= FLASH_CR_STRT;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_SER;
FLASH_CR &= ~FLASH_CR_SER;
FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3);
}
@ -230,21 +230,21 @@ void flash_erase_all_sectors(u32 program_size)
flash_wait_for_last_operation();
flash_set_program_size(program_size);
FLASH_CR |= FLASH_MER; /* Enable mass erase. */
FLASH_CR |= FLASH_STRT; /* Trigger the erase. */
FLASH_CR |= FLASH_CR_MER; /* Enable mass erase. */
FLASH_CR |= FLASH_CR_STRT; /* Trigger the erase. */
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_MER; /* Disable mass erase. */
FLASH_CR &= ~FLASH_CR_MER; /* Disable mass erase. */
}
void flash_program_option_bytes(u32 data)
{
flash_wait_for_last_operation();
if (FLASH_OPTCR & FLASH_OPTLOCK)
if (FLASH_OPTCR & FLASH_OPTCR_OPTLOCK)
flash_unlock_option_bytes();
FLASH_OPTCR = data & ~0x3;
FLASH_OPTCR |= FLASH_OPTSTRT; /* Enable option byte programming. */
FLASH_OPTCR |= FLASH_OPTCR_OPTSTRT; /* Enable option byte programming. */
flash_wait_for_last_operation();
}

2
lib/stm32/f2/rcc.c
View File

@ -37,7 +37,7 @@ const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] =
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.flash_config = FLASH_ICE | FLASH_DCE | FLASH_LATENCY_3WS,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},

74
lib/stm32/f4/flash.c
View File

@ -28,42 +28,42 @@ static inline void flash_set_program_size(u32 psize)
void flash_data_cache_enable(void)
{
FLASH_ACR |= FLASH_DCE;
FLASH_ACR |= FLASH_ACR_DCE;
}
void flash_dcache_disable(void)
{
FLASH_ACR &= ~FLASH_DCE;
FLASH_ACR &= ~FLASH_ACR_DCE;
}
void flash_icache_enable(void)
{
FLASH_ACR |= FLASH_ICE;
FLASH_ACR |= FLASH_ACR_ICE;
}
void flash_icache_disable(void)
{
FLASH_ACR &= ~FLASH_ICE;
FLASH_ACR &= ~FLASH_ACR_ICE;
}
void flash_prefetch_enable(void)
{
FLASH_ACR |= FLASH_PRFTEN;
FLASH_ACR |= FLASH_ACR_PRFTEN;
}
void flash_prefetch_disable(void)
{
FLASH_ACR &= ~FLASH_PRFTEN;
FLASH_ACR &= ~FLASH_ACR_PRFTEN;
}
void flash_dcache_reset(void)
{
FLASH_ACR |= FLASH_DCRST;
FLASH_ACR |= FLASH_ACR_DCRST;
}
void flash_icache_reset(void)
{
FLASH_ACR |= FLASH_ICRST;
FLASH_ACR |= FLASH_ACR_ICRST;
}
void flash_set_ws(u32 ws)
@ -79,43 +79,43 @@ void flash_set_ws(u32 ws)
void flash_unlock(void)
{
/* Authorize the FPEC access. */
FLASH_KEYR = FLASH_KEY1;
FLASH_KEYR = FLASH_KEY2;
FLASH_KEYR = FLASH_KEYR_KEY1;
FLASH_KEYR = FLASH_KEYR_KEY2;
}
void flash_lock(void)
{
FLASH_CR |= FLASH_LOCK;
FLASH_CR |= FLASH_CR_LOCK;
}
void flash_clear_pgserr_flag(void)
{
FLASH_SR |= FLASH_PGSERR;
FLASH_SR |= FLASH_SR_PGSERR;
}
void flash_clear_pgperr_flag(void)
{
FLASH_SR |= FLASH_PGPERR;
FLASH_SR |= FLASH_SR_PGPERR;
}
void flash_clear_pgaerr_flag(void)
{
FLASH_SR |= FLASH_PGAERR;
FLASH_SR |= FLASH_SR_PGAERR;
}
void flash_clear_eop_flag(void)
{
FLASH_SR |= FLASH_EOP;
FLASH_SR |= FLASH_SR_EOP;
}
void flash_clear_wrperr_flag(void)
{
FLASH_SR |= FLASH_WRPERR;
FLASH_SR |= FLASH_SR_WRPERR;
}
void flash_clear_bsy_flag(void)
{
FLASH_SR &= ~FLASH_BSY;
FLASH_SR &= ~FLASH_SR_BSY;
}
void flash_clear_status_flags(void)
@ -130,18 +130,18 @@ void flash_clear_status_flags(void)
void flash_unlock_option_bytes(void)
{
FLASH_OPTKEYR = FLASH_OPTKEY1;
FLASH_OPTKEYR = FLASH_OPTKEY2;
FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1;
FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2;
}
void flash_lock_option_bytes(void)
{
FLASH_OPTCR |= FLASH_OPTLOCK;
FLASH_OPTCR |= FLASH_OPTCR_OPTLOCK;
}
void flash_wait_for_last_operation(void)
{
while ((FLASH_SR & FLASH_BSY) == FLASH_BSY)
while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY)
;
}
@ -152,7 +152,7 @@ void flash_program_double_word(u32 address, u64 data, u32 program_size)
flash_set_program_size(program_size);
/* Enable writes to flash. */
FLASH_CR |= FLASH_PG;
FLASH_CR |= FLASH_CR_PG;
/* Program the first half of the word. */
MMIO64(address) = data;
@ -161,7 +161,7 @@ void flash_program_double_word(u32 address, u64 data, u32 program_size)
flash_wait_for_last_operation();
/* Disable writes to flash. */
FLASH_CR &= ~FLASH_PG;
FLASH_CR &= ~FLASH_CR_PG;
}
void flash_program_word(u32 address, u32 data, u32 program_size)
@ -171,7 +171,7 @@ void flash_program_word(u32 address, u32 data, u32 program_size)
flash_set_program_size(program_size);
/* Enable writes to flash. */
FLASH_CR |= FLASH_PG;
FLASH_CR |= FLASH_CR_PG;
/* Program the first half of the word. */
MMIO32(address) = data;
@ -180,7 +180,7 @@ void flash_program_word(u32 address, u32 data, u32 program_size)
flash_wait_for_last_operation();
/* Disable writes to flash. */
FLASH_CR &= ~FLASH_PG;
FLASH_CR &= ~FLASH_CR_PG;
}
void flash_program_half_word(u32 address, u16 data, u32 program_size)
@ -188,13 +188,13 @@ void flash_program_half_word(u32 address, u16 data, u32 program_size)
flash_wait_for_last_operation();
flash_set_program_size(program_size);
FLASH_CR |= FLASH_PG;
FLASH_CR |= FLASH_CR_PG;
MMIO16(address) = data;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */
FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
}
void flash_program_byte(u32 address, u8 data, u32 program_size)
@ -202,13 +202,13 @@ void flash_program_byte(u32 address, u8 data, u32 program_size)
flash_wait_for_last_operation();
flash_set_program_size(program_size);
FLASH_CR |= FLASH_PG;
FLASH_CR |= FLASH_CR_PG;
MMIO8(address) = data;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */
FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
}
void flash_erase_sector(u32 sector, u32 program_size)
@ -218,11 +218,11 @@ void flash_erase_sector(u32 sector, u32 program_size)
FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3);
FLASH_CR |= sector;
FLASH_CR |= FLASH_SER;
FLASH_CR |= FLASH_STRT;
FLASH_CR |= FLASH_CR_SER;
FLASH_CR |= FLASH_CR_STRT;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_SER;
FLASH_CR &= ~FLASH_CR_SER;
FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3);
}
@ -231,21 +231,21 @@ void flash_erase_all_sectors(u32 program_size)
flash_wait_for_last_operation();
flash_set_program_size(program_size);
FLASH_CR |= FLASH_MER; /* Enable mass erase. */
FLASH_CR |= FLASH_STRT; /* Trigger the erase. */
FLASH_CR |= FLASH_CR_MER; /* Enable mass erase. */
FLASH_CR |= FLASH_CR_STRT; /* Trigger the erase. */
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_MER; /* Disable mass erase. */
FLASH_CR &= ~FLASH_CR_MER; /* Disable mass erase. */
}
void flash_program_option_bytes(u32 data)
{
flash_wait_for_last_operation();
if (FLASH_OPTCR & FLASH_OPTLOCK)
if (FLASH_OPTCR & FLASH_OPTCR_OPTLOCK)
flash_unlock_option_bytes();
FLASH_OPTCR = data & ~0x3;
FLASH_OPTCR |= FLASH_OPTSTRT; /* Enable option byte programming. */
FLASH_OPTCR |= FLASH_OPTCR_OPTSTRT; /* Enable option byte programming. */
flash_wait_for_last_operation();
}

4
lib/stm32/f4/rcc.c
View File

@ -39,7 +39,7 @@ const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] =
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ICE | FLASH_DCE | FLASH_LATENCY_3WS,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
@ -51,7 +51,7 @@ const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] =
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.flash_config = FLASH_ICE | FLASH_DCE | FLASH_LATENCY_5WS,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_5WS,
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},

8
lib/stm32/l1/flash.c
View File

@ -23,22 +23,22 @@
void flash_64bit_enable(void)
{
FLASH_ACR |= FLASH_ACC64;
FLASH_ACR |= FLASH_ACR_ACC64;
}
void flash_64bit_disable(void)
{
FLASH_ACR &= ~FLASH_ACC64;
FLASH_ACR &= ~FLASH_ACR_ACC64;
}
void flash_prefetch_enable(void)
{
FLASH_ACR |= FLASH_PRFTEN;
FLASH_ACR |= FLASH_ACR_PRFTEN;
}
void flash_prefetch_disable(void)
{
FLASH_ACR &= ~FLASH_PRFTEN;
FLASH_ACR &= ~FLASH_ACR_PRFTEN;
}
void flash_set_ws(u32 ws)

6
lib/stm32/l1/rcc.c
View File

@ -39,7 +39,7 @@ const clock_scale_t clock_config[CLOCK_CONFIG_END] =
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = RANGE1,
.flash_config = FLASH_LATENCY_1WS,
.flash_config = FLASH_ACR_LATENCY_1WS,
.apb1_frequency = 24000000,
.apb2_frequency = 24000000,
},
@ -51,7 +51,7 @@ const clock_scale_t clock_config[CLOCK_CONFIG_END] =
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = RANGE1,
.flash_config = FLASH_LATENCY_1WS,
.flash_config = FLASH_ACR_LATENCY_1WS,
.apb1_frequency = 32000000,
.apb2_frequency = 32000000,
},
@ -60,7 +60,7 @@ const clock_scale_t clock_config[CLOCK_CONFIG_END] =
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = RANGE1,
.flash_config = FLASH_LATENCY_0WS,
.flash_config = FLASH_ACR_LATENCY_0WS,
.apb1_frequency = 16000000,
.apb2_frequency = 16000000,
},

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