Fergus Noble
13 years ago
1 changed files with 453 additions and 0 deletions
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/*
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* This file is part of the libopencm3 project. |
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* |
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> |
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* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com> |
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* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com> |
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* |
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* This program is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#ifndef LIBOPENCM3_RCC_H |
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#define LIBOPENCM3_RCC_H |
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#include <libopencm3/stm32/memorymap.h> |
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#include <libopencm3/cm3/common.h> |
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/* --- RCC registers ------------------------------------------------------- */ |
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#define RCC_CR MMIO32(RCC_BASE + 0x00) |
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#define RCC_PLLCFGR MMIO32(RCC_BASE + 0x04) |
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#define RCC_CFGR MMIO32(RCC_BASE + 0x08) |
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#define RCC_CIR MMIO32(RCC_BASE + 0x0c) |
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#define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x10) |
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#define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x14) |
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#define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x18) |
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/* RCC_BASE + 0x1C Reserved */ |
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#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x20) |
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#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x24) |
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/* RCC_BASE + 0x28 Reserved */ |
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/* RCC_BASE + 0x2C Reserved */ |
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#define RCC_AHB1ENR MMIO32(RCC_BASE + 0x30) |
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#define RCC_AHB2ENR MMIO32(RCC_BASE + 0x34) |
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#define RCC_AHB3ENR MMIO32(RCC_BASE + 0x38) |
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/* RCC_BASE + 0x3C Reserved */ |
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#define RCC_APB1ENR MMIO32(RCC_BASE + 0x40) |
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#define RCC_APB2ENR MMIO32(RCC_BASE + 0x44) |
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/* RCC_BASE + 0x48 Reserved */ |
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/* RCC_BASE + 0x4C Reserved */ |
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#define RCC_AHB1LPENR MMIO32(RCC_BASE + 0x50) |
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#define RCC_AHB2LPENR MMIO32(RCC_BASE + 0x54) |
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#define RCC_AHB3LPENR MMIO32(RCC_BASE + 0x58) |
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/* RCC_BASE + 0x5C Reserved */ |
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#define RCC_APB1LPENR MMIO32(RCC_BASE + 0x60) |
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#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x64) |
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/* RCC_BASE + 0x68 Reserved */ |
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/* RCC_BASE + 0x6C Reserved */ |
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#define RCC_BDCR MMIO32(RCC_BASE + 0x70) |
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#define RCC_CSR MMIO32(RCC_BASE + 0x74) |
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/* RCC_BASE + 0x78 Reserved */ |
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/* RCC_BASE + 0x7C Reserved */ |
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#define RCC_SSCGR MMIO32(RCC_BASE + 0x80) |
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#define RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84) |
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/* --- RCC_CR values ------------------------------------------------------- */ |
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#define RCC_CR_PLLI2SRDY (1 << 27) |
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#define RCC_CR_PLLI2SON (1 << 26) |
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#define RCC_CR_PLLRDY (1 << 25) |
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#define RCC_CR_PLLON (1 << 24) |
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#define RCC_CR_CSSON (1 << 19) |
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#define RCC_CR_HSEBYP (1 << 18) |
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#define RCC_CR_HSERDY (1 << 17) |
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#define RCC_CR_HSEON (1 << 16) |
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/* HSICAL: [15:8] */ |
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/* HSITRIM: [7:3] */ |
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#define RCC_CR_HSIRDY (1 << 1) |
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#define RCC_CR_HSION (1 << 0) |
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/* --- RCC_PLLCFGR values ------------------------------------------------------- */ |
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/* PLLQ: [27:24] */ |
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#define RCC_PLLCFGR_PLLQ_SHIFT 24 |
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#define RCC_PLLCFGR_PLLSRC (1 << 22) |
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/* PLLP: [17:16] */ |
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#define RCC_PLLCFGR_PLLP_SHIFT 16 |
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/* PLLN: [14:6] */ |
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#define RCC_PLLCFGR_PLLN_SHIFT 6 |
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/* PLLM: [5:0] */ |
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#define RCC_PLLCFGR_PLLM_SHIFT 0 |
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/* --- RCC_CFGR values ----------------------------------------------------- */ |
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/* MCO2: Microcontroller clock output 2 */ |
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#define RCC_CFGR_MCO2_SHIFT 30 |
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#define RCC_CFGR_MCO2_SYSCLK 0x0 |
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#define RCC_CFGR_MCO2_PLLI2S 0x1 |
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#define RCC_CFGR_MCO2_HSE 0x2 |
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#define RCC_CFGR_MCO2_PLL 0x3 |
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/* MCO1/2PRE: MCO Prescalers */ |
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#define RCC_CFGR_MCO2PRE_SHIFT 27 |
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#define RCC_CFGR_MCO1PRE_SHIFT 24 |
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#define RCC_CFGR_MCOPRE_DIV_NONE 0x0 |
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#define RCC_CFGR_MCOPRE_DIV_2 0x4 |
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#define RCC_CFGR_MCOPRE_DIV_3 0x5 |
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#define RCC_CFGR_MCOPRE_DIV_4 0x6 |
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#define RCC_CFGR_MCOPRE_DIV_5 0x7 |
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/* I2SSRC: I2S clock selection */ |
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#define RCC_CFGR_I2SSRC (1 << 23) |
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/* MCO1: Microcontroller clock output 1 */ |
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#define RCC_CFGR_MCO1_SHIFT 21 |
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#define RCC_CFGR_MCO1_HSI 0x0 |
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#define RCC_CFGR_MCO1_LSE 0x1 |
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#define RCC_CFGR_MCO1_HSE 0x2 |
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#define RCC_CFGR_MCO1_PLL 0x3 |
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/* RTCPRE: HSE division factor for RTC clock */ |
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#define RCC_CFGR_RTCPRE_SHIFT 21 |
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/* PPRE1/2: APB high-speed prescalers */ |
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#define RCC_CFGR_PPRE2_SHIFT 13 |
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#define RCC_CFGR_PPRE1_SHIFT 10 |
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#define RCC_CFGR_PPRE_DIV_NONE 0x0 |
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#define RCC_CFGR_PPRE_DIV_2 0x4 |
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#define RCC_CFGR_PPRE_DIV_4 0x5 |
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#define RCC_CFGR_PPRE_DIV_8 0x6 |
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#define RCC_CFGR_PPRE_DIV_16 0x7 |
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/* HPRE: AHB high-speed prescaler */ |
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#define RCC_CFGR_HPRE_SHIFT 4 |
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#define RCC_CFGR_HPRE_DIV_NONE 0x0 |
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#define RCC_CFGR_HPRE_DIV_2 (0x8+0) |
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#define RCC_CFGR_HPRE_DIV_4 (0x8+1) |
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#define RCC_CFGR_HPRE_DIV_8 (0x8+2) |
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#define RCC_CFGR_HPRE_DIV_16 (0x8+3) |
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#define RCC_CFGR_HPRE_DIV_64 (0x8+4) |
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#define RCC_CFGR_HPRE_DIV_128 (0x8+5) |
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#define RCC_CFGR_HPRE_DIV_256 (0x8+6) |
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#define RCC_CFGR_HPRE_DIV_512 (0x8+7) |
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/* SWS: System clock switch status */ |
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#define RCC_CFGR_SWS_SHIFT 2 |
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#define RCC_CFGR_SWS_HSI 0x0 |
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#define RCC_CFGR_SWS_HSE 0x1 |
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#define RCC_CFGR_SWS_PLL 0x2 |
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/* SW: System clock switch */ |
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#define RCC_CFGR_SW_SHIFT 0 |
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#define RCC_CFGR_SW_HSI 0x0 |
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#define RCC_CFGR_SW_HSE 0x1 |
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#define RCC_CFGR_SW_PLL 0x2 |
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/* --- RCC_CIR values ------------------------------------------------------ */ |
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/* Clock security system interrupt clear bit */ |
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#define RCC_CIR_CSSC (1 << 23) |
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/* OSC ready interrupt clear bits */ |
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#define RCC_CIR_PLLI2SRDYC (1 << 21) |
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#define RCC_CIR_PLLRDYC (1 << 20) |
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#define RCC_CIR_HSERDYC (1 << 19) |
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#define RCC_CIR_HSIRDYC (1 << 18) |
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#define RCC_CIR_LSERDYC (1 << 17) |
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#define RCC_CIR_LSIRDYC (1 << 16) |
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/* OSC ready interrupt enable bits */ |
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#define RCC_CIR_PLLI2SRDYIE (1 << 13) |
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#define RCC_CIR_PLLRDYIE (1 << 12) |
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#define RCC_CIR_HSERDYIE (1 << 11) |
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#define RCC_CIR_HSIRDYIE (1 << 10) |
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#define RCC_CIR_LSERDYIE (1 << 9) |
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#define RCC_CIR_LSIRDYIE (1 << 8) |
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/* Clock security system interrupt flag bit */ |
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#define RCC_CIR_CSSF (1 << 7) |
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/* OSC ready interrupt flag bits */ |
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#define RCC_CIR_PLLI2SRDYF (1 << 5) |
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#define RCC_CIR_PLLRDYF (1 << 4) |
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#define RCC_CIR_HSERDYF (1 << 3) |
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#define RCC_CIR_HSIRDYF (1 << 2) |
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#define RCC_CIR_LSERDYF (1 << 1) |
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#define RCC_CIR_LSIRDYF (1 << 0) |
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/* --- RCC_AHB1RSTR values ------------------------------------------------- */ |
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#define RCC_AHB1RSTR_OTGHSRST (1 << 29) |
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#define RCC_AHB1RSTR_ETHMACRST (1 << 25) |
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#define RCC_AHB1RSTR_DMA2RST (1 << 22) |
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#define RCC_AHB1RSTR_DMA1RST (1 << 21) |
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#define RCC_AHB1RSTR_CRCRST (1 << 12) |
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#define RCC_AHB1RSTR_GPIOIRST (1 << 8) |
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#define RCC_AHB1RSTR_GPIOHRST (1 << 7) |
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#define RCC_AHB1RSTR_GPIOGRST (1 << 6) |
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#define RCC_AHB1RSTR_GPIOFRST (1 << 5) |
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#define RCC_AHB1RSTR_GPIOERST (1 << 4) |
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#define RCC_AHB1RSTR_GPIODRST (1 << 3) |
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#define RCC_AHB1RSTR_GPIOCRST (1 << 2) |
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#define RCC_AHB1RSTR_GPIOBRST (1 << 1) |
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#define RCC_AHB1RSTR_GPIOARST (1 << 0) |
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/* --- RCC_AHB2RSTR values ------------------------------------------------- */ |
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#define RCC_AHB2RSTR_OTGFSRST (1 << 7) |
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#define RCC_AHB2RSTR_RNGRST (1 << 6) |
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#define RCC_AHB2RSTR_HASHRST (1 << 5) |
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#define RCC_AHB2RSTR_CRYPRST (1 << 4) |
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#define RCC_AHB2RSTR_DCMIRST (1 << 0) |
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/* --- RCC_AHB3RSTR values ------------------------------------------------- */ |
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#define RCC_AHB3RSTR_FSMCRST (1 << 0) |
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/* --- RCC_APB1RSTR values ------------------------------------------------- */ |
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#define RCC_APB1RSTR_DACRST (1 << 29) |
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#define RCC_APB1RSTR_PWRRST (1 << 28) |
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#define RCC_APB1RSTR_CAN2RST (1 << 26) |
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#define RCC_APB1RSTR_CAN1RST (1 << 25) |
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#define RCC_APB1RSTR_I2C3RST (1 << 23) |
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#define RCC_APB1RSTR_I2C2RST (1 << 22) |
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#define RCC_APB1RSTR_I2C1RST (1 << 21) |
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#define RCC_APB1RSTR_USART5RST (1 << 20) |
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#define RCC_APB1RSTR_USART4RST (1 << 19) |
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#define RCC_APB1RSTR_USART3RST (1 << 18) |
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#define RCC_APB1RSTR_USART2RST (1 << 17) |
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#define RCC_APB1RSTR_SPI3RST (1 << 15) |
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#define RCC_APB1RSTR_SPI2RST (1 << 14) |
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#define RCC_APB1RSTR_WWDGRST (1 << 11) |
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#define RCC_APB1RSTR_TIM14RST (1 << 8) |
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#define RCC_APB1RSTR_TIM13RST (1 << 7) |
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#define RCC_APB1RSTR_TIM12RST (1 << 6) |
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#define RCC_APB1RSTR_TIM7RST (1 << 5) |
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#define RCC_APB1RSTR_TIM6RST (1 << 4) |
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#define RCC_APB1RSTR_TIM5RST (1 << 3) |
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#define RCC_APB1RSTR_TIM4RST (1 << 2) |
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#define RCC_APB1RSTR_TIM3RST (1 << 1) |
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#define RCC_APB1RSTR_TIM2RST (1 << 0) |
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/* --- RCC_APB2RSTR values ------------------------------------------------- */ |
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#define RCC_APB2RSTR_TIM11RST (1 << 18) |
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#define RCC_APB2RSTR_TIM10RST (1 << 17) |
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#define RCC_APB2RSTR_TIM9RST (1 << 16) |
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#define RCC_APB2RSTR_SYSCFGRST (1 << 14) |
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#define RCC_APB2RSTR_SPI1RST (1 << 12) |
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#define RCC_APB2RSTR_SDIORST (1 << 11) |
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#define RCC_APB2RSTR_ADCRST (1 << 8) |
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#define RCC_APB2RSTR_USART6RST (1 << 5) |
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#define RCC_APB2RSTR_USART1RST (1 << 4) |
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#define RCC_APB2RSTR_TIM8RST (1 << 1) |
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#define RCC_APB2RSTR_TIM1RST (1 << 0) |
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/* --- RCC_AHB1ENR values ------------------------------------------------- */ |
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#define RCC_AHB1ENR_OTGHSULPIEN (1 << 30) |
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#define RCC_AHB1ENR_OTGHSEN (1 << 29) |
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#define RCC_AHB1ENR_ETHMACPTPEN (1 << 28) |
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#define RCC_AHB1ENR_ETHMACRXEN (1 << 27) |
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#define RCC_AHB1ENR_ETHMACTXEN (1 << 26) |
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#define RCC_AHB1ENR_ETHMACEN (1 << 25) |
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#define RCC_AHB1ENR_DMA2EN (1 << 22) |
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#define RCC_AHB1ENR_DMA1EN (1 << 21) |
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#define RCC_AHB1ENR_BKPSRAMEN (1 << 18) |
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#define RCC_AHB1ENR_CRCEN (1 << 12) |
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#define RCC_AHB1ENR_GPIOIEN (1 << 8) |
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#define RCC_AHB1ENR_GPIOHEN (1 << 7) |
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#define RCC_AHB1ENR_GPIOGEN (1 << 6) |
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#define RCC_AHB1ENR_GPIOFEN (1 << 5) |
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#define RCC_AHB1ENR_GPIOEEN (1 << 4) |
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#define RCC_AHB1ENR_GPIODEN (1 << 3) |
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#define RCC_AHB1ENR_GPIOCEN (1 << 2) |
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#define RCC_AHB1ENR_GPIOBEN (1 << 1) |
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#define RCC_AHB1ENR_GPIOAEN (1 << 0) |
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/* --- RCC_AHB2ENR values ------------------------------------------------- */ |
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#define RCC_AHB2ENR_OTGFSEN (1 << 7) |
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#define RCC_AHB2ENR_RNGEN (1 << 6) |
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#define RCC_AHB2ENR_HASHEN (1 << 5) |
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#define RCC_AHB2ENR_CRYPEN (1 << 4) |
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#define RCC_AHB2ENR_DCMIEN (1 << 0) |
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/* --- RCC_AHB3ENR values ------------------------------------------------- */ |
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#define RCC_AHB3ENR_FSMCEN (1 << 0) |
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/* --- RCC_APB1ENR values ------------------------------------------------- */ |
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#define RCC_APB1ENR_DACEN (1 << 29) |
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#define RCC_APB1ENR_PWREN (1 << 28) |
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#define RCC_APB1ENR_CAN2EN (1 << 26) |
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#define RCC_APB1ENR_CAN1EN (1 << 25) |
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#define RCC_APB1ENR_I2C3EN (1 << 23) |
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#define RCC_APB1ENR_I2C2EN (1 << 22) |
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#define RCC_APB1ENR_I2C1EN (1 << 21) |
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#define RCC_APB1ENR_USART5EN (1 << 20) |
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#define RCC_APB1ENR_USART4EN (1 << 19) |
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#define RCC_APB1ENR_USART3EN (1 << 18) |
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#define RCC_APB1ENR_USART2EN (1 << 17) |
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#define RCC_APB1ENR_SPI3EN (1 << 15) |
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#define RCC_APB1ENR_SPI2EN (1 << 14) |
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#define RCC_APB1ENR_WWDGEN (1 << 11) |
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#define RCC_APB1ENR_TIM14EN (1 << 8) |
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#define RCC_APB1ENR_TIM13EN (1 << 7) |
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#define RCC_APB1ENR_TIM12EN (1 << 6) |
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#define RCC_APB1ENR_TIM7EN (1 << 5) |
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#define RCC_APB1ENR_TIM6EN (1 << 4) |
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#define RCC_APB1ENR_TIM5EN (1 << 3) |
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#define RCC_APB1ENR_TIM4EN (1 << 2) |
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#define RCC_APB1ENR_TIM3EN (1 << 1) |
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#define RCC_APB1ENR_TIM2EN (1 << 0) |
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/* --- RCC_APB2ENR values ------------------------------------------------- */ |
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#define RCC_APB2ENR_TIM11EN (1 << 18) |
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#define RCC_APB2ENR_TIM10EN (1 << 17) |
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#define RCC_APB2ENR_TIM9EN (1 << 16) |
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#define RCC_APB2ENR_SYSCFGEN (1 << 14) |
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#define RCC_APB2ENR_SPI1EN (1 << 12) |
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#define RCC_APB2ENR_SDIOEN (1 << 11) |
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#define RCC_APB2ENR_ADC3EN (1 << 10) |
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#define RCC_APB2ENR_ADC2EN (1 << 9) |
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#define RCC_APB2ENR_ADC1EN (1 << 8) |
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#define RCC_APB2ENR_USART6EN (1 << 5) |
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#define RCC_APB2ENR_USART1EN (1 << 4) |
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#define RCC_APB2ENR_TIM8EN (1 << 1) |
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#define RCC_APB2ENR_TIM1EN (1 << 0) |
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/* --- RCC_AHB1LPENR values ------------------------------------------------- */ |
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#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30) |
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#define RCC_AHB1LPENR_OTGHSLPEN (1 << 29) |
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#define RCC_AHB1LPENR_ETHMACPTPLPEN (1 << 28) |
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#define RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27) |
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#define RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26) |
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#define RCC_AHB1LPENR_ETHMACLPEN (1 << 25) |
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#define RCC_AHB1LPENR_DMA2LPEN (1 << 22) |
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#define RCC_AHB1LPENR_DMA1LPEN (1 << 21) |
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#define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18) |
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#define RCC_AHB1LPENR_SRAM2LPEN (1 << 17) |
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#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) |
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#define RCC_AHB1LPENR_FLITFLPEN (1 << 15) |
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#define RCC_AHB1LPENR_CRCLPEN (1 << 12) |
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#define RCC_AHB1LPENR_GPIOILPEN (1 << 8) |
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#define RCC_AHB1LPENR_GPIOHLPEN (1 << 7) |
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#define RCC_AHB1LPENR_GPIOGLPEN (1 << 6) |
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#define RCC_AHB1LPENR_GPIOFLPEN (1 << 5) |
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#define RCC_AHB1LPENR_GPIOELPEN (1 << 4) |
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#define RCC_AHB1LPENR_GPIODLPEN (1 << 3) |
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#define RCC_AHB1LPENR_GPIOCLPEN (1 << 2) |
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#define RCC_AHB1LPENR_GPIOBLPEN (1 << 1) |
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#define RCC_AHB1LPENR_GPIOALPEN (1 << 0) |
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/* --- RCC_AHB2LPENR values ------------------------------------------------- */ |
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#define RCC_AHB2LPENR_OTGFSLPEN (1 << 7) |
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#define RCC_AHB2LPENR_RNGLPEN (1 << 6) |
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#define RCC_AHB2LPENR_HASHLPEN (1 << 5) |
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#define RCC_AHB2LPENR_CRYPLPEN (1 << 4) |
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#define RCC_AHB2LPENR_DCMILPEN (1 << 0) |
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/* --- RCC_AHB3LPENR values ------------------------------------------------- */ |
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#define RCC_AHB3LPENR_FSMCLPEN (1 << 0) |
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/* --- RCC_APB1LPENR values ------------------------------------------------- */ |
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#define RCC_APB1LPENR_DACLPEN (1 << 29) |
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#define RCC_APB1LPENR_PWRLPEN (1 << 28) |
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#define RCC_APB1LPENR_CAN2LPEN (1 << 26) |
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#define RCC_APB1LPENR_CAN1LPEN (1 << 25) |
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#define RCC_APB1LPENR_I2C3LPEN (1 << 23) |
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#define RCC_APB1LPENR_I2C2LPEN (1 << 22) |
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#define RCC_APB1LPENR_I2C1LPEN (1 << 21) |
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#define RCC_APB1LPENR_USART5LPEN (1 << 20) |
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#define RCC_APB1LPENR_USART4LPEN (1 << 19) |
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#define RCC_APB1LPENR_USART3LPEN (1 << 18) |
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#define RCC_APB1LPENR_USART2LPEN (1 << 17) |
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#define RCC_APB1LPENR_SPI3LPEN (1 << 15) |
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#define RCC_APB1LPENR_SPI2LPEN (1 << 14) |
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#define RCC_APB1LPENR_WWDGLPEN (1 << 11) |
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#define RCC_APB1LPENR_TIM14LPEN (1 << 8) |
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#define RCC_APB1LPENR_TIM13LPEN (1 << 7) |
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#define RCC_APB1LPENR_TIM12LPEN (1 << 6) |
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#define RCC_APB1LPENR_TIM7LPEN (1 << 5) |
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#define RCC_APB1LPENR_TIM6LPEN (1 << 4) |
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#define RCC_APB1LPENR_TIM5LPEN (1 << 3) |
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#define RCC_APB1LPENR_TIM4LPEN (1 << 2) |
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#define RCC_APB1LPENR_TIM3LPEN (1 << 1) |
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#define RCC_APB1LPENR_TIM2LPEN (1 << 0) |
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/* --- RCC_APB2LPENR values ------------------------------------------------- */ |
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#define RCC_APB2LPENR_TIM11LPEN (1 << 18) |
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#define RCC_APB2LPENR_TIM10LPEN (1 << 17) |
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#define RCC_APB2LPENR_TIM9LPEN (1 << 16) |
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#define RCC_APB2LPENR_SYSCFGLPEN (1 << 14) |
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#define RCC_APB2LPENR_SPI1LPEN (1 << 12) |
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#define RCC_APB2LPENR_SDIOLPEN (1 << 11) |
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#define RCC_APB2LPENR_ADC3LPEN (1 << 10) |
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#define RCC_APB2LPENR_ADC2LPEN (1 << 9) |
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#define RCC_APB2LPENR_ADC1LPEN (1 << 8) |
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#define RCC_APB2LPENR_USART6LPEN (1 << 5) |
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#define RCC_APB2LPENR_USART1LPEN (1 << 4) |
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#define RCC_APB2LPENR_TIM8LPEN (1 << 1) |
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#define RCC_APB2LPENR_TIM1LPEN (1 << 0) |
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/* --- RCC_BDCR values ----------------------------------------------------- */ |
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#define RCC_BDCR_BDRST (1 << 16) |
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#define RCC_BDCR_RTCEN (1 << 15) |
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/* RCC_BDCR[9:8]: RTCSEL */ |
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#define RCC_BDCR_LSEBYP (1 << 2) |
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#define RCC_BDCR_LSERDY (1 << 1) |
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#define RCC_BDCR_LSEON (1 << 0) |
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/* --- RCC_CSR values ------------------------------------------------------ */ |
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#define RCC_CSR_LPWRRSTF (1 << 31) |
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#define RCC_CSR_WWDGRSTF (1 << 30) |
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#define RCC_CSR_IWDGRSTF (1 << 29) |
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#define RCC_CSR_SFTRSTF (1 << 28) |
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#define RCC_CSR_PORRSTF (1 << 27) |
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#define RCC_CSR_PINRSTF (1 << 26) |
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#define RCC_CSR_BORRSTF (1 << 26) |
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#define RCC_CSR_RMVF (1 << 24) |
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#define RCC_CSR_LSIRDY (1 << 1) |
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#define RCC_CSR_LSION (1 << 0) |
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/* --- RCC_SSCGR values ---------------------------------------------------- */ |
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/* PLL spread spectrum clock generation documented in Datasheet. */ |
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#define RCC_SSCGR_SSCGEN (1 << 31) |
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#define RCC_SSCGR_SPREADSEL (1 << 30) |
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/* RCC_SSCGR[27:16]: INCSTEP */ |
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#define RCC_SSCGR_INCSTEP_SHIFT 16 |
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/* RCC_SSCGR[15:0]: MODPER */ |
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#define RCC_SSCGR_MODPER_SHIFT 15 |
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/* --- RCC_PLLI2SCFGR values ----------------------------------------------- */ |
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/* RCC_PLLI2SCFGR[30:28]: PLLI2SR */ |
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#define RCC_PLLI2SCFGR_PLLI2SR_SHIFT 28 |
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/* RCC_PLLI2SCFGR[14:6]: PLLI2SN */ |
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#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6 |
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#endif |
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Loading…
Reference in new issue