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Updated the documentation so that it appears in all families Also added it to the L1 area, but is untested. An addition to the memorymap allows commonality and a #ifdef added to the spi_common_all code to exclude the case of SPI3 for L1 and F0 as SPI3 doesn't exist in those. An rcc dispatch header was added to remove same code from the spi header.pull/72/head
Ken Sarkies
12 years ago
27 changed files with 790 additions and 498 deletions
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/** @addtogroup spi_defines */ |
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/*
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* This file is part of the libopencm3 project. |
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* |
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> |
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* |
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* This library is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU Lesser General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* This library is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public License |
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H */ |
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#ifndef LIBOPENCM3_SPI_COMMON_ALL_H |
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#define LIBOPENCM3_SPI_COMMON_ALL_H |
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#include <libopencm3/cm3/common.h> |
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/**@{*/ |
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/* Registers can be accessed as 16bit or 32bit values. */ |
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/* --- Convenience macros -------------------------------------------------- */ |
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/****************************************************************************/ |
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/** @defgroup spi_reg_base SPI Register base address
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@ingroup spi_defines |
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@{*/ |
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#define SPI1 SPI1_BASE |
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#define SPI2 SPI2_I2S_BASE |
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#define SPI3 SPI3_I2S_BASE |
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/**@}*/ |
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/* --- SPI registers ------------------------------------------------------- */ |
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/* Control register 1 (SPIx_CR1) */ |
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/* Note: Not used in I2S mode. */ |
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#define SPI_CR1(spi_base) MMIO32(spi_base + 0x00) |
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#define SPI1_CR1 SPI_CR1(SPI1_BASE) |
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#define SPI2_CR1 SPI_CR1(SPI2_I2S_BASE) |
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#define SPI3_CR1 SPI_CR1(SPI3_I2S_BASE) |
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/* Control register 2 (SPIx_CR2) */ |
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#define SPI_CR2(spi_base) MMIO32(spi_base + 0x04) |
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#define SPI1_CR2 SPI_CR2(SPI1_BASE) |
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#define SPI2_CR2 SPI_CR2(SPI2_I2S_BASE) |
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#define SPI3_CR2 SPI_CR2(SPI3_I2S_BASE) |
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/* Status register (SPIx_SR) */ |
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#define SPI_SR(spi_base) MMIO32(spi_base + 0x08) |
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#define SPI1_SR SPI_SR(SPI1_BASE) |
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#define SPI2_SR SPI_SR(SPI2_I2S_BASE) |
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#define SPI3_SR SPI_SR(SPI3_I2S_BASE) |
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/* Data register (SPIx_DR) */ |
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#define SPI_DR(spi_base) MMIO32(spi_base + 0x0c) |
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#define SPI1_DR SPI_DR(SPI1_BASE) |
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#define SPI2_DR SPI_DR(SPI2_I2S_BASE) |
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#define SPI3_DR SPI_DR(SPI3_I2S_BASE) |
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/* CRC polynomial register (SPIx_CRCPR) */ |
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/* Note: Not used in I2S mode. */ |
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#define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10) |
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#define SPI1_CRCPR SPI_CRCPR(SPI1_BASE) |
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#define SPI2_CRCPR SPI_CRCPR(SPI2_I2S_BASE) |
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#define SPI3_CRCPR SPI_CRCPR(SPI3_I2S_BASE) |
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/* RX CRC register (SPIx_RXCRCR) */ |
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/* Note: Not used in I2S mode. */ |
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#define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14) |
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#define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE) |
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#define SPI2_RXCRCR SPI_RXCRCR(SPI2_I2S_BASE) |
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#define SPI3_RXCRCR SPI_RXCRCR(SPI3_I2S_BASE) |
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/* TX CRC register (SPIx_RXCRCR) */ |
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/* Note: Not used in I2S mode. */ |
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#define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18) |
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#define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE) |
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#define SPI2_TXCRCR SPI_TXCRCR(SPI2_I2S_BASE) |
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#define SPI3_TXCRCR SPI_TXCRCR(SPI3_I2S_BASE) |
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/* I2S configuration register (SPIx_I2SCFGR) */ |
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#define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c) |
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#define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE) |
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#define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_I2S_BASE) |
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#define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_I2S_BASE) |
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/* I2S prescaler register (SPIx_I2SPR) */ |
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#define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20) |
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#define SPI1_I2SPR SPI_I2SPR(SPI1_BASE) |
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#define SPI2_I2SPR SPI_I2SPR(SPI2_I2S_BASE) |
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#define SPI3_I2SPR SPI_I2SPR(SPI3_I2S_BASE) |
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/* --- SPI_CR1 values ------------------------------------------------------ */ |
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/* Note: None of the CR1 bits are used in I2S mode. */ |
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/* BIDIMODE: Bidirectional data mode enable */ |
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#define SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15) |
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#define SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15) |
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#define SPI_CR1_BIDIMODE (1 << 15) |
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/* BIDIOE: Output enable in bidirectional mode */ |
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#define SPI_CR1_BIDIOE (1 << 14) |
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/* CRCEN: Hardware CRC calculation enable */ |
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#define SPI_CR1_CRCEN (1 << 13) |
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/* CRCNEXT: Transmit CRC next */ |
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#define SPI_CR1_CRCNEXT (1 << 12) |
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/* DFF: Data frame format */ |
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/****************************************************************************/ |
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/** @defgroup spi_dff SPI data frame format
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@ingroup spi_defines |
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@{*/ |
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#define SPI_CR1_DFF_8BIT (0 << 11) |
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#define SPI_CR1_DFF_16BIT (1 << 11) |
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/**@}*/ |
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#define SPI_CR1_DFF (1 << 11) |
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/* RXONLY: Receive only */ |
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#define SPI_CR1_RXONLY (1 << 10) |
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/* SSM: Software slave management */ |
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#define SPI_CR1_SSM (1 << 9) |
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/* SSI: Internal slave select */ |
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#define SPI_CR1_SSI (1 << 8) |
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/* LSBFIRST: Frame format */ |
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/****************************************************************************/ |
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/** @defgroup spi_lsbfirst SPI lsb/msb first
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@ingroup spi_defines |
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@{*/ |
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#define SPI_CR1_MSBFIRST (0 << 7) |
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#define SPI_CR1_LSBFIRST (1 << 7) |
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/**@}*/ |
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/* SPE: SPI enable */ |
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#define SPI_CR1_SPE (1 << 6) |
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/* BR[2:0]: Baud rate control */ |
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/****************************************************************************/ |
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/** @defgroup spi_baudrate SPI peripheral baud rates
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@ingroup spi_defines |
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@{*/ |
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3) |
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3) |
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3) |
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3) |
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3) |
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3) |
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3) |
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3) |
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/**@}*/ |
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/****************************************************************************/ |
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/** @defgroup spi_br_pre SPI peripheral baud rate prescale values
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@ingroup spi_defines |
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@{*/ |
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#define SPI_CR1_BR_FPCLK_DIV_2 0x0 |
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#define SPI_CR1_BR_FPCLK_DIV_4 0x1 |
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#define SPI_CR1_BR_FPCLK_DIV_8 0x2 |
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#define SPI_CR1_BR_FPCLK_DIV_16 0x3 |
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#define SPI_CR1_BR_FPCLK_DIV_32 0x4 |
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#define SPI_CR1_BR_FPCLK_DIV_64 0x5 |
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#define SPI_CR1_BR_FPCLK_DIV_128 0x6 |
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#define SPI_CR1_BR_FPCLK_DIV_256 0x7 |
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/**@}*/ |
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/* MSTR: Master selection */ |
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#define SPI_CR1_MSTR (1 << 2) |
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/* CPOL: Clock polarity */ |
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/****************************************************************************/ |
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/** @defgroup spi_cpol SPI clock polarity
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@ingroup spi_defines |
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@{*/ |
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#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1) |
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#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1) |
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/**@}*/ |
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#define SPI_CR1_CPOL (1 << 1) |
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/* CPHA: Clock phase */ |
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/****************************************************************************/ |
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/** @defgroup spi_cpha SPI clock phase
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@ingroup spi_defines |
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@{*/ |
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#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0) |
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#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0) |
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/**@}*/ |
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#define SPI_CR1_CPHA (1 << 0) |
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/* --- SPI_CR2 values ------------------------------------------------------ */ |
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/* Bits [15:8]: Reserved. Forced to 0 by hardware. */ |
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/* TXEIE: Tx buffer empty interrupt enable */ |
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#define SPI_CR2_TXEIE (1 << 7) |
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/* RXNEIE: Rx buffer not empty interrupt enable */ |
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#define SPI_CR2_RXNEIE (1 << 6) |
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/* ERRIE: Error interrupt enable */ |
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#define SPI_CR2_ERRIE (1 << 5) |
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/* Bits [4:3]: Reserved. Forced to 0 by hardware. */ |
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/* SSOE: SS output enable */ |
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/* Note: Not used in I2S mode. */ |
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#define SPI_CR2_SSOE (1 << 2) |
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/* TXDMAEN: Tx buffer DMA enable */ |
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#define SPI_CR2_TXDMAEN (1 << 1) |
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/* RXDMAEN: Rx buffer DMA enable */ |
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#define SPI_CR2_RXDMAEN (1 << 0) |
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/* --- SPI_SR values ------------------------------------------------------- */ |
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/* Bits [15:8]: Reserved. Forced to 0 by hardware. */ |
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/* BSY: Busy flag */ |
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#define SPI_SR_BSY (1 << 7) |
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/* OVR: Overrun flag */ |
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#define SPI_SR_OVR (1 << 6) |
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/* MODF: Mode fault */ |
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/* Note: Not used in I2S mode. */ |
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#define SPI_SR_MODF (1 << 5) |
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/* CRCERR: CRC error flag */ |
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/* Note: Not used in I2S mode. */ |
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#define SPI_SR_CRCERR (1 << 4) |
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/* UDR: Underrun flag */ |
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/* Note: Not used in SPI mode. */ |
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#define SPI_SR_UDR (1 << 3) |
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/* CHSIDE: Channel side */ |
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/* Note: Not used in SPI mode. No meaning in PCM mode. */ |
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#define SPI_SR_CHSIDE (1 << 2) |
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/* TXE: Transmit buffer empty */ |
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#define SPI_SR_TXE (1 << 1) |
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/* RXNE: Receive buffer not empty */ |
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#define SPI_SR_RXNE (1 << 0) |
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/* --- SPI_DR values ------------------------------------------------------- */ |
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/* SPI_DR[15:0]: Data Register. */ |
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/* --- SPI_CRCPR values ---------------------------------------------------- */ |
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/* Note: Not used in I2S mode. */ |
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/* SPI_CRCPR [15:0]: CRC Polynomial Register. */ |
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/* --- SPI_RXCRCR values --------------------------------------------------- */ |
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/* Note: Not used in I2S mode. */ |
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/* SPI_RXCRCR [15:0]: RX CRC Register. */ |
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/* --- SPI_TXCRCR values --------------------------------------------------- */ |
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/* Note: Not used in I2S mode. */ |
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/* SPI_TXCRCR [15:0]: TX CRC Register. */ |
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/* --- SPI_I2SCFGR values -------------------------------------------------- */ |
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/* Note: None of these bits are used in SPI mode. */ |
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/* Bits [15:12]: Reserved. Forced to 0 by hardware. */ |
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/* I2SMOD: I2S mode selection */ |
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#define SPI_I2SCFGR_I2SMOD (1 << 11) |
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/* I2SE: I2S enable */ |
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#define SPI_I2SCFGR_I2SE (1 << 10) |
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/* I2SCFG[9:8]: I2S configuration mode */ |
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#define SPI_I2SCFGR_I2SCFG_LSB 8 |
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#define SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0 |
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#define SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1 |
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#define SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2 |
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#define SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3 |
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/* PCMSYNC: PCM frame synchronization */ |
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#define SPI_I2SCFGR_PCMSYNC (1 << 7) |
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/* Bit 6: Reserved. Forced to 0 by hardware. */ |
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/* I2SSTD[5:4]: I2S standard selection */ |
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#define SPI_I2SCFGR_I2SSTD_LSB 4 |
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#define SPI_I2SCFGR_I2SSTD_I2S_PHILLIPS 0x0 |
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#define SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1 |
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#define SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2 |
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#define SPI_I2SCFGR_I2SSTD_PCM 0x3 |
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/* CKPOL: Steady state clock polarity */ |
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#define SPI_I2SCFGR_CKPOL (1 << 3) |
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/* DATLEN[2:1]: Data length to be transferred */ |
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#define SPI_I2SCFGR_DATLEN_LSB 1 |
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#define SPI_I2SCFGR_DATLEN_16BIT 0x0 |
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#define SPI_I2SCFGR_DATLEN_24BIT 0x1 |
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#define SPI_I2SCFGR_DATLEN_32BIT 0x2 |
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/* CHLEN: Channel length */ |
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#define SPI_I2SCFGR_CHLEN (1 << 0) |
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/* --- SPI_I2SPR values ---------------------------------------------------- */ |
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/* Note: None of these bits are used in SPI mode. */ |
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/* Bits [15:10]: Reserved. Forced to 0 by hardware. */ |
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/* MCKOE: Master clock output enable */ |
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#define SPI_I2SPR_MCKOE (1 << 9) |
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/* ODD: Odd factor for the prescaler */ |
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#define SPI_I2SPR_ODD (1 << 8) |
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/* I2SDIV[7:0]: I2S linear prescaler */ |
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/* 0 and 1 are forbidden values */ |
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/* --- Function prototypes ------------------------------------------------- */ |
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BEGIN_DECLS |
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void spi_reset(u32 spi_peripheral); |
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int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst); |
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void spi_enable(u32 spi); |
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void spi_disable(u32 spi); |
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void spi_write(u32 spi, u16 data); |
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void spi_send(u32 spi, u16 data); |
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u16 spi_read(u32 spi); |
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u16 spi_xfer(u32 spi, u16 data); |
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void spi_set_bidirectional_mode(u32 spi); |
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void spi_set_unidirectional_mode(u32 spi); |
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void spi_set_bidirectional_receive_only_mode(u32 spi); |
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void spi_set_bidirectional_transmit_only_mode(u32 spi); |
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void spi_enable_crc(u32 spi); |
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void spi_disable_crc(u32 spi); |
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void spi_set_next_tx_from_buffer(u32 spi); |
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void spi_set_next_tx_from_crc(u32 spi); |
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void spi_set_dff_8bit(u32 spi); |
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void spi_set_dff_16bit(u32 spi); |
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void spi_set_full_duplex_mode(u32 spi); |
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void spi_set_receive_only_mode(u32 spi); |
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void spi_disable_software_slave_management(u32 spi); |
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void spi_enable_software_slave_management(u32 spi); |
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void spi_set_nss_high(u32 spi); |
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void spi_set_nss_low(u32 spi); |
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void spi_send_lsb_first(u32 spi); |
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void spi_send_msb_first(u32 spi); |
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void spi_set_baudrate_prescaler(u32 spi, u8 baudrate); |
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void spi_set_master_mode(u32 spi); |
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void spi_set_slave_mode(u32 spi); |
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void spi_set_clock_polarity_1(u32 spi); |
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void spi_set_clock_polarity_0(u32 spi); |
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void spi_set_clock_phase_1(u32 spi); |
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void spi_set_clock_phase_0(u32 spi); |
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void spi_enable_tx_buffer_empty_interrupt(u32 spi); |
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void spi_disable_tx_buffer_empty_interrupt(u32 spi); |
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void spi_enable_rx_buffer_not_empty_interrupt(u32 spi); |
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void spi_disable_rx_buffer_not_empty_interrupt(u32 spi); |
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void spi_enable_error_interrupt(u32 spi); |
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void spi_disable_error_interrupt(u32 spi); |
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void spi_enable_ss_output(u32 spi); |
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void spi_disable_ss_output(u32 spi); |
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void spi_enable_tx_dma(u32 spi); |
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void spi_disable_tx_dma(u32 spi); |
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void spi_enable_rx_dma(u32 spi); |
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void spi_disable_rx_dma(u32 spi); |
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END_DECLS |
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/**@}*/ |
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#endif |
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@ -0,0 +1,50 @@ |
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/** @addtogroup spi_defines */ |
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/*
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* This file is part of the libopencm3 project. |
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* |
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* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com> |
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* |
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* This library is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU Lesser General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* This library is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public License |
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H */ |
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#ifndef LIBOPENCM3_SPI_COMMON_F24_H |
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#define LIBOPENCM3_SPI_COMMON_F24_H |
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/**@{*/ |
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#include <libopencm3/stm32/common/spi_common_all.h> |
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/*
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* This file extends the common STM32 version with definitions only |
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* applicable to the STM32F2/4 series of devices. |
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*/ |
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/* --- SPI_CR2 values ------------------------------------------------------ */ |
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/* FRF: Frame format */ |
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/* Note: Not used in I2S mode. */ |
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#define SPI_CR2_FRF (1 << 4) |
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#define SPI_CR2_FRF_MOTOROLA_MODE (0 << 4) |
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#define SPI_CR2_FRF_TI_MODE (1 << 4) |
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/* --- SPI_SR values ------------------------------------------------------- */ |
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/* TIFRFE: TI frame format error */ |
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#define SPI_SR_TIFRFE (1 << 8) |
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#endif |
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/**@}*/ |
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@ -0,0 +1,40 @@ |
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/** @defgroup spi_defines SPI Defines
|
|||
|
|||
@brief <b>Defined Constants and Types for the STM32F1xx SPI</b> |
|||
|
|||
@ingroup STM32F1xx_defines |
|||
|
|||
@version 1.0.0 |
|||
|
|||
@author @htmlonly © @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net> |
|||
|
|||
@date 5 December 2012 |
|||
|
|||
LGPL License Terms @ref lgpl_license |
|||
*/ |
|||
|
|||
/*
|
|||
* This file is part of the libopencm3 project. |
|||
* |
|||
* This library is free software: you can redistribute it and/or modify |
|||
* it under the terms of the GNU Lesser General Public License as published by |
|||
* the Free Software Foundation, either version 3 of the License, or |
|||
* (at your option) any later version. |
|||
* |
|||
* This library is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU Lesser General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU Lesser General Public License |
|||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|||
*/ |
|||
|
|||
#ifndef LIBOPENCM3_SPI_H |
|||
#define LIBOPENCM3_SPI_H |
|||
|
|||
#include <libopencm3/stm32/f1/memorymap.h> |
|||
#include <libopencm3/stm32/common/spi_common_all.h> |
|||
|
|||
#endif |
|||
|
|||
@ -0,0 +1,40 @@ |
|||
/** @defgroup spi_defines SPI Defines
|
|||
|
|||
@brief <b>Defined Constants and Types for the STM32L1xx SPI</b> |
|||
|
|||
@ingroup STM32L1xx_defines |
|||
|
|||
@version 1.0.0 |
|||
|
|||
@author @htmlonly © @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net> |
|||
|
|||
@date 5 December 2012 |
|||
|
|||
LGPL License Terms @ref lgpl_license |
|||
*/ |
|||
|
|||
/*
|
|||
* This file is part of the libopencm3 project. |
|||
* |
|||
* This library is free software: you can redistribute it and/or modify |
|||
* it under the terms of the GNU Lesser General Public License as published by |
|||
* the Free Software Foundation, either version 3 of the License, or |
|||
* (at your option) any later version. |
|||
* |
|||
* This library is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU Lesser General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU Lesser General Public License |
|||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|||
*/ |
|||
|
|||
#ifndef LIBOPENCM3_SPI_H |
|||
#define LIBOPENCM3_SPI_H |
|||
|
|||
#include <libopencm3/stm32/l1/memorymap.h> |
|||
#include <libopencm3/stm32/common/spi_common_all.h> |
|||
|
|||
#endif |
|||
|
|||
@ -0,0 +1,31 @@ |
|||
/* This provides unification of code over STM32F subfamilies */ |
|||
|
|||
/*
|
|||
* This file is part of the libopencm3 project. |
|||
* |
|||
* This library is free software: you can redistribute it and/or modify |
|||
* it under the terms of the GNU Lesser General Public License as published by |
|||
* the Free Software Foundation, either version 3 of the License, or |
|||
* (at your option) any later version. |
|||
* |
|||
* This library is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU Lesser General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU Lesser General Public License |
|||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|||
*/ |
|||
|
|||
#if defined(STM32F1) |
|||
# include <libopencm3/stm32/f1/rcc.h> |
|||
#elif defined(STM32F2) |
|||
# include <libopencm3/stm32/f2/rcc.h> |
|||
#elif defined(STM32F4) |
|||
# include <libopencm3/stm32/f4/rcc.h> |
|||
#elif defined(STM32L1) |
|||
# include <libopencm3/stm32/l1/rcc.h> |
|||
#else |
|||
# error "stm32 family not defined." |
|||
#endif |
|||
|
|||
@ -0,0 +1,28 @@ |
|||
/** @defgroup spi_file SPI
|
|||
|
|||
@ingroup STM32F1xx |
|||
|
|||
@brief <b>libopencm3 STM32F1xx SPI</b> |
|||
|
|||
*/ |
|||
|
|||
/*
|
|||
* This file is part of the libopencm3 project. |
|||
* |
|||
* This library is free software: you can redistribute it and/or modify |
|||
* it under the terms of the GNU Lesser General Public License as published by |
|||
* the Free Software Foundation, either version 3 of the License, or |
|||
* (at your option) any later version. |
|||
* |
|||
* This library is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU Lesser General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU Lesser General Public License |
|||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|||
*/ |
|||
|
|||
#include <libopencm3/stm32/spi.h> |
|||
#include <libopencm3/stm32/common/spi_common_all.h> |
|||
|
|||
@ -0,0 +1,28 @@ |
|||
/** @defgroup spi_file SPI
|
|||
|
|||
@ingroup STM32F2xx |
|||
|
|||
@brief <b>libopencm3 STM32F2xx SPI</b> |
|||
|
|||
*/ |
|||
|
|||
/*
|
|||
* This file is part of the libopencm3 project. |
|||
* |
|||
* This library is free software: you can redistribute it and/or modify |
|||
* it under the terms of the GNU Lesser General Public License as published by |
|||
* the Free Software Foundation, either version 3 of the License, or |
|||
* (at your option) any later version. |
|||
* |
|||
* This library is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU Lesser General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU Lesser General Public License |
|||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|||
*/ |
|||
|
|||
#include <libopencm3/stm32/spi.h> |
|||
#include <libopencm3/stm32/common/spi_common_f24.h> |
|||
|
|||
@ -0,0 +1,28 @@ |
|||
/** @defgroup spi_file SPI
|
|||
|
|||
@ingroup STM32F4xx |
|||
|
|||
@brief <b>libopencm3 STM32F4xx SPI</b> |
|||
|
|||
*/ |
|||
|
|||
/*
|
|||
* This file is part of the libopencm3 project. |
|||
* |
|||
* This library is free software: you can redistribute it and/or modify |
|||
* it under the terms of the GNU Lesser General Public License as published by |
|||
* the Free Software Foundation, either version 3 of the License, or |
|||
* (at your option) any later version. |
|||
* |
|||
* This library is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU Lesser General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU Lesser General Public License |
|||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|||
*/ |
|||
|
|||
#include <libopencm3/stm32/spi.h> |
|||
#include <libopencm3/stm32/common/spi_common_f24.h> |
|||
|
|||
@ -0,0 +1,28 @@ |
|||
/** @defgroup spi_file SPI
|
|||
|
|||
@ingroup STM32L1xx |
|||
|
|||
@brief <b>libopencm3 STM32L1xx SPI</b> |
|||
|
|||
*/ |
|||
|
|||
/*
|
|||
* This file is part of the libopencm3 project. |
|||
* |
|||
* This library is free software: you can redistribute it and/or modify |
|||
* it under the terms of the GNU Lesser General Public License as published by |
|||
* the Free Software Foundation, either version 3 of the License, or |
|||
* (at your option) any later version. |
|||
* |
|||
* This library is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU Lesser General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU Lesser General Public License |
|||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|||
*/ |
|||
|
|||
#include <libopencm3/stm32/spi.h> |
|||
#include <libopencm3/stm32/common/spi_common_all.h> |
|||
|
|||
Loading…
Reference in new issue