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Add basic functionality needed to setup the UART and send/recieve data. Interrupts, DMA, and more advanced features are not implemented in this patch. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>pull/112/merge
Alexandru Gagniuc
12 years ago
committed by
Piotr Esden-Tempski
Piotr Esden-Tempski
3 changed files with 469 additions and 1 deletions
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/*
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* This file is part of the libopencm3 project. |
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* |
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* Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com> |
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* |
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* This library is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU Lesser General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* This library is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public License |
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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/**
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* @defgroup uart_file UART |
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* |
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* @ingroup LM4Fxx |
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* |
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* @author @htmlonly © @endhtmlonly 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com> |
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* |
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* \brief <b>libopencm3 LM4F Universal Asynchronous Receiver Transmitter</b> |
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* |
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* The LM4F UART API provides functionality for accessing the UART hardware of |
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* the LM4F. |
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* |
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* Please see the individual UART modules for more details. To use the UART, the |
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* uart.h header needs to be included: |
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* @code{.c} |
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* #include <libopencm3/lm4f/uart.h> |
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* @endcode |
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* |
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* @{ |
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*/ |
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#include <libopencm3/lm4f/uart.h> |
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#include <libopencm3/lm4f/systemcontrol.h> |
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#include <libopencm3/lm4f/rcc.h> |
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/** @defgroup uart_config UART configuration
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* @ingroup uart_file |
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* |
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* \brief <b>Enabling and configuring the UART</b> |
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* |
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* Enabling the UART is a two step process. The GPIO on which the UART resides |
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* must be enabled, and the UART pins must be configured as alternate function, |
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* digital pins. Pins must also be muxed to the appropriate alternate function. |
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* This is done with the GPIO API. |
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* |
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* The second step involves enabling and the UART itself. The UART should be |
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* disabled while it is being configured. |
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* -# The UART clock must be enabled with @ref periph_clock_enable(). |
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* -# The UART must be disabled with @ref uart_disable(). |
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* -# The UART clock source should be chosen before setting the baudrate. |
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* -# Baudrate, data bits, stop bit length, and parity can be configured. |
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* -# If needed, enable CTS or RTS lines via the @ref uart_set_flow_control(). |
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* -# The UART can now be enabled with @ref uart_enable(). |
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* |
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* For example, to enable UART1 at 115200 8n1 with hardware flow control: |
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* @code{.c} |
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* // Enable the UART clock
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* periph_clock_enable(RCC_UART1); |
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* // We need a brief delay before we can access UART config registers
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* __asm__("nop"); __asm__("nop"); __asm__("nop"); |
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* // Disable the UART while we mess with its settings
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* uart_disable(UART1); |
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* // Configure the UART clock source as precision internal oscillator
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* uart_clock_from_piosc(); |
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* // Set communication parameters
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* uart_set_baudrate(UART1, 115200); |
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* uart_set_databits(UART1, 8); |
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* uart_set_parity(UART1, UART_PARITY_NONE); |
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* uart_set_stopbits(UART1, 1); |
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* // Enable RTC and CTS lines
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* uart_set_flow_control(UART1, UART_FLOWCTL_HARD_RTS_CTS); |
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* // Now that we're done messing with the settings, enable the UART
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* uart_enable(UART1); |
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* @endcode |
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*/ |
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/**@{*/ |
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/**
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* \brief Enable the UART |
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* |
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* Enable the UART. The Rx and Tx lines are also enabled. |
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* |
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* @param[in] uart UART block register address base @ref uart_reg_base |
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*/ |
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void uart_enable(u32 uart) |
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{ |
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UART_CTL(uart) |= (UART_CTL_UARTEN | UART_CTL_RXE | UART_CTL_TXE); |
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} |
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/**
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* \brief Disable the UART |
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* |
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* @param[in] uart UART block register address base @ref uart_reg_base |
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*/ |
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void uart_disable(u32 uart) |
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{ |
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UART_CTL(uart) &= ~UART_CTL_UARTEN; |
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} |
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/**
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* \brief Set UART baudrate |
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* |
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* @param[in] uart UART block register address base @ref uart_reg_base |
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* @param[in] baud Baud rate in bits per second (bps).* |
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*/ |
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void uart_set_baudrate(u32 uart, u32 baud) |
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{ |
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u32 clock; |
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/* Are we running off the internal clock or system clock? */ |
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if (UART_CC(uart) == UART_CC_CS_PIOSC) |
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clock = 16000000; |
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else |
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clock = rcc_get_system_clock_frequency(); |
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/* Find the baudrate divisor */ |
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u32 div = (((clock * 8) / baud) + 1) / 2; |
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/* Set the baudrate divisors */ |
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UART_IBRD(uart) = div / 64; |
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UART_FBRD(uart) = div % 64; |
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} |
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/**
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* \brief Set UART databits |
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* |
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* @param[in] uart UART block register address base @ref uart_reg_base |
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* @param[in] databits number of data bits per transmission. |
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*/ |
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void uart_set_databits(u32 uart, u8 databits) |
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{ |
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u32 reg32, bits32; |
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/* This has the same effect as using UART_LCRH_WLEN_5/6/7/8 directly */ |
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bits32 = (databits - 5) << 5; |
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/* TODO: What about 9 data bits? */ |
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reg32 = UART_LCRH(uart); |
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reg32 &= ~UART_LCRH_WLEN_MASK; |
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reg32 |= bits32; |
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UART_LCRH(uart) = reg32; |
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} |
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/**
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* \brief Set UART stopbits |
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* |
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* @param[in] uart UART block register address base @ref uart_reg_base |
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* @param[in] bits the requested number of stopbits, either 1 or 2. |
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*/ |
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void uart_set_stopbits(u32 uart, u8 stopbits) |
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{ |
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if (stopbits == 2) |
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UART_LCRH(uart) |= UART_LCRH_STP2; |
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else |
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UART_LCRH(uart) &= ~UART_LCRH_STP2; |
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} |
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/**
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* \brief Set UART parity |
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* |
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* @param[in] uart UART block register address base @ref uart_reg_base |
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* @param[in] bits the requested parity scheme. |
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*/ |
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void uart_set_parity(u32 uart, enum uart_parity parity) |
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{ |
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u32 reg32; |
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reg32 = UART_LCRH(uart); |
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reg32 |= UART_LCRH_PEN; |
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reg32 &= ~(UART_LCRH_SPS | UART_LCRH_EPS); |
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switch (parity) |
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{ |
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case UART_PARITY_NONE: |
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/* Once we disable parity the other bits are meaningless */ |
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UART_LCRH(uart) &= ~UART_LCRH_PEN; |
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return; |
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case UART_PARITY_ODD: |
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break; |
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case UART_PARITY_EVEN: |
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reg32 |= UART_LCRH_EPS; |
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break; |
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case UART_PARITY_STICK_0: |
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reg32 |= (UART_LCRH_SPS | UART_LCRH_EPS); |
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break; |
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case UART_PARITY_STICK_1: |
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reg32 |= UART_LCRH_SPS; |
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break; |
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} |
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UART_LCRH(uart) = reg32; |
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} |
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/**
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* \brief Set the flow control scheme |
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* |
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* Set the flow control scheme by enabling or disabling RTS and CTS lines. This |
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* will only have effect if the given UART supports the RTS and CTS lines. |
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* |
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* @param[in] uart UART block register address base @ref uart_reg_base |
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* @param[in] flow The flow control scheme to use (none, RTS, CTS or both) \n |
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* UART_FLOWCTL_RTS -- enable the RTS line \n |
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* UART_FLOWCTL_CTS -- enable the CTS line \n |
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* UART_FLOWCTL_RTS_CTS -- enable both RTS and CTS lines |
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*/ |
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void uart_set_flow_control(u32 uart, enum uart_flowctl flow) |
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{ |
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u32 reg32 = UART_CTL(uart); |
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reg32 &= ~(UART_CTL_RTSEN | UART_CTL_CTSEN); |
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if (flow == UART_FLOWCTL_RTS) |
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reg32 |= UART_CTL_RTSEN; |
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else if (flow == UART_FLOWCTL_CTS) |
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reg32 |= UART_CTL_CTSEN; |
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else if (flow == UART_FLOWCTL_RTS_CTS) |
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reg32 |= (UART_CTL_RTSEN | UART_CTL_CTSEN); |
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UART_CTL(uart) = reg32; |
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} |
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/**
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* \brief Clock the UART module from the internal oscillator |
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* |
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* @param[in] uart UART block register address base @ref uart_reg_base |
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*/ |
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void uart_clock_from_piosc(u32 uart) |
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{ |
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UART_CC(uart) = UART_CC_CS_PIOSC; |
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} |
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/**
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* \brief Clock the UART module from the system clock |
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* |
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* @param[in] uart UART block register address base @ref uart_reg_base |
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*/ |
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void uart_clock_from_sysclk(u32 uart) |
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{ |
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UART_CC(uart) = UART_CC_CS_SYSCLK; |
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} |
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/**@}*/ |
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/** @defgroup uart_send_recv UART transmission and reception
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* @ingroup uart_file |
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* |
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* \brief <b>Sending and receiving data through the UART</b> |
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* |
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* Primitives for sending and recieving data are provided, @ref uart_send() and |
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* @ref uart_recv(). These primitives do not check if data can be transmitted |
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* or wait for data. If waiting until data is available or can be transmitted is |
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* desired, blocking primitives are also available, @ref uart_send_blocking() |
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* and @ref uart_recv_blocking(). |
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* |
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* These primitives only handle one byte at at time, and thus may be unsuited |
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* for some applications. You may also consider using @ref uart_dma. |
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*/ |
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/**@{*/ |
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/**
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* \brief UART Send a Data Word. |
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* |
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* @param[in] uart UART block register address base @ref uart_reg_base |
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* @param[in] data data to send. |
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*/ |
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void uart_send(u32 uart, u16 data) |
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{ |
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data &= 0xFF; |
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UART_DR(uart) = data; |
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} |
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/**
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* \brief UART Read a Received Data Word. |
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* |
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* @param[in] uart UART block register address base @ref uart_reg_base |
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* @return data from the Rx FIFO. |
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*/ |
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u16 uart_recv(u32 uart) |
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{ |
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return UART_DR(uart) & UART_DR_DATA_MASK; |
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} |
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/**
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* \brief UART Wait for Transmit Data Buffer Not Full |
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* |
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* Blocks until the transmit data FIFO is not empty and can accept the next data |
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* word. |
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* \n |
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* Even if the FIFO is not empty, this function will return as long as there is |
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* room for at least one more word. |
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* |
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* @param[in] uart UART block register address base @ref uart_reg_base |
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*/ |
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void uart_wait_send_ready(u32 uart) |
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{ |
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/* Wait until the Tx FIFO is no longer full */ |
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while(UART_FR(uart) & UART_FR_TXFF); |
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} |
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/**
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* \brief UART Wait for Received Data Available |
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* |
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* Blocks until the receive data FIFO holds a at least valid received data word. |
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* |
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* @param[in] uart UART block register address base @ref uart_reg_base |
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*/ |
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void uart_wait_recv_ready(u32 uart) |
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{ |
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/* Wait until the Tx FIFO is no longer empty */ |
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while(UART_FR(uart) & UART_FR_RXFE); |
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} |
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/**
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* \brief UART Send Data Word with Blocking |
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* |
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* Blocks until the transmit data FIFO can accept the next data word for |
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* transmission. |
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* |
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* @param[in] uart UART block register address base @ref uart_reg_base |
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*/ |
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void uart_send_blocking(u32 uart, u16 data) |
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{ |
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uart_wait_send_ready(uart); |
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uart_send(uart, data); |
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} |
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/**
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* \brief UART Read a Received Data Word with Blocking. |
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* |
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* Wait until a data word has been received then return the word. |
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* |
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* @param[in] uart UART block register address base @ref uart_reg_base |
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* @return data from the Rx FIFO. |
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*/ |
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u16 uart_recv_blocking(u32 uart) |
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{ |
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uart_wait_recv_ready(uart); |
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return uart_recv(uart); |
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} |
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/**@}*/ |
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/** @defgroup uart_irq UART Interrupt control
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* @ingroup uart_file |
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* |
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* \brief <b>Configuring interrupts from the UART</b> |
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* |
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*/ |
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/**@{*/ |
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void uart_enable_rx_interrupt(u32 uart) |
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{ |
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/* TODO: this is just a stub. */ |
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} |
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void uart_disable_rx_interrupt(u32 uart) |
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{ |
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/* TODO: this is just a stub. */ |
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} |
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void uart_enable_tx_interrupt(u32 uart) |
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{ |
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/* TODO: this is just a stub. */ |
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} |
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void uart_disable_tx_interrupt(u32 uart) |
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{ |
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/* TODO: this is just a stub. */ |
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} |
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/**@}*/ |
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/** @defgroup uart_dma UART DMA control
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* @ingroup uart_file |
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* |
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* \brief <b>Enabling Direct Memory Access transfers for the UART</b> |
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* |
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*/ |
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/**@{*/ |
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void uart_enable_rx_dma(u32 uart) |
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{ |
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/* TODO: this is just a stub. */ |
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} |
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void uart_disable_rx_dma(u32 uart) |
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{ |
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/* TODO: this is just a stub. */ |
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} |
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void uart_enable_tx_dma(u32 uart) |
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{ |
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/* TODO: this is just a stub. */ |
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} |
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void uart_disable_tx_dma(u32 uart) |
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{ |
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/* TODO: this is just a stub. */ |
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} |
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/**@}*/ |
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/*
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bool uart_get_flag(u32 uart, u32 flag); |
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bool uart_get_interrupt_source(u32 uart, u32 flag); |
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*/ |
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/**
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* @} |
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*/ |
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