stm32g0: use proper register for gpio peripheral clock sleep enable.

Reviewed-by: Karl Palsson <karlp@tweak.net.au>

include/libopencm3/stm32/g0/rcc.h

@@ -678,12 +678,12 @@ enum rcc_periph_clken {
 	RCC_TIM1 = _REG_BIT(RCC_APBENR2_OFFSET, 11),
 	RCC_SYSCFG = _REG_BIT(RCC_APBENR2_OFFSET, 0),
 
-	SCC_GPIOF = _REG_BIT(RCC_IOPENR_OFFSET, 5),
-	SCC_GPIOE = _REG_BIT(RCC_IOPENR_OFFSET, 4),
-	SCC_GPIOD = _REG_BIT(RCC_IOPENR_OFFSET, 3),
-	SCC_GPIOC = _REG_BIT(RCC_IOPENR_OFFSET, 2),
-	SCC_GPIOB = _REG_BIT(RCC_IOPENR_OFFSET, 1),
-	SCC_GPIOA = _REG_BIT(RCC_IOPENR_OFFSET, 0),
+	SCC_GPIOF = _REG_BIT(RCC_IOPSMENR_OFFSET, 5),
+	SCC_GPIOE = _REG_BIT(RCC_IOPSMENR_OFFSET, 4),
+	SCC_GPIOD = _REG_BIT(RCC_IOPSMENR_OFFSET, 3),
+	SCC_GPIOC = _REG_BIT(RCC_IOPSMENR_OFFSET, 2),
+	SCC_GPIOB = _REG_BIT(RCC_IOPSMENR_OFFSET, 1),
+	SCC_GPIOA = _REG_BIT(RCC_IOPSMENR_OFFSET, 0),
 
 	SCC_RNG = _REG_BIT(RCC_AHBSMENR_OFFSET, 18),
 	SCC_AES = _REG_BIT(RCC_AHBSMENR_OFFSET, 16),