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libopencm3
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Fix compile by using the correct variable name.

pull/2/head
Uwe Hermann 16 years ago
parent
ab8cec181c
commit
944456fde1
1 changed files with 7 additions and 7 deletions
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  1. 14
      include/libopenstm32/usart.h

14
include/libopenstm32/usart.h
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@ -25,7 +25,7 @@
/* --- USART registers ----------------------------------------------------- */ /* --- USART registers ----------------------------------------------------- */
/* Status register (USARTx_SR) */ /* Status register (USARTx_SR) */
#define USART_SR(usart) MMIO32(usart_base + 0x00) #define USART_SR(usart_base) MMIO32(usart_base + 0x00)
#define USART1_SR USART_SR(USART1_BASE) #define USART1_SR USART_SR(USART1_BASE)
#define USART2_SR USART_SR(USART2_BASE) #define USART2_SR USART_SR(USART2_BASE)
#define USART3_SR USART_SR(USART3_BASE) #define USART3_SR USART_SR(USART3_BASE)
@ -33,7 +33,7 @@
#define UART5_SR USART_SR(UART5_BASE) #define UART5_SR USART_SR(UART5_BASE)
/* Data register (USARTx_DR) */ /* Data register (USARTx_DR) */
#define USART_DR(usart) MMIO32(usart_base + 0x04) #define USART_DR(usart_base) MMIO32(usart_base + 0x04)
#define USART1_DR USART_DR(USART1_BASE) #define USART1_DR USART_DR(USART1_BASE)
#define USART2_DR USART_DR(USART2_BASE) #define USART2_DR USART_DR(USART2_BASE)
#define USART3_DR USART_DR(USART3_BASE) #define USART3_DR USART_DR(USART3_BASE)
@ -41,7 +41,7 @@
#define UART5_DR USART_DR(UART5_BASE) #define UART5_DR USART_DR(UART5_BASE)
/* Baud rate register (USARTx_BRR) */ /* Baud rate register (USARTx_BRR) */
#define USART_BRR(usart) MMIO32(usart_base + 0x08) #define USART_BRR(usart_base) MMIO32(usart_base + 0x08)
#define USART1_BRR USART_BRR(USART1_BASE) #define USART1_BRR USART_BRR(USART1_BASE)
#define USART2_BRR USART_BRR(USART2_BASE) #define USART2_BRR USART_BRR(USART2_BASE)
#define USART3_BRR USART_BRR(USART3_BASE) #define USART3_BRR USART_BRR(USART3_BASE)
@ -49,7 +49,7 @@
#define UART5_BRR USART_BRR(UART5_BASE) #define UART5_BRR USART_BRR(UART5_BASE)
/* Control register 1 (USARTx_CR1) */ /* Control register 1 (USARTx_CR1) */
#define USART_CR1(usart) MMIO32(usart_base + 0x0c) #define USART_CR1(usart_base) MMIO32(usart_base + 0x0c)
#define USART1_CR1 USART_CR1(USART1_BASE) #define USART1_CR1 USART_CR1(USART1_BASE)
#define USART2_CR1 USART_CR1(USART2_BASE) #define USART2_CR1 USART_CR1(USART2_BASE)
#define USART3_CR1 USART_CR1(USART3_BASE) #define USART3_CR1 USART_CR1(USART3_BASE)
@ -57,7 +57,7 @@
#define UART5_CR1 USART_CR1(UART5_BASE) #define UART5_CR1 USART_CR1(UART5_BASE)
/* Control register 2 (USARTx_CR2) */ /* Control register 2 (USARTx_CR2) */
#define USART_CR2(usart) MMIO32(usart_base + 0x10) #define USART_CR2(usart_base) MMIO32(usart_base + 0x10)
#define USART1_CR2 USART_CR2(USART1_BASE) #define USART1_CR2 USART_CR2(USART1_BASE)
#define USART2_CR2 USART_CR2(USART2_BASE) #define USART2_CR2 USART_CR2(USART2_BASE)
#define USART3_CR2 USART_CR2(USART3_BASE) #define USART3_CR2 USART_CR2(USART3_BASE)
@ -65,7 +65,7 @@
#define UART5_CR2 USART_CR2(UART5_BASE) #define UART5_CR2 USART_CR2(UART5_BASE)
/* Control register 3 (USARTx_CR3) */ /* Control register 3 (USARTx_CR3) */
#define USART_CR3(usart) MMIO32(usart_base + 0x14) #define USART_CR3(usart_base) MMIO32(usart_base + 0x14)
#define USART1_CR3 USART_CR3(USART1_BASE) #define USART1_CR3 USART_CR3(USART1_BASE)
#define USART2_CR3 USART_CR3(USART2_BASE) #define USART2_CR3 USART_CR3(USART2_BASE)
#define USART3_CR3 USART_CR3(USART3_BASE) #define USART3_CR3 USART_CR3(USART3_BASE)
@ -73,7 +73,7 @@
#define UART5_CR3 USART_CR3(UART5_BASE) #define UART5_CR3 USART_CR3(UART5_BASE)
/* Guard time and prescaler register (USARTx_GTPR) */ /* Guard time and prescaler register (USARTx_GTPR) */
#define USART_GTPR(usart) MMIO32(usart_base + 0x18) #define USART_GTPR(usart_base) MMIO32(usart_base + 0x18)
#define USART1_GTPR USART_GTPR(USART1_BASE) #define USART1_GTPR USART_GTPR(USART1_BASE)
#define USART2_GTPR USART_GTPR(USART2_BASE) #define USART2_GTPR USART_GTPR(USART2_BASE)
#define USART3_GTPR USART_GTPR(USART3_BASE) #define USART3_GTPR USART_GTPR(USART3_BASE)

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