Fergus Noble
13 years ago
committed by
Stephen Caudle
Stephen Caudle
1 changed files with 274 additions and 0 deletions
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/*
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* This file is part of the libopencm3 project. |
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* |
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* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com> |
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* |
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* This program is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#ifndef LIBOPENCM3_GPIO_H |
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#define LIBOPENCM3_GPIO_H |
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#include <libopencm3/stm32/memorymap.h> |
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#include <libopencm3/cm3/common.h> |
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/* --- Convenience macros -------------------------------------------------- */ |
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/* GPIO port base addresses (for convenience) */ |
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#define GPIOA GPIO_PORT_A_BASE |
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#define GPIOB GPIO_PORT_B_BASE |
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#define GPIOC GPIO_PORT_C_BASE |
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#define GPIOD GPIO_PORT_D_BASE |
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#define GPIOE GPIO_PORT_E_BASE |
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#define GPIOF GPIO_PORT_F_BASE |
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#define GPIOG GPIO_PORT_G_BASE |
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#define GPIOH GPIO_PORT_H_BASE |
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#define GPIOI GPIO_PORT_I_BASE |
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/* GPIO number definitions (for convenience) */ |
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#define GPIO0 (1 << 0) |
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#define GPIO1 (1 << 1) |
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#define GPIO2 (1 << 2) |
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#define GPIO3 (1 << 3) |
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#define GPIO4 (1 << 4) |
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#define GPIO5 (1 << 5) |
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#define GPIO6 (1 << 6) |
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#define GPIO7 (1 << 7) |
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#define GPIO8 (1 << 8) |
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#define GPIO9 (1 << 9) |
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#define GPIO10 (1 << 10) |
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#define GPIO11 (1 << 11) |
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#define GPIO12 (1 << 12) |
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#define GPIO13 (1 << 13) |
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#define GPIO14 (1 << 14) |
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#define GPIO15 (1 << 15) |
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#define GPIO_ALL 0xffff |
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/* --- GPIO registers ------------------------------------------------------ */ |
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/* Port mode register (GPIOx_MODER) */ |
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#define GPIO_MODER(port) MMIO32(port + 0x00) |
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#define GPIOA_MODER GPIO_MODER(GPIOA) |
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#define GPIOB_MODER GPIO_MODER(GPIOB) |
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#define GPIOC_MODER GPIO_MODER(GPIOC) |
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#define GPIOD_MODER GPIO_MODER(GPIOD) |
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#define GPIOE_MODER GPIO_MODER(GPIOE) |
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#define GPIOF_MODER GPIO_MODER(GPIOF) |
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#define GPIOG_MODER GPIO_MODER(GPIOG) |
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#define GPIOH_MODER GPIO_MODER(GPIOH) |
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#define GPIOI_MODER GPIO_MODER(GPIOI) |
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/* Port output type register (GPIOx_OTYPER) */ |
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#define GPIO_OTYPER(port) MMIO32(port + 0x04) |
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#define GPIOA_OTYPER GPIO_OTYPER(GPIOA) |
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#define GPIOB_OTYPER GPIO_OTYPER(GPIOB) |
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#define GPIOC_OTYPER GPIO_OTYPER(GPIOC) |
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#define GPIOD_OTYPER GPIO_OTYPER(GPIOD) |
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#define GPIOE_OTYPER GPIO_OTYPER(GPIOE) |
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#define GPIOF_OTYPER GPIO_OTYPER(GPIOF) |
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#define GPIOG_OTYPER GPIO_OTYPER(GPIOG) |
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#define GPIOH_OTYPER GPIO_OTYPER(GPIOH) |
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#define GPIOI_OTYPER GPIO_OTYPER(GPIOI) |
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/* Port output speed register (GPIOx_OSPEEDR) */ |
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#define GPIO_OSPEEDR(port) MMIO32(port + 0x08) |
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#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA) |
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#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB) |
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#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC) |
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#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD) |
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#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE) |
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#define GPIOF_OSPEEDR GPIO_OSPEEDR(GPIOF) |
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#define GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG) |
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#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH) |
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#define GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI) |
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/* Port pull-up/pull-down register (GPIOx_PUPDR) */ |
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#define GPIO_PUPDR(port) MMIO32(port + 0x0C) |
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#define GPIOA_PUPDR GPIO_PUPDR(GPIOA) |
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#define GPIOB_PUPDR GPIO_PUPDR(GPIOB) |
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#define GPIOC_PUPDR GPIO_PUPDR(GPIOC) |
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#define GPIOD_PUPDR GPIO_PUPDR(GPIOD) |
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#define GPIOE_PUPDR GPIO_PUPDR(GPIOE) |
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#define GPIOF_PUPDR GPIO_PUPDR(GPIOF) |
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#define GPIOG_PUPDR GPIO_PUPDR(GPIOG) |
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#define GPIOH_PUPDR GPIO_PUPDR(GPIOH) |
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#define GPIOI_PUPDR GPIO_PUPDR(GPIOI) |
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/* Port input data register (GPIOx_IDR) */ |
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#define GPIO_IDR(port) MMIO32(port + 0x10) |
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#define GPIOA_IDR GPIO_IDR(GPIOA) |
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#define GPIOB_IDR GPIO_IDR(GPIOB) |
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#define GPIOC_IDR GPIO_IDR(GPIOC) |
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#define GPIOD_IDR GPIO_IDR(GPIOD) |
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#define GPIOE_IDR GPIO_IDR(GPIOE) |
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#define GPIOF_IDR GPIO_IDR(GPIOF) |
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#define GPIOG_IDR GPIO_IDR(GPIOG) |
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#define GPIOH_IDR GPIO_IDR(GPIOH) |
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#define GPIOI_IDR GPIO_IDR(GPIOI) |
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/* Port output data register (GPIOx_ODR) */ |
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#define GPIO_ODR(port) MMIO32(port + 0x14) |
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#define GPIOA_ODR GPIO_ODR(GPIOA) |
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#define GPIOB_ODR GPIO_ODR(GPIOB) |
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#define GPIOC_ODR GPIO_ODR(GPIOC) |
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#define GPIOD_ODR GPIO_ODR(GPIOD) |
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#define GPIOE_ODR GPIO_ODR(GPIOE) |
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#define GPIOF_ODR GPIO_ODR(GPIOF) |
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#define GPIOG_ODR GPIO_ODR(GPIOG) |
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#define GPIOH_ODR GPIO_ODR(GPIOH) |
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#define GPIOI_ODR GPIO_ODR(GPIOI) |
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/* Port bit set/reset register (GPIOx_BSRR) */ |
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#define GPIO_BSRR(port) MMIO32(port + 0x18) |
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#define GPIOA_BSRR GPIO_BSRR(GPIOA) |
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#define GPIOB_BSRR GPIO_BSRR(GPIOB) |
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#define GPIOC_BSRR GPIO_BSRR(GPIOC) |
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#define GPIOD_BSRR GPIO_BSRR(GPIOD) |
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#define GPIOE_BSRR GPIO_BSRR(GPIOE) |
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#define GPIOF_BSRR GPIO_BSRR(GPIOF) |
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#define GPIOG_BSRR GPIO_BSRR(GPIOG) |
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#define GPIOH_BSRR GPIO_BSRR(GPIOH) |
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#define GPIOI_BSRR GPIO_BSRR(GPIOI) |
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/* Port configuration lock register (GPIOx_LCKR) */ |
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#define GPIO_LCKR(port) MMIO32(port + 0x1C) |
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#define GPIOA_LCKR GPIO_LCKR(GPIOA) |
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#define GPIOB_LCKR GPIO_LCKR(GPIOB) |
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#define GPIOC_LCKR GPIO_LCKR(GPIOC) |
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#define GPIOD_LCKR GPIO_LCKR(GPIOD) |
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#define GPIOE_LCKR GPIO_LCKR(GPIOE) |
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#define GPIOF_LCKR GPIO_LCKR(GPIOF) |
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#define GPIOG_LCKR GPIO_LCKR(GPIOG) |
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#define GPIOH_LCKR GPIO_LCKR(GPIOH) |
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#define GPIOI_LCKR GPIO_LCKR(GPIOI) |
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/* Alternate function low register (GPIOx_AFRL) */ |
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#define GPIO_AFRL(port) MMIO32(port + 0x20) |
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#define GPIOA_AFRL GPIO_AFRL(GPIOA) |
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#define GPIOB_AFRL GPIO_AFRL(GPIOB) |
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#define GPIOC_AFRL GPIO_AFRL(GPIOC) |
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#define GPIOD_AFRL GPIO_AFRL(GPIOD) |
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#define GPIOE_AFRL GPIO_AFRL(GPIOE) |
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#define GPIOF_AFRL GPIO_AFRL(GPIOF) |
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#define GPIOG_AFRL GPIO_AFRL(GPIOG) |
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#define GPIOH_AFRL GPIO_AFRL(GPIOH) |
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#define GPIOI_AFRL GPIO_AFRL(GPIOI) |
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/* Alternate function high register (GPIOx_AFRH) */ |
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#define GPIO_AFRH(port) MMIO32(port + 0x24) |
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#define GPIOA_AFRH GPIO_AFRH(GPIOA) |
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#define GPIOB_AFRH GPIO_AFRH(GPIOB) |
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#define GPIOC_AFRH GPIO_AFRH(GPIOC) |
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#define GPIOD_AFRH GPIO_AFRH(GPIOD) |
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#define GPIOE_AFRH GPIO_AFRH(GPIOE) |
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#define GPIOF_AFRH GPIO_AFRH(GPIOF) |
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#define GPIOG_AFRH GPIO_AFRH(GPIOG) |
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#define GPIOH_AFRH GPIO_AFRH(GPIOH) |
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#define GPIOI_AFRH GPIO_AFRH(GPIOI) |
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/* --- GPIOx_MODER values -------------------------------------------------- */ |
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#define GPIO_MODE(n, mode) (mode << (2*n)) |
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#define GPIO_MODE_INPUT 0x0 |
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#define GPIO_MODE_OUTPUT 0x1 |
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#define GPIO_MODE_AF 0x2 |
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#define GPIO_MODE_ANALOG 0x3 |
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/* --- GPIOx_OTYPER values ------------------------------------------------- */ |
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#define GPIO_OTYPE_PP 0x0 |
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#define GPIO_OTYPE_OD 0x1 |
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/* --- GPIOx_OSPEEDR values ------------------------------------------------ */ |
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#define GPIO_OSPEED(n, speed) (speed << (2*n)) |
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#define GPIO_OSPEED_2MHZ 0x0 |
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#define GPIO_OSPEED_25MHZ 0x1 |
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#define GPIO_OSPEED_50MHZ 0x2 |
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#define GPIO_OSPEED_100MHZ 0x3 |
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/* --- GPIOx_PUPDR values -------------------------------------------------- */ |
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#define GPIO_PUPD(n, pupd) (pupd << (2*n)) |
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#define GPIO_PUPD_NONE 0x0 |
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#define GPIO_PUPD_PULLUP 0x1 |
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#define GPIO_PUPD_PULLDOWN 0x2 |
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/* --- GPIOx_IDR values ---------------------------------------------------- */ |
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/* GPIOx_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */ |
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/* --- GPIOx_ODR values ---------------------------------------------------- */ |
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/* GPIOx_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */ |
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/* --- GPIOx_BSRR values --------------------------------------------------- */ |
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/* GPIOx_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */ |
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/* GPIOx_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */ |
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/* --- GPIOx_LCKR values --------------------------------------------------- */ |
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#define GPIO_LCKK (1 << 16) |
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/* GPIOx_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */ |
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/* --- GPIOx_AFRL/H values ------------------------------------------------- */ |
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/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */ |
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/* See Datasheet Table 6 (pg. 48) for alternate function mappings. */ |
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#define GPIO_AFR(n, af) (af << (n*4)) |
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#define GPIO_AF0 0x0 |
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#define GPIO_AF1 0x1 |
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#define GPIO_AF2 0x2 |
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#define GPIO_AF3 0x3 |
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#define GPIO_AF4 0x4 |
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#define GPIO_AF5 0x5 |
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#define GPIO_AF6 0x6 |
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#define GPIO_AF7 0x7 |
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#define GPIO_AF8 0x8 |
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#define GPIO_AF9 0x9 |
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#define GPIO_AF10 0xA |
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#define GPIO_AF11 0xB |
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#define GPIO_AF12 0xC |
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#define GPIO_AF13 0xD |
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#define GPIO_AF14 0xE |
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#define GPIO_AF15 0xF |
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/* Note: EXTI source selection is now in the SYSCFG peripheral. */ |
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/* --- Function prototypes ------------------------------------------------- */ |
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/*
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* Note: The F2 series has a completely new GPIO peripheral with different |
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* configuration options. Here we implement a different API partly to more |
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* closely match the peripheral capabilities and also to deliberately break |
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* compatibility with old F1 code so there is no confusion with similar |
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* sounding functions that have very different functionality. |
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*/ |
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void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios); |
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void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios); |
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void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios); |
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/* This part of the API is compatible with the F1 series */ |
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void gpio_set(u32 gpioport, u16 gpios); |
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void gpio_clear(u32 gpioport, u16 gpios); |
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u16 gpio_get(u32 gpioport, u16 gpios); |
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void gpio_toggle(u32 gpioport, u16 gpios); |
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u16 gpio_port_read(u32 gpioport); |
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void gpio_port_write(u32 gpioport, u16 data); |
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void gpio_port_config_lock(u32 gpioport, u16 gpios); |
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#endif |
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