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@ -486,6 +486,53 @@ void rcc_clock_setup_in_hsi_out_48mhz(void) |
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rcc_ppre2_frequency = 48000000; |
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} |
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void rcc_clock_setup_in_hsi_out_24mhz(void) { |
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/* Enable internal high-speed oscillator. */ |
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rcc_osc_on(HSI); |
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rcc_wait_for_osc_ready(HSI); |
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/* Select HSI as SYSCLK source. */ |
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); |
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/*
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* Set prescalers for AHB, ADC, ABP1, ABP2. |
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* Do this before touching the PLL (TODO: why?). |
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*/ |
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rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 24MHz Max. 24MHz */ |
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); /* Set. 12MHz Max. 12MHz */ |
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rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_NODIV); /* Set. 24MHz Max. 24MHz */ |
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 24MHz Max. 24MHz */ |
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/*
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* Sysclk is (will be) running with 24MHz -> 2 waitstates. |
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* 0WS from 0-24MHz |
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* 1WS from 24-48MHz |
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* 2WS from 48-72MHz |
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*/ |
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flash_set_ws(FLASH_LATENCY_0WS); |
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/*
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* Set the PLL multiplication factor to 6. |
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* 8MHz (internal) * 6 (multiplier) / 2 (PLLSRC_HSI_CLK_DIV2) = 24MHz |
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*/ |
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rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL6); |
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/* Select HSI/2 as PLL source. */ |
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rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2); |
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/* Enable PLL oscillator and wait for it to stabilize. */ |
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rcc_osc_on(PLL); |
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rcc_wait_for_osc_ready(PLL); |
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/* Select PLL as SYSCLK source. */ |
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); |
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/* Set the peripheral clock frequencies used */ |
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rcc_ppre1_frequency = 24000000; |
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rcc_ppre2_frequency = 24000000; |
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} |
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void rcc_clock_setup_in_hse_8mhz_out_24mhz(void) |
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{ |
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/* Enable internal high-speed oscillator. */ |
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