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@ -127,7 +127,7 @@ |
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/* TEIF: Transfer error interrupt flag */ |
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#define DMA_ISR_TEIF_BIT (1 << 3) |
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#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << (4 * (channel) -1)) |
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#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << (4 * ((channel) -1))) |
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#define DMA_ISR_TEIF1 DMA_ISR_TEIF(DMA_CHANNEL1) |
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#define DMA_ISR_TEIF2 DMA_ISR_TEIF(DMA_CHANNEL2) |
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@ -139,7 +139,7 @@ |
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/* HTIF: Half transfer interrupt flag */ |
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#define DMA_ISR_HTIF_BIT (1 << 2) |
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#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << (4 * (channel) -1)) |
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#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << (4 * ((channel) -1))) |
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#define DMA_ISR_HTIF1 DMA_ISR_HTIF(DMA_CHANNEL1) |
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#define DMA_ISR_HTIF2 DMA_ISR_HTIF(DMA_CHANNEL2) |
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@ -151,7 +151,7 @@ |
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/* TCIF: Transfer complete interrupt flag */ |
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#define DMA_ISR_TCIF_BIT (1 << 1) |
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#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << (4 * (channel) -1)) |
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#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << (4 * ((channel) -1))) |
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#define DMA_ISR_TCIF1 DMA_ISR_TCIF(DMA_CHANNEL1) |
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#define DMA_ISR_TCIF2 DMA_ISR_TCIF(DMA_CHANNEL2) |
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@ -163,7 +163,7 @@ |
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/* GIF: Global interrupt flag */ |
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#define DMA_ISR_GIF_BIT (1 << 0) |
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#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << (4 * (channel) -1)) |
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#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << (4 * ((channel) -1))) |
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#define DMA_ISR_GIF1 DMA_ISR_GIF(DMA_CHANNEL1) |
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#define DMA_ISR_GIF2 DMA_ISR_GIF(DMA_CHANNEL2) |
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@ -177,7 +177,7 @@ |
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/* CTEIF: Transfer error clear */ |
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#define DMA_IFCR_CTEIF_BIT (1 << 3) |
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#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << (4 * (channel) -1)) |
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#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << (4 * ((channel) -1))) |
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#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF(DMA_CHANNEL1) |
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#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF(DMA_CHANNEL2) |
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@ -189,7 +189,7 @@ |
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/* CHTIF: Half transfer clear */ |
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#define DMA_IFCR_CHTIF_BIT (1 << 2) |
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#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << (4 * (channel) -1)) |
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#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << (4 * ((channel) -1))) |
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#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF(DMA_CHANNEL1) |
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#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF(DMA_CHANNEL2) |
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@ -201,7 +201,7 @@ |
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/* CTCIF: Transfer complete clear */ |
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#define DMA_IFCR_CTCIF_BIT (1 << 1) |
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#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << (4 * (channel) -1)) |
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#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << (4 * ((channel) -1))) |
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#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF(DMA_CHANNEL1) |
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#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF(DMA_CHANNEL2) |
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@ -213,7 +213,7 @@ |
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/* CGIF: Global interrupt clear */ |
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#define DMA_IFCR_CGIF_BIT (1 << 0) |
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#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << (4 * (channel) -1)) |
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#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << (4 * ((channel) -1))) |
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#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF(DMA_CHANNEL1) |
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#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF(DMA_CHANNEL2) |
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