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ADC documentation added 

In adc.h additional defines needed to assist documentation - lines 172-191
added, and 384,436-451 are duplicates of earlier defines to complete
parameter sets (compiler has no trouble with these).

Minor doc corrections to other files.

No code changes (apart from additional defines).
pull/24/head
Ken Sarkies 12 years ago
parent
11727f56c9
commit
acc276a612
9 changed files with 725 additions and 35 deletions
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  1. 2
      include/libopencm3/stm32/doc-stm32f.h
  2. 226
      include/libopencm3/stm32/f1/adc.h
  3. 8
      include/libopencm3/stm32/f1/nvic_f1.h
  4. 4
      include/libopencm3/stm32/nvic.h
  5. 4
      lib/stm32/dac.c
  6. 504
      lib/stm32/f1/adc.c
  7. 4
      lib/stm32/iwdg.c
  8. 4
      lib/stm32/nvic.c
  9. 4
      lib/stm32/systick.c

2
include/libopencm3/stm32/doc-stm32f.h
View File

@ -13,7 +13,7 @@
LGPL License Terms @ref lgpl_license LGPL License Terms @ref lgpl_license
*/ */
/** @defgroup STM32F-files STM32F Top Level Files /** @defgroup STM32F_files STM32F Top Level Files
@brief Common Files for ST Microelectronics STM32F series. @brief Common Files for ST Microelectronics STM32F series.

226
include/libopencm3/stm32/f1/adc.h
View File

@ -1,3 +1,17 @@
/** @defgroup STM32F1xx_adc_defines ADC Defines
@brief <b>Defined Constants and Types for the STM32F1xx Analog to Digital Converters</b>
@ingroup STM32F1xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/
/* /*
* This file is part of the libopencm3 project. * This file is part of the libopencm3 project.
* *
@ -17,6 +31,8 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>. * along with this library. If not, see <http://www.gnu.org/licenses/>.
*/ */
/**@{*/
#ifndef LIBOPENCM3_ADC_H #ifndef LIBOPENCM3_ADC_H
#define LIBOPENCM3_ADC_H #define LIBOPENCM3_ADC_H
@ -26,9 +42,15 @@
/* --- Convenience macros -------------------------------------------------- */ /* --- Convenience macros -------------------------------------------------- */
/* ADC port base addresses (for convenience) */ /* ADC port base addresses (for convenience) */
/****************************************************************************/
/** @defgroup adc_reg_base ADC register base addresses
@ingroup STM32F1xx_adc_defines
@{*/
#define ADC1 ADC1_BASE #define ADC1 ADC1_BASE
#define ADC2 ADC2_BASE #define ADC2 ADC2_BASE
#define ADC3 ADC3_BASE #define ADC3 ADC3_BASE
/**@}*/
/* --- ADC registers ------------------------------------------------------- */ /* --- ADC registers ------------------------------------------------------- */
@ -140,6 +162,35 @@
#define ADC2_DR ADC_DR(ADC2) #define ADC2_DR ADC_DR(ADC2)
#define ADC3_DR ADC_DR(ADC3) #define ADC3_DR ADC_DR(ADC3)
/* --- ADC Channels ------------------------------------------------------- */
/****************************************************************************/
/** @defgroup adc_channel ADC Channel Numbers
@ingroup STM32F1xx_adc_defines
@{*/
#define ADC_CHANNEL0 0x00
#define ADC_CHANNEL1 0x01
#define ADC_CHANNEL2 0x02
#define ADC_CHANNEL3 0x03
#define ADC_CHANNEL4 0x04
#define ADC_CHANNEL5 0x05
#define ADC_CHANNEL6 0x06
#define ADC_CHANNEL7 0x07
#define ADC_CHANNEL8 0x08
#define ADC_CHANNEL9 0x09
#define ADC_CHANNEL10 0x0A
#define ADC_CHANNEL11 0x0B
#define ADC_CHANNEL12 0x0C
#define ADC_CHANNEL13 0x0D
#define ADC_CHANNEL14 0x0E
#define ADC_CHANNEL15 0x0F
#define ADC_CHANNEL16 0x10
#define ADC_CHANNEL17 0x11
#define ADC_MASK 0x1F
#define ADC_SHIFT 0
/**@}*/
/* --- ADC_SR values ------------------------------------------------------- */ /* --- ADC_SR values ------------------------------------------------------- */
#define ADC_SR_STRT (1 << 4) #define ADC_SR_STRT (1 << 4)
@ -171,20 +222,42 @@
* SIM: Slow interleaved mode only. * SIM: Slow interleaved mode only.
* ATM: Alternate trigger mode only. * ATM: Alternate trigger mode only.
*/ */
/****************************************************************************/
/* ADC_CR1 DUALMOD[3:0] ADC Mode Selection */
/** @defgroup adc_cr1_dualmod ADC Mode Selection
@ingroup STM32F1xx_adc_defines
@{*/
/** Independent (non-dual) mode */
#define ADC_CR1_DUALMOD_IND (0x0 << 16) #define ADC_CR1_DUALMOD_IND (0x0 << 16)
/** Combined regular simultaneous + injected simultaneous mode. */
#define ADC_CR1_DUALMOD_CRSISM (0x1 << 16) #define ADC_CR1_DUALMOD_CRSISM (0x1 << 16)
/** Combined regular simultaneous + alternate trigger mode. */
#define ADC_CR1_DUALMOD_CRSATM (0x2 << 16) #define ADC_CR1_DUALMOD_CRSATM (0x2 << 16)
/** Combined injected simultaneous + fast interleaved mode. */
#define ADC_CR1_DUALMOD_CISFIM (0x3 << 16) #define ADC_CR1_DUALMOD_CISFIM (0x3 << 16)
/** Combined injected simultaneous + slow interleaved mode. */
#define ADC_CR1_DUALMOD_CISSIM (0x4 << 16) #define ADC_CR1_DUALMOD_CISSIM (0x4 << 16)
/** Injected simultaneous mode only. */
#define ADC_CR1_DUALMOD_ISM (0x5 << 16) #define ADC_CR1_DUALMOD_ISM (0x5 << 16)
/** Regular simultaneous mode only. */
#define ADC_CR1_DUALMOD_RSM (0x6 << 16) #define ADC_CR1_DUALMOD_RSM (0x6 << 16)
/** Fast interleaved mode only. */
#define ADC_CR1_DUALMOD_FIM (0x7 << 16) #define ADC_CR1_DUALMOD_FIM (0x7 << 16)
/** Slow interleaved mode only. */
#define ADC_CR1_DUALMOD_SIM (0x8 << 16) #define ADC_CR1_DUALMOD_SIM (0x8 << 16)
/** Alternate trigger mode only. */
#define ADC_CR1_DUALMOD_ATM (0x9 << 16) #define ADC_CR1_DUALMOD_ATM (0x9 << 16)
#define ADC_CR1_DUALMOD_MASK (0xF << 16) #define ADC_CR1_DUALMOD_MASK (0xF << 16)
#define ADC_CR1_DUALMOD_SHIFT 16 #define ADC_CR1_DUALMOD_SHIFT 16
/**@}*/
/* DISCNUM[2:0]: Discontinous mode channel count. */ /* DISCNUM[2:0]: Discontinous mode channel count. */
/****************************************************************************/
/** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode.
@ingroup STM32F1xx_adc_defines
@{*/
#define ADC_CR1_DISCNUM_1CHANNELS (0x0 << 13) #define ADC_CR1_DISCNUM_1CHANNELS (0x0 << 13)
#define ADC_CR1_DISCNUM_2CHANNELS (0x1 << 13) #define ADC_CR1_DISCNUM_2CHANNELS (0x1 << 13)
#define ADC_CR1_DISCNUM_3CHANNELS (0x2 << 13) #define ADC_CR1_DISCNUM_3CHANNELS (0x2 << 13)
@ -195,29 +268,30 @@
#define ADC_CR1_DISCNUM_8CHANNELS (0x7 << 13) #define ADC_CR1_DISCNUM_8CHANNELS (0x7 << 13)
#define ADC_CR1_DISCNUM_MASK (0x7 << 13) #define ADC_CR1_DISCNUM_MASK (0x7 << 13)
#define ADC_CR1_DISCNUM_SHIFT 13 #define ADC_CR1_DISCNUM_SHIFT 13
/**@}*/
/* JDISCEN: Discontinous mode on injected channels. */ /* JDISCEN: */ /** Discontinous mode on injected channels. */
#define ADC_CR1_JDISCEN (1 << 12) #define ADC_CR1_JDISCEN (1 << 12)
/* DISCEN: Discontinous mode on regular channels. */ /* DISCEN: */ /** Discontinous mode on regular channels. */
#define ADC_CR1_DISCEN (1 << 11) #define ADC_CR1_DISCEN (1 << 11)
/* JAUTO: Automatic Injection Group conversion. */ /* JAUTO: */ /** Automatic Injection Group conversion. */
#define ADC_CR1_JAUTO (1 << 10) #define ADC_CR1_JAUTO (1 << 10)
/* AWDSGL: Enable the watchdog on a single channel in scan mode. */ /* AWDSGL: */ /** Enable the watchdog on a single channel in scan mode. */
#define ADC_CR1_AWDSGL (1 << 9) #define ADC_CR1_AWDSGL (1 << 9)
/* SCAN: Scan mode. */ /* SCAN: */ /** Scan mode. */
#define ADC_CR1_SCAN (1 << 8) #define ADC_CR1_SCAN (1 << 8)
/* JEOCIE: Interrupt enable for injected channels. */ /* JEOCIE: */ /** Interrupt enable for injected channels. */
#define ADC_CR1_JEOCIE (1 << 7) #define ADC_CR1_JEOCIE (1 << 7)
/* AWDIE: Analog watchdog interrupt enable. */ /* AWDIE: */ /** Analog watchdog interrupt enable. */
#define ADC_CR1_AWDIE (1 << 6) #define ADC_CR1_AWDIE (1 << 6)
/* EOCIE: Interrupt enable EOC. */ /* EOCIE: */ /** Interrupt enable EOC. */
#define ADC_CR1_EOCIE (1 << 5) #define ADC_CR1_EOCIE (1 << 5)
/* AWDCH[4:0]: Analog watchdog channel bits. (Up to 17 other values reserved) */ /* AWDCH[4:0]: Analog watchdog channel bits. (Up to 17 other values reserved) */
@ -227,6 +301,12 @@
* ADC2: Analog channel 16 and 17 are internally connected to V_SS. * ADC2: Analog channel 16 and 17 are internally connected to V_SS.
* ADC3: Analog channel 9, 14, 15, 16 and 17 are internally connected to V_SS. * ADC3: Analog channel 9, 14, 15, 16 and 17 are internally connected to V_SS.
*/ */
/****************************************************************************/
/* ADC_CR1 AWDCH[4:0] ADC watchdog channel */
/** @defgroup adc_watchdog_channel ADC watchdog channel
@ingroup STM32F1xx_adc_defines
@{*/
#define ADC_CR1_AWDCH_CHANNEL0 (0x00 << 0) #define ADC_CR1_AWDCH_CHANNEL0 (0x00 << 0)
#define ADC_CR1_AWDCH_CHANNEL1 (0x01 << 0) #define ADC_CR1_AWDCH_CHANNEL1 (0x01 << 0)
#define ADC_CR1_AWDCH_CHANNEL2 (0x02 << 0) #define ADC_CR1_AWDCH_CHANNEL2 (0x02 << 0)
@ -247,39 +327,70 @@
#define ADC_CR1_AWDCH_CHANNEL17 (0x11 << 0) #define ADC_CR1_AWDCH_CHANNEL17 (0x11 << 0)
#define ADC_CR1_AWDCH_MASK (0x1F << 0) #define ADC_CR1_AWDCH_MASK (0x1F << 0)
#define ADC_CR1_AWDCH_SHIFT 0 #define ADC_CR1_AWDCH_SHIFT 0
/**@}*/
/* --- ADC_CR2 values ------------------------------------------------------ */ /* --- ADC_CR2 values ------------------------------------------------------ */
/* TSVREFE: Temperature sensor and V_REFINT enable. (ADC1 only!) */ /* TSVREFE: */ /** Temperature sensor and V_REFINT enable. (ADC1 only!) */
#define ADC_CR2_TSVREFE (1 << 23) #define ADC_CR2_TSVREFE (1 << 23)
/* SWSTART: Start conversion of regular channels. */ /* SWSTART: */ /** Start conversion of regular channels. */
#define ADC_CR2_SWSTART (1 << 22) #define ADC_CR2_SWSTART (1 << 22)
/* JSWSTART: Start conversion of injected channels. */ /* JSWSTART: */ /** Start conversion of injected channels. */
#define ADC_CR2_JSWSTART (1 << 21) #define ADC_CR2_JSWSTART (1 << 21)
/* EXTTRIG: External trigger conversion mode for regular channels. */ /* EXTTRIG: */ /** External trigger conversion mode for regular channels. */
#define ADC_CR2_EXTTRIG (1 << 20) #define ADC_CR2_EXTTRIG (1 << 20)
/* EXTSEL[2:0]: External event select for regular group. */ /* EXTSEL[2:0]: External event select for regular group. */
/* The following are only valid for ADC1 and ADC2. */ /* The following are only valid for ADC1 and ADC2. */
/****************************************************************************/
/* ADC_CR2 EXTSEL[2:0] ADC Trigger Identifier for ADC1 and ADC2 */
/** @defgroup adc_trigger_regular_12 ADC Trigger Identifier for ADC1 and ADC2
@ingroup STM32F1xx_adc_defines
@{*/
/** Timer 1 Compare Output 1 */
#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 17) #define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 17)
/** Timer 1 Compare Output 2 */
#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 17) #define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 17)
/** Timer 1 Compare Output 3 */
#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17) #define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17)
/** Timer 2 Compare Output 2 */
#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 17) #define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 17)
/** Timer 3 Trigger Output */
#define ADC_CR2_EXTSEL_TIM3_TRGO (0x4 << 17) #define ADC_CR2_EXTSEL_TIM3_TRGO (0x4 << 17)
/** Timer 4 Compare Output 4 */
#define ADC_CR2_EXTSEL_TIM4_CC4 (0x5 << 17) #define ADC_CR2_EXTSEL_TIM4_CC4 (0x5 << 17)
/** External Interrupt 11 */
#define ADC_CR2_EXTSEL_EXTI11 (0x6 << 17) #define ADC_CR2_EXTSEL_EXTI11 (0x6 << 17)
/** Software Trigger */
#define ADC_CR2_EXTSEL_SWSTART (0x7 << 17) #define ADC_CR2_EXTSEL_SWSTART (0x7 << 17)
/**@}*/
/* The following are only valid for ADC3 */ /* The following are only valid for ADC3 */
/****************************************************************************/
/* ADC_CR2 EXTSEL[2:0] ADC Trigger Identifier for ADC3 */
/** @defgroup adc_trigger_regular_3 ADC Trigger Identifier for ADC3
@ingroup STM32F1xx_adc_defines
@{*/
/** Timer 2 Compare Output 1 */
#define ADC_CR2_EXTSEL_TIM3_CC1 (0x0 << 17) #define ADC_CR2_EXTSEL_TIM3_CC1 (0x0 << 17)
/** Timer 2 Compare Output 3 */
#define ADC_CR2_EXTSEL_TIM2_CC3 (0x1 << 17) #define ADC_CR2_EXTSEL_TIM2_CC3 (0x1 << 17)
/** Timer 1 Compare Output 3 */
#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17)
/** Timer 8 Compare Output 1 */
#define ADC_CR2_EXTSEL_TIM8_CC1 (0x3 << 17) #define ADC_CR2_EXTSEL_TIM8_CC1 (0x3 << 17)
/** Timer 8 Trigger Output */
#define ADC_CR2_EXTSEL_TIM8_TRGO (0x4 << 17) #define ADC_CR2_EXTSEL_TIM8_TRGO (0x4 << 17)
/** Timer 5 Compare Output 1 */
#define ADC_CR2_EXTSEL_TIM5_CC1 (0x5 << 17) #define ADC_CR2_EXTSEL_TIM5_CC1 (0x5 << 17)
/** Timer 5 Compare Output 3 */
#define ADC_CR2_EXTSEL_TIM5_CC3 (0x6 << 17) #define ADC_CR2_EXTSEL_TIM5_CC3 (0x6 << 17)
/**@}*/
#define ADC_CR2_EXTSEL_MASK (0x7 << 17) #define ADC_CR2_EXTSEL_MASK (0x7 << 17)
#define ADC_CR2_EXTSEL_SHIFT 17 #define ADC_CR2_EXTSEL_SHIFT 17
@ -291,21 +402,54 @@
/* JEXTSEL[2:0]: External event selection for injected group. */ /* JEXTSEL[2:0]: External event selection for injected group. */
/* The following are only valid for ADC1 and ADC2. */ /* The following are only valid for ADC1 and ADC2. */
/****************************************************************************/
/* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC1 and ADC2 */
/** @defgroup adc_trigger_injected_12 ADC Injected Trigger Identifier for ADC1 and ADC2
@ingroup STM32F1xx_adc_defines
@{*/
/** Timer 1 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12) #define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12)
/** Timer 1 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12) #define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12)
/** Timer 2 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x2 << 12) #define ADC_CR2_JEXTSEL_TIM2_TRGO (0x2 << 12)
/** Timer 2 Compare Output 1 */
#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x3 << 12) #define ADC_CR2_JEXTSEL_TIM2_CC1 (0x3 << 12)
/** Timer 3 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x4 << 12) #define ADC_CR2_JEXTSEL_TIM3_CC4 (0x4 << 12)
/** Timer 4 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x5 << 12) #define ADC_CR2_JEXTSEL_TIM4_TRGO (0x5 << 12)
/** External Interrupt 15 */
#define ADC_CR2_JEXTSEL_EXTI15 (0x6 << 12) #define ADC_CR2_JEXTSEL_EXTI15 (0x6 << 12)
/** Injected Software Trigger */
#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */ #define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */
/**@}*/
/* The following are the different meanings for ADC3 only. */ /* The following are the different meanings for ADC3 only. */
/****************************************************************************/
/* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC3 */
/** @defgroup adc_trigger_injected_3 ADC Injected Trigger Identifier for ADC3
@ingroup STM32F1xx_adc_defines
@{*/
/** Timer 1 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12)
/** Timer 1 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12)
/** Timer 4 Compare Output 3 */
#define ADC_CR2_JEXTSEL_TIM4_CC3 (0x2 << 12) #define ADC_CR2_JEXTSEL_TIM4_CC3 (0x2 << 12)
/** Timer 8 Compare Output 2 */
#define ADC_CR2_JEXTSEL_TIM8_CC2 (0x3 << 12) #define ADC_CR2_JEXTSEL_TIM8_CC2 (0x3 << 12)
/** Timer 8 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM8_CC4 (0x4 << 12) #define ADC_CR2_JEXTSEL_TIM8_CC4 (0x4 << 12)
/** Timer 5 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM5_TRGO (0x5 << 12) #define ADC_CR2_JEXTSEL_TIM5_TRGO (0x5 << 12)
/** Timer53 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM5_CC4 (0x6 << 12) #define ADC_CR2_JEXTSEL_TIM5_CC4 (0x6 << 12)
/** Injected Software Trigger */
#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */
/**@}*/
#define ADC_CR2_JEXTSEL_MASK (0x7 << 12) #define ADC_CR2_JEXTSEL_MASK (0x7 << 12)
#define ADC_CR2_JEXTSEL_SHIFT 12 #define ADC_CR2_JEXTSEL_SHIFT 12
@ -340,7 +484,6 @@
#define ADC_CR2_ADON (1 << 0) #define ADC_CR2_ADON (1 << 0)
/* --- ADC_SMPR1 values ---------------------------------------------------- */ /* --- ADC_SMPR1 values ---------------------------------------------------- */
#define ADC_SMPR1_SMP17_LSB 21 #define ADC_SMPR1_SMP17_LSB 21
#define ADC_SMPR1_SMP16_LSB 18 #define ADC_SMPR1_SMP16_LSB 18
#define ADC_SMPR1_SMP15_LSB 15 #define ADC_SMPR1_SMP15_LSB 15
@ -357,6 +500,12 @@
#define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMP12_LSB) #define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMP12_LSB)
#define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMP11_LSB) #define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMP11_LSB)
#define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMP10_LSB) #define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMP10_LSB)
/****************************************************************************/
/* ADC_SMPR1 ADC Sample Time Selection for Channels */
/** @defgroup adc_sample_r1 ADC Sample Time Selection for ADC1
@ingroup STM32F1xx_adc_defines
@{*/
#define ADC_SMPR1_SMP_1DOT5CYC 0x0 #define ADC_SMPR1_SMP_1DOT5CYC 0x0
#define ADC_SMPR1_SMP_7DOT5CYC 0x1 #define ADC_SMPR1_SMP_7DOT5CYC 0x1
#define ADC_SMPR1_SMP_13DOT5CYC 0x2 #define ADC_SMPR1_SMP_13DOT5CYC 0x2
@ -365,6 +514,7 @@
#define ADC_SMPR1_SMP_55DOT5CYC 0x5 #define ADC_SMPR1_SMP_55DOT5CYC 0x5
#define ADC_SMPR1_SMP_71DOT5CYC 0x6 #define ADC_SMPR1_SMP_71DOT5CYC 0x6
#define ADC_SMPR1_SMP_239DOT5CYC 0x7 #define ADC_SMPR1_SMP_239DOT5CYC 0x7
/**@}*/
/* --- ADC_SMPR2 values ---------------------------------------------------- */ /* --- ADC_SMPR2 values ---------------------------------------------------- */
@ -388,6 +538,12 @@
#define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMP2_LSB) #define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMP2_LSB)
#define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMP1_LSB) #define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMP1_LSB)
#define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMP0_LSB) #define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMP0_LSB)
/****************************************************************************/
/* ADC_SMPR2 ADC Sample Time Selection for Channels */
/** @defgroup adc_sample_r2 ADC Sample Time Selection for ADC2
@ingroup STM32F1xx_adc_defines
@{*/
#define ADC_SMPR2_SMP_1DOT5CYC 0x0 #define ADC_SMPR2_SMP_1DOT5CYC 0x0
#define ADC_SMPR2_SMP_7DOT5CYC 0x1 #define ADC_SMPR2_SMP_7DOT5CYC 0x1
#define ADC_SMPR2_SMP_13DOT5CYC 0x2 #define ADC_SMPR2_SMP_13DOT5CYC 0x2
@ -396,9 +552,15 @@
#define ADC_SMPR2_SMP_55DOT5CYC 0x5 #define ADC_SMPR2_SMP_55DOT5CYC 0x5
#define ADC_SMPR2_SMP_71DOT5CYC 0x6 #define ADC_SMPR2_SMP_71DOT5CYC 0x6
#define ADC_SMPR2_SMP_239DOT5CYC 0x7 #define ADC_SMPR2_SMP_239DOT5CYC 0x7
/**@}*/
/* --- ADC_SMPRx generic values -------------------------------------------- */ /* --- ADC_SMPRx generic values -------------------------------------------- */
/****************************************************************************/
/* ADC_SMPRG ADC Sample Time Selection for Channels */
/** @defgroup adc_sample_rg ADC Sample Time Selection Generic
@ingroup STM32F1xx_adc_defines
@{*/
#define ADC_SMPR_SMP_1DOT5CYC 0x0 #define ADC_SMPR_SMP_1DOT5CYC 0x0
#define ADC_SMPR_SMP_7DOT5CYC 0x1 #define ADC_SMPR_SMP_7DOT5CYC 0x1
#define ADC_SMPR_SMP_13DOT5CYC 0x2 #define ADC_SMPR_SMP_13DOT5CYC 0x2
@ -407,6 +569,7 @@
#define ADC_SMPR_SMP_55DOT5CYC 0x5 #define ADC_SMPR_SMP_55DOT5CYC 0x5
#define ADC_SMPR_SMP_71DOT5CYC 0x6 #define ADC_SMPR_SMP_71DOT5CYC 0x6
#define ADC_SMPR_SMP_239DOT5CYC 0x7 #define ADC_SMPR_SMP_239DOT5CYC 0x7
/**@}*/
/* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */ /* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */
@ -429,6 +592,13 @@
#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQ15_LSB) #define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQ15_LSB)
#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQ14_LSB) #define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQ14_LSB)
#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQ13_LSB) #define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQ13_LSB)
/* TODO Fix error
#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB)
#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB)
#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB)
#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB)
#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB)
*/
/* --- ADC_SQR2 values ----------------------------------------------------- */ /* --- ADC_SQR2 values ----------------------------------------------------- */
@ -444,6 +614,14 @@
#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQ9_LSB) #define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQ9_LSB)
#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQ8_LSB) #define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQ8_LSB)
#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQ7_LSB) #define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQ7_LSB)
/* TODO Fix error
#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB)
#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB)
#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB)
#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB)
#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB)
#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB)
*/
/* --- ADC_SQR3 values ----------------------------------------------------- */ /* --- ADC_SQR3 values ----------------------------------------------------- */
@ -459,7 +637,14 @@
#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQ3_LSB) #define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQ3_LSB)
#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQ2_LSB) #define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQ2_LSB)
#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQ1_LSB) #define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQ1_LSB)
/* TODO Fix error
#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB)
#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB)
#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB)
#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB)
#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB)
#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB)
*/
/* --- ADC_JSQR values ----------------------------------------------------- */ /* --- ADC_JSQR values ----------------------------------------------------- */
#define ADC_JSQR_JL_LSB 20 #define ADC_JSQR_JL_LSB 20
@ -472,6 +657,13 @@
#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQ3_LSB) #define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQ3_LSB)
#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQ2_LSB) #define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQ2_LSB)
#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQ1_LSB) #define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQ1_LSB)
/* TODO Fix error
#define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB)
#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB)
#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB)
#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)
#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)
*/
/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ /* --- ADC_JDRx, ADC_DR values --------------------------------------------- */
@ -481,12 +673,10 @@
#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB) #define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB)
#define ADC_DATA_MSK (0xffff << ADC_DA) #define ADC_DATA_MSK (0xffff << ADC_DA)
#define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB) #define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB)
/* ADC1 only (dual mode) */ /* ADC1 only (dual mode) */
/* --- Function prototypes ------------------------------------------------- */ /* --- Function prototypes ------------------------------------------------- */
/* TODO */
void adc_enable_analog_watchdog_regular(u32 adc); void adc_enable_analog_watchdog_regular(u32 adc);
void adc_disable_analog_watchdog_regular(u32 adc); void adc_disable_analog_watchdog_regular(u32 adc);
void adc_enable_analog_watchdog_injected(u32 adc); void adc_enable_analog_watchdog_injected(u32 adc);
@ -533,3 +723,5 @@ void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]);
void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]); void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]);
#endif #endif
/**@}*/

8
include/libopencm3/stm32/f1/nvic_f1.h
View File

@ -1,8 +1,4 @@
/** @defgroup STM32F_nvic_f1_defines STM32F NVIC Defines /** @brief <b>Defined Constants and Types for the STM32F1xx Nested Vectored Interrupt Controller</b>
@brief <b>Defined Constants and Types for the STM32F1xx Nested Vectored Interrupt Controller</b>
@ingroup STM32F_defines
@version 1.0.0 @version 1.0.0
@ -113,6 +109,6 @@ LGPL License Terms @ref lgpl_license
#define NVIC_CAN2_RX1_IRQ 65 #define NVIC_CAN2_RX1_IRQ 65
#define NVIC_CAN2_SCE_IRQ 66 #define NVIC_CAN2_SCE_IRQ 66
#define NVIC_OTG_FS_IRQ 67 #define NVIC_OTG_FS_IRQ 67
/*@}*/ /**@}*/
#endif #endif

4
include/libopencm3/stm32/nvic.h
View File

@ -1,4 +1,4 @@
/** @defgroup STM32F_nvic_defines STM32F NVIC Defines /** @defgroup STM32F_nvic_defines NVIC Defines
@brief <b>libopencm3 STM32F Nested Vectored Interrupt Controller</b> @brief <b>libopencm3 STM32F Nested Vectored Interrupt Controller</b>
@ -96,7 +96,7 @@ IRQ numbers -3 and -6 to -9 are reserved
/* irq number -3 reserved */ /* irq number -3 reserved */
#define NVIC_PENDSV_IRQ -2 #define NVIC_PENDSV_IRQ -2
#define NVIC_SYSTICK_IRQ -1 #define NVIC_SYSTICK_IRQ -1
/*@}*/ /**@}*/
/* Note: User interrupts are family specific and are defined in a family /* Note: User interrupts are family specific and are defined in a family

4
lib/stm32/dac.c
View File

@ -1,6 +1,6 @@
/** @defgroup STM32F-dac-file DAC /** @defgroup STM32F_dac_file DAC
@ingroup STM32F-files @ingroup STM32F_files
@brief <b>libopencm3 STM32Fxx Digital to Analog Converter</b> @brief <b>libopencm3 STM32Fxx Digital to Analog Converter</b>

504
lib/stm32/f1/adc.c
View File

@ -1,3 +1,70 @@
/** @defgroup STM32F1xx_adc_file ADC
@ingroup STM32F1xx
@brief <b>libopencm3 STM32F1xx Analog to Digital Converters</b>
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@date 18 August 2012
This library supports the A/D Converter Control System in the STM32F1xx series
of ARM Cortex Microcontrollers by ST Microelectronics.
Devices can have up to three A/D converters each with their own set of registers.
However all the A/D converters share a common clock which is prescaled from the APB2
clock by default by a minimum factor of 2 to a maximum of 8.
Each A/D converter has up to 18 channels:
@li On ADC1 the analog channels 16 and 17 are internally connected to the temperature
sensor and V<sub>REFINT</sub>, respectively.
@li On ADC2 the analog channels 16 and 17 are internally connected to V<sub>SS</sub>.
@li On ADC3 the analog channels 9, 14, 15, 16 and 17 are internally connected to V<sub>SS</sub>.
The conversions can occur as a one-off conversion whereby the process stops once
conversion is complete. The conversions can also be continuous wherein a new
conversion starts immediately the previous conversion has ended.
Conversion can occur as a single channel conversion or a scan of a group of
channels in either continuous or one-off mode. If more than one channel is converted
in a scan group, DMA must be used to transfer the data as there is only one
result register available. An interrupt can be set to occur at the end of
conversion, which occurs after all channels have been scanned.
A discontinuous mode allows a subgroup of group of a channels to be converted in
bursts of a given length.
Injected conversions allow a second group of channels to be converted separately
from the regular group. An interrupt can be set to occur at the end of
conversion, which occurs after all channels have been scanned.
@section adc_api_ex Basic ADC Handling API.
Example 1: Simple single channel conversion polled. Enable the peripheral clock
and ADC, reset ADC and set the prescaler divider. Set dual mode to independent.
@code
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN);
adc_power_on(ADC1);
adc_calibration(ADC1);
rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_ADC1RST);
rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_ADC1RST);
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2);
adc_set_dual_mode(ADC_CR1_DUALMOD_IND);
adc_disable_scan_mode(ADC1);
adc_set_single_conversion_mode(ADC1);
adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR1_SMP_1DOT5CYC);
adc_set_single_channel(ADC1, ADC_CHANNEL0);
adc_start_conversion_regular(ADC1);
while (! adc_eoc(ADC1));
reg16 = adc_read_regular(ADC1);
@endcode
LGPL License Terms @ref lgpl_license
*/
/* /*
* This file is part of the libopencm3 project. * This file is part of the libopencm3 project.
* *
@ -27,10 +94,12 @@
* rcc_peripheral_clear_reset(&RCC_APB2RSTR, ADC1RST); * rcc_peripheral_clear_reset(&RCC_APB2RSTR, ADC1RST);
* *
* rcc_set_adc_clk(ADC_PRE_PLCK2_DIV2); * rcc_set_adc_clk(ADC_PRE_PLCK2_DIV2);
* adc_set_mode(ADC1, TODO); * adc_set_dual_mode(ADC1, TODO);
* reg16 = adc_read(ADC1, ADC_CH_0); * reg16 = adc_read(ADC1, ADC_CH_0);
*/ */
/**@{*/
#include <libopencm3/stm32/f1/adc.h> #include <libopencm3/stm32/f1/adc.h>
void rcc_set_adc_clk(u32 prescaler) void rcc_set_adc_clk(u32 prescaler)
@ -50,6 +119,14 @@ void adc_set_mode(u32 block, /* TODO */ u8 mode)
mode = mode; mode = mode;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Read from a Conversion Result Register
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] reg Unsigned int8. Register number (1 ... 4).
@returns Unsigned int32 conversion result.
*/
void adc_read(u32 block, u32 channel) void adc_read(u32 block, u32 channel)
{ {
/* TODO */ /* TODO */
@ -59,61 +136,167 @@ void adc_read(u32 block, u32 channel)
channel = channel; channel = channel;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog for Regular Conversions
The analog watchdog allows the monitoring of an analog signal between two threshold
levels. The thresholds must be preset. Comparison is done before data alignment
takes place, so the thresholds are left-aligned.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_analog_watchdog_regular(u32 adc) void adc_enable_analog_watchdog_regular(u32 adc)
{ {
ADC_CR1(adc) |= ADC_CR1_AWDEN; ADC_CR1(adc) |= ADC_CR1_AWDEN;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable Analog Watchdog for Regular Conversions
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_analog_watchdog_regular(u32 adc) void adc_disable_analog_watchdog_regular(u32 adc)
{ {
ADC_CR1(adc) &= ~ADC_CR1_AWDEN; ADC_CR1(adc) &= ~ADC_CR1_AWDEN;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog for Injected Conversions
The analog watchdog allows the monitoring of an analog signal between two threshold
levels. The thresholds must be preset. Comparison is done before data alignment
takes place, so the thresholds are left-aligned.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_analog_watchdog_injected(u32 adc) void adc_enable_analog_watchdog_injected(u32 adc)
{ {
ADC_CR1(adc) |= ADC_CR1_JAWDEN; ADC_CR1(adc) |= ADC_CR1_JAWDEN;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable Analog Watchdog for Injected Conversions
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_analog_watchdog_injected(u32 adc) void adc_disable_analog_watchdog_injected(u32 adc)
{ {
ADC_CR1(adc) &= ~ADC_CR1_JAWDEN; ADC_CR1(adc) &= ~ADC_CR1_JAWDEN;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Enable Discontinuous Mode for Regular Conversions
In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the
defined regular channel group. The subgroup is defined by the number of
consecutive channels to be converted. After a subgroup has been converted
the next trigger will start conversion of the immediately following subgroup
of the same length or until the whole group has all been converted. When the
the whole group has been converted, the next trigger will restart conversion
of the subgroup at the beginning of the whole group.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] length Unsigned int8. Number of channels in the group @ref adc_cr1_discnum
*/
void adc_enable_discontinous_mode_regular(u32 adc) void adc_enable_discontinous_mode_regular(u32 adc)
{ {
ADC_CR1(adc) |= ADC_CR1_DISCEN; ADC_CR1(adc) |= ADC_CR1_DISCEN;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable Discontinuous Mode for Regular Conversions
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_discontinous_mode_regular(u32 adc) void adc_disable_discontinous_mode_regular(u32 adc)
{ {
ADC_CR1(adc) &= ~ADC_CR1_DISCEN; ADC_CR1(adc) &= ~ADC_CR1_DISCEN;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Enable Discontinuous Mode for Injected Conversions
In this mode the ADC converts sequentially one channel of the defined group of
injected channels, cycling back to the first channel in the group once the
entire group has been converted.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_discontinous_mode_injected(u32 adc) void adc_enable_discontinous_mode_injected(u32 adc)
{ {
ADC_CR1(adc) |= ADC_CR1_JDISCEN; ADC_CR1(adc) |= ADC_CR1_JDISCEN;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable Discontinuous Mode for Injected Conversions
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_discontinous_mode_injected(u32 adc) void adc_disable_discontinous_mode_injected(u32 adc)
{ {
ADC_CR1(adc) &= ~ADC_CR1_JDISCEN; ADC_CR1(adc) &= ~ADC_CR1_JDISCEN;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Enable Automatic Injected Conversions
The ADC converts a defined injected group of channels immediately after the
regular channels have been converted. The external trigger on the injected
channels is disabled as required.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_automatic_injected_group_conversion(u32 adc) void adc_enable_automatic_injected_group_conversion(u32 adc)
{ {
ADC_CR1(adc) |= ADC_CR1_JAUTO; ADC_CR1(adc) |= ADC_CR1_JAUTO;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable Automatic Injected Conversions
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_automatic_injected_group_conversion(u32 adc) void adc_disable_automatic_injected_group_conversion(u32 adc)
{ {
ADC_CR1(adc) &= ~ADC_CR1_JAUTO; ADC_CR1(adc) &= ~ADC_CR1_JAUTO;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog for All Regular and Injected Channels
The analog watchdog allows the monitoring of an analog signal between two threshold
levels. The thresholds must be preset. Comparison is done before data alignment
takes place, so the thresholds are left-aligned.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_analog_watchdog_on_all_channels(u32 adc) void adc_enable_analog_watchdog_on_all_channels(u32 adc)
{ {
ADC_CR1(adc) |= ADC_CR1_AWDSGL; ADC_CR1(adc) |= ADC_CR1_AWDSGL;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog for a Selected Channel
The analog watchdog allows the monitoring of an analog signal between two threshold
levels. The thresholds must be preset. Comparison is done before data alignment
takes place, so the thresholds are left-aligned.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel
*/
void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel) void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel)
{ {
u32 reg32; u32 reg32;
@ -125,56 +308,140 @@ void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel)
ADC_CR1(adc) &= ~ADC_CR1_AWDSGL; ADC_CR1(adc) &= ~ADC_CR1_AWDSGL;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Set Scan Mode
In this mode a conversion consists of a scan of the predefined set of channels,
regular and injected, each channel conversion immediately following the
previous one. It can use single, continuous or discontinuous mode.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_scan_mode(u32 adc) void adc_enable_scan_mode(u32 adc)
{ {
ADC_CR1(adc) |= ADC_CR1_SCAN; ADC_CR1(adc) |= ADC_CR1_SCAN;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable Scan Mode
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_scan_mode(u32 adc) void adc_disable_scan_mode(u32 adc)
{ {
ADC_CR1(adc) &= ~ADC_CR1_SCAN; ADC_CR1(adc) &= ~ADC_CR1_SCAN;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Enable Injected End-Of-Conversion Interrupt
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_jeoc_interrupt(u32 adc) void adc_enable_jeoc_interrupt(u32 adc)
{ {
ADC_CR1(adc) |= ADC_CR1_JEOCIE; ADC_CR1(adc) |= ADC_CR1_JEOCIE;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable Injected End-Of-Conversion Interrupt
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_jeoc_interrupt(u32 adc) void adc_disable_jeoc_interrupt(u32 adc)
{ {
ADC_CR1(adc) &= ~ADC_CR1_JEOCIE; ADC_CR1(adc) &= ~ADC_CR1_JEOCIE;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog Interrupt
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_awd_interrupt(u32 adc) void adc_enable_awd_interrupt(u32 adc)
{ {
ADC_CR1(adc) |= ADC_CR1_AWDIE; ADC_CR1(adc) |= ADC_CR1_AWDIE;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable Analog Watchdog Interrupt
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_awd_interrupt(u32 adc) void adc_disable_awd_interrupt(u32 adc)
{ {
ADC_CR1(adc) &= ~ADC_CR1_AWDIE; ADC_CR1(adc) &= ~ADC_CR1_AWDIE;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Enable Regular End-Of-Conversion Interrupt
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_eoc_interrupt(u32 adc) void adc_enable_eoc_interrupt(u32 adc)
{ {
ADC_CR1(adc) |= ADC_CR1_EOCIE; ADC_CR1(adc) |= ADC_CR1_EOCIE;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable Regular End-Of-Conversion Interrupt
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_eoc_interrupt(u32 adc) void adc_disable_eoc_interrupt(u32 adc)
{ {
ADC_CR1(adc) &= ~ADC_CR1_EOCIE; ADC_CR1(adc) &= ~ADC_CR1_EOCIE;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Enable The Temperature Sensor
This enables both the sensor and the reference voltage measurements on channels
16 and 17.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_temperature_sensor(u32 adc) void adc_enable_temperature_sensor(u32 adc)
{ {
ADC_CR2(adc) |= ADC_CR2_TSVREFE; ADC_CR2(adc) |= ADC_CR2_TSVREFE;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable The Temperature Sensor
Disabling this will reduce power consumption from the sensor and the reference
voltage measurements.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_temperature_sensor(u32 adc) void adc_disable_temperature_sensor(u32 adc)
{ {
ADC_CR2(adc) &= ~ADC_CR2_TSVREFE; ADC_CR2(adc) &= ~ADC_CR2_TSVREFE;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Software Triggered Conversion on Regular Channels
This starts conversion on a set of defined regular channels if the ADC trigger
is set to be a software trigger. It is cleared by hardware once conversion
starts.
Note this is a software trigger and requires triggering to be enabled and the
trigger source to be set appropriately otherwise conversion will not start.
This is not the same as the ADC start conversion operation.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_start_conversion_regular(u32 adc) void adc_start_conversion_regular(u32 adc)
{ {
/* Start conversion on regular channels. */ /* Start conversion on regular channels. */
@ -184,6 +451,20 @@ void adc_start_conversion_regular(u32 adc)
while (ADC_CR2(adc) & ADC_CR2_SWSTART); while (ADC_CR2(adc) & ADC_CR2_SWSTART);
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Software Triggered Conversion on Injected Channels
This starts conversion on a set of defined injected channels if the ADC trigger
is set to be a software trigger. It is cleared by hardware once conversion
starts.
Note this is a software trigger and requires triggering to be enabled and the
trigger source to be set appropriately otherwise conversion will not start.
This is not the same as the ADC start conversion operation.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_start_conversion_injected(u32 adc) void adc_start_conversion_injected(u32 adc)
{ {
/* Start conversion on injected channels. */ /* Start conversion on injected channels. */
@ -193,6 +474,36 @@ void adc_start_conversion_injected(u32 adc)
while (ADC_CR2(adc) & ADC_CR2_JSWSTART); while (ADC_CR2(adc) & ADC_CR2_JSWSTART);
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Enable an External Trigger for Regular Channels
This enables an external trigger for set of defined regular channels.
For ADC1 and ADC2
@li Timer 1 CC1 event
@li Timer 1 CC2 event
@li Timer 1 CC3 event
@li Timer 2 CC2 event
@li Timer 3 TRGO event
@li Timer 4 CC4 event
@li EXTI (TIM8_TRGO is also possible on some devices, see datasheet)
@li Software Start
For ADC3
@li Timer 3 CC1 event
@li Timer 2 CC3 event
@li Timer 1 CC3 event
@li Timer 8 CC1 event
@li Timer 8 TRGO event
@li Timer 5 CC1 event
@li Timer 5 CC3 event
@li Software Start
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_regular_12
for ADC1 and ADC2, or @ref adc_trigger_regular_3 for ADC3
*/
void adc_enable_external_trigger_regular(u32 adc, u32 trigger) void adc_enable_external_trigger_regular(u32 adc, u32 trigger)
{ {
u32 reg32; u32 reg32;
@ -204,11 +515,47 @@ void adc_enable_external_trigger_regular(u32 adc, u32 trigger)
ADC_CR2(adc) |= ADC_CR2_EXTTRIG; ADC_CR2(adc) |= ADC_CR2_EXTTRIG;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable an External Trigger for Regular Channels
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_external_trigger_regular(u32 adc) void adc_disable_external_trigger_regular(u32 adc)
{ {
ADC_CR2(adc) &= ~ADC_CR2_EXTTRIG; ADC_CR2(adc) &= ~ADC_CR2_EXTTRIG;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Enable an External Trigger for Injected Channels
This enables an external trigger for set of defined injected channels.
For ADC1 and ADC2
@li Timer 1 TRGO event
@li Timer 1 CC4 event
@li Timer 2 TRGO event
@li Timer 2 CC1 event
@li Timer 3 CC4 event
@li Timer 4 TRGO event
@li EXTI (TIM8 CC4 is also possible on some devices, see datasheet)
@li Software Start
For ADC3
@li Timer 1 TRGO event
@li Timer 1 CC4 event
@li Timer 4 CC3 event
@li Timer 8 CC2 event
@li Timer 8 CC4 event
@li Timer 5 TRGO event
@li Timer 5 CC4 event
@li Software Start
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected_12
for ADC1 and ADC2, or @ref adc_trigger_injected_3 for ADC3
*/
void adc_enable_external_trigger_injected(u32 adc, u32 trigger) void adc_enable_external_trigger_injected(u32 adc, u32 trigger)
{ {
u32 reg32; u32 reg32;
@ -220,65 +567,169 @@ void adc_enable_external_trigger_injected(u32 adc, u32 trigger)
ADC_CR2(adc) |= ADC_CR2_JEXTTRIG; ADC_CR2(adc) |= ADC_CR2_JEXTTRIG;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable an External Trigger for Injected Channels
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_external_trigger_injected(u32 adc) void adc_disable_external_trigger_injected(u32 adc)
{ {
ADC_CR2(adc) &= ~ADC_CR2_JEXTTRIG; ADC_CR2(adc) &= ~ADC_CR2_JEXTTRIG;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Set the Data as Left Aligned
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_set_left_aligned(u32 adc) void adc_set_left_aligned(u32 adc)
{ {
ADC_CR2(adc) |= ADC_CR2_ALIGN; ADC_CR2(adc) |= ADC_CR2_ALIGN;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Set the Data as Right Aligned
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_set_right_aligned(u32 adc) void adc_set_right_aligned(u32 adc)
{ {
ADC_CR2(adc) &= ~ADC_CR2_ALIGN; ADC_CR2(adc) &= ~ADC_CR2_ALIGN;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Enable DMA Transfers
Only available for ADC1 through DMA1 channel1, and ADC3 through DMA2 channel5.
ADC2 will use DMA if it is set as slave in dual mode with ADC1 in DMA transfer
mode.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_dma(u32 adc) void adc_enable_dma(u32 adc)
{ {
if ((adc == ADC1) | (adc == ADC3)) if ((adc == ADC1) | (adc == ADC3))
ADC_CR2(adc) |= ADC_CR2_DMA; ADC_CR2(adc) |= ADC_CR2_DMA;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable DMA Transfers
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_dma(u32 adc) void adc_disable_dma(u32 adc)
{ {
if ((adc == ADC1) | (adc == ADC3)) if ((adc == ADC1) | (adc == ADC3))
ADC_CR2(adc) &= ~ADC_CR2_DMA; ADC_CR2(adc) &= ~ADC_CR2_DMA;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Initialize Calibration Registers
This resets the calibration registers. It is not clear if this is required to be
done before every calibration operation.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_reset_calibration(u32 adc) void adc_reset_calibration(u32 adc)
{ {
ADC_CR2(adc) |= ADC_CR2_RSTCAL; ADC_CR2(adc) |= ADC_CR2_RSTCAL;
while (ADC_CR2(adc) & ADC_CR2_RSTCAL); while (ADC_CR2(adc) & ADC_CR2_RSTCAL);
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Calibration
The calibration data for the ADC is recomputed. The hardware clears the
calibration status flag when calibration is complete. This function does not return
until this happens and the ADC is ready for use.
The ADC must have been powered down for at least 2 ADC clock cycles, then powered on.
before calibration starts
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_calibration(u32 adc) void adc_calibration(u32 adc)
{ {
ADC_CR2(adc) |= ADC_CR2_CAL; ADC_CR2(adc) |= ADC_CR2_CAL;
while (ADC_CR2(adc) & ADC_CR2_CAL); while (ADC_CR2(adc) & ADC_CR2_CAL);
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Enable Continuous Conversion Mode
In this mode the ADC starts a new conversion of a single channel or a channel
group immediately following completion of the previous channel group conversion.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_set_continous_conversion_mode(u32 adc) void adc_set_continous_conversion_mode(u32 adc)
{ {
ADC_CR2(adc) |= ADC_CR2_CONT; ADC_CR2(adc) |= ADC_CR2_CONT;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Enable Single Conversion Mode
In this mode the ADC performs a conversion of one channel or a channel group
and stops.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_set_single_conversion_mode(u32 adc) void adc_set_single_conversion_mode(u32 adc)
{ {
ADC_CR2(adc) &= ~ADC_CR2_CONT; ADC_CR2(adc) &= ~ADC_CR2_CONT;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Power On
If the ADC is in power-down mode then it is powered up. The application needs
to wait a time of about 3 microseconds for stabilization before using the ADC.
If the ADC is already on this function call will initiate a conversion.
@todo fix this.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_on(u32 adc) void adc_on(u32 adc)
{ {
ADC_CR2(adc) |= ADC_CR2_ADON; ADC_CR2(adc) |= ADC_CR2_ADON;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Off
Turn off the ADC to reduce power consumption to a few microamps.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_off(u32 adc) void adc_off(u32 adc)
{ {
ADC_CR2(adc) &= ~ADC_CR2_ADON; ADC_CR2(adc) &= ~ADC_CR2_ADON;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Set the Sample Time for a Single Channel
The sampling time can be selected in ADC clock cycles from 1.5 to 239.5.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref adc_channel
@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
*/
void adc_set_conversion_time(u32 adc, u8 channel, u8 time) void adc_set_conversion_time(u32 adc, u8 channel, u8 time)
{ {
u32 reg32; u32 reg32;
@ -296,6 +747,16 @@ void adc_set_conversion_time(u32 adc, u8 channel, u8 time)
} }
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Set the Sample Time for All Channels
The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same for
all channels.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
*/
void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) void adc_set_conversion_time_on_all_channels(u32 adc, u8 time)
{ {
u8 i; u8 i;
@ -310,6 +771,13 @@ void adc_set_conversion_time_on_all_channels(u32 adc, u8 time)
ADC_SMPR1(adc) = reg32; ADC_SMPR1(adc) = reg32;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Set Analog Watchdog Upper Threshold
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] threshold Unsigned int8. Upper threshold value
*/
void adc_set_watchdog_high_threshold(u32 adc, u16 threshold) void adc_set_watchdog_high_threshold(u32 adc, u16 threshold)
{ {
u32 reg32 = 0; u32 reg32 = 0;
@ -319,6 +787,13 @@ void adc_set_watchdog_high_threshold(u32 adc, u16 threshold)
ADC_HTR(adc) = reg32; ADC_HTR(adc) = reg32;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Set Analog Watchdog Lower Threshold
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] threshold Unsigned int8. Lower threshold value
*/
void adc_set_watchdog_low_threshold(u32 adc, u16 threshold) void adc_set_watchdog_low_threshold(u32 adc, u16 threshold)
{ {
u32 reg32 = 0; u32 reg32 = 0;
@ -328,6 +803,18 @@ void adc_set_watchdog_low_threshold(u32 adc, u16 threshold)
ADC_LTR(adc) = reg32; ADC_LTR(adc) = reg32;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Set a Regular Channel Conversion Sequence
Define a sequence of channels to be converted as a regular group with a length
from 1 to 16 channels. If this is called during conversion, the current conversion
is reset and conversion begins again with the newly defined group.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] length Unsigned int8. Number of channels in the group.
@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18.
*/
void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]) void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[])
{ {
u32 reg32_1 = 0, reg32_2 = 0, reg32_3 = 0; u32 reg32_1 = 0, reg32_2 = 0, reg32_3 = 0;
@ -352,6 +839,18 @@ void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[])
ADC_SQR3(adc) = reg32_3; ADC_SQR3(adc) = reg32_3;
} }
/*-----------------------------------------------------------------------------*/
/** @brief ADC Set an Injected Channel Conversion Sequence
Defines a sequence of channels to be converted as an injected group with a length
from 1 to 4 channels. If this is called during conversion, the current conversion
is reset and conversion begins again with the newly defined group.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] length Unsigned int8. Number of channels in the group.
@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18
*/
void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]) void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[])
{ {
u32 reg32 = 0; u32 reg32 = 0;
@ -368,3 +867,6 @@ void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[])
ADC_JSQR(adc) = reg32; ADC_JSQR(adc) = reg32;
} }
/**@}*/

4
lib/stm32/iwdg.c
View File

@ -1,6 +1,6 @@
/** @defgroup STM32F-iwdg-file IWDG /** @defgroup STM32F_iwdg_file IWDG
@ingroup STM32F-files @ingroup STM32F_files
@brief <b>libopencm3 STM32F1xx Independent Watchdog Timer</b> @brief <b>libopencm3 STM32F1xx Independent Watchdog Timer</b>

4
lib/stm32/nvic.c
View File

@ -1,6 +1,6 @@
/** @defgroup STM32F-nvic-file NVIC /** @defgroup STM32F_nvic_file NVIC
@ingroup STM32F-files @ingroup STM32F_files
@brief <b>libopencm3 STM32F Nested Vectored Interrupt Controller</b> @brief <b>libopencm3 STM32F Nested Vectored Interrupt Controller</b>

4
lib/stm32/systick.c
View File

@ -1,6 +1,6 @@
/** @defgroup STM32F-systick-file SysTick /** @defgroup STM32F_systick_file SysTick
@ingroup STM32F-files @ingroup STM32F_files
@brief <b>libopencm3 STM32Fxx System Tick Timer</b> @brief <b>libopencm3 STM32Fxx System Tick Timer</b>

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