[Style] Stylefix sweep over the whole codebase.

9 years ago · b1049f9a6f
39 changed files with 445 additions and 359 deletions
--- a/include/libopencm3/lm4f/ssi.h
+++ b/include/libopencm3/lm4f/ssi.h
@ -1,16 +1,16 @@
 /** @defgroup ssi_defines Synchronous Serial Interface
- * 
+ *
 * @brief <b>Defined Constants and Types for the LM4F Synchronous Serial Interface (SSI)</b>
- * 
+ *
 * @ingroup LM4Fxx_defines
- * 
+ *
 * @version 1.0.0
- * 
+ *
 * @author @htmlonly &copy; @endhtmlonly 2014
 * Tiago Costa <nippius+github@gmail.com>
- * 
+ *
 * @date 11 June 2014
- * 
+ *
 * LGPL License Terms @ref lgpl_license
 */

@ -67,7 +67,7 @@

 /* SSI Satus */
 #define SSI_SR(port)		MMIO32((port) + 0x00C)
- 
+
 /* SSI Clock Prescale */
 #define SSI_CPSR(port)		MMIO32((port) + 0x010)

@ -84,7 +84,7 @@
 #define SSI_ICR(port)		MMIO32((port) + 0x020)

 /* SSI DMA Control */
-#define SSI_DMACTL(port) 	MMIO32((port) + 0x024)
+#define SSI_DMACTL(port)	MMIO32((port) + 0x024)

 /* SSI Clock Configuration */
 #define SSI_CC(port)		MMIO32((port) + 0xFC8)
@ -115,4 +115,4 @@ END_DECLS
 /**@}*/

 #endif	/* LM4F_SSI_H */
- 
+
--- a/include/libopencm3/sam/3s/smc.h
+++ b/include/libopencm3/sam/3s/smc.h
@ -33,16 +33,20 @@
 /* --- Static Memory Controller (SMC) registers ---------------------------- */

 /* Setup Register */
-#define SMC_SETUP(CS_number)		MMIO32(SMC_BASE + 0x10*(CS_number) + 0x00)
+#define SMC_SETUP(CS_number)		MMIO32(SMC_BASE + 0x10*(CS_number) \
+						+ 0x00)

 /* Pulse Register */
-#define SMC_PULSE(CS_number)		MMIO32(SMC_BASE + 0x10*(CS_number) + 0x04)
+#define SMC_PULSE(CS_number)		MMIO32(SMC_BASE + 0x10*(CS_number) \
+						+ 0x04)

 /* Cycle Register */
-#define SMC_CYCLE(CS_number)		MMIO32(SMC_BASE + 0x10*(CS_number) + 0x08)
+#define SMC_CYCLE(CS_number)		MMIO32(SMC_BASE + 0x10*(CS_number) \
+						+ 0x08)

 /* Mode Register */
-#define SMC_MODE(CS_number)		MMIO32(SMC_BASE + 0x10*(CS_number) + 0x0C)
+#define SMC_MODE(CS_number)		MMIO32(SMC_BASE + 0x10*(CS_number) \
+						+ 0x0C)

 /* Off Chip Memory Scrambling Mode Register */
 #define SMC_OCMS			MMIO32(SMC_BASE + 0x80)
--- a/include/libopencm3/sam/common/smc_common_3a3u3x.h
+++ b/include/libopencm3/sam/common/smc_common_3a3u3x.h
@ -117,19 +117,24 @@
 #define SMC_ECC_PR15			MMIO32(SMC_BASE + 0x6C)

 /* Setup Register */
-#define SMC_SETUP(CS_number)		MMIO32(SMC_BASE + 0x14*(CS_number) + 0x70)
+#define SMC_SETUP(CS_number)		MMIO32(SMC_BASE + 0x14*(CS_number) \
+						+ 0x70)

 /* Pulse Register */
-#define SMC_PULSE(CS_number)		MMIO32(SMC_BASE + 0x14*(CS_number) + 0x74)
+#define SMC_PULSE(CS_number)		MMIO32(SMC_BASE + 0x14*(CS_number) \
+						+ 0x74)

 /* Cycle Register */
-#define SMC_CYCLE(CS_number)		MMIO32(SMC_BASE + 0x14*(CS_number) + 0x78)
+#define SMC_CYCLE(CS_number)		MMIO32(SMC_BASE + 0x14*(CS_number) \
+						+ 0x78)

 /* Timings Register */
-#define SMC_TIMINGS(CS_number)		MMIO32(SMC_BASE + 0x14*(CS_number) + 0x7C)
+#define SMC_TIMINGS(CS_number)		MMIO32(SMC_BASE + 0x14*(CS_number) \
+						+ 0x7C)

 /* Mode Register */
-#define SMC_MODE(CS_number)		MMIO32(SMC_BASE + 0x14*(CS_number) + 0x80)
+#define SMC_MODE(CS_number)		MMIO32(SMC_BASE + 0x14*(CS_number) \
+						+ 0x80)

 /* Off Chip Memory Scrambling Mode Register */
 #define SMC_OCMS			MMIO32(SMC_BASE + 0x110)
@ -374,10 +379,14 @@
 #define SMC_ECC_MD_ECC_PAGESIZE_MASK	(0x03 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)

 /* ECC Page Size Values */
-#define SMC_ECC_MD_ECC_PAGESIZE_PS512_16	(0x00 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)
-#define SMC_ECC_MD_ECC_PAGESIZE_PS1024_32	(0x01 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)
-#define SMC_ECC_MD_ECC_PAGESIZE_PS2048_64	(0x02 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)
-#define SMC_ECC_MD_ECC_PAGESIZE_PS4096_128	(0x03 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)
+#define SMC_ECC_MD_ECC_PAGESIZE_PS512_16	\
+	(0x00 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)
+#define SMC_ECC_MD_ECC_PAGESIZE_PS1024_32	\
+	(0x01 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)
+#define SMC_ECC_MD_ECC_PAGESIZE_PS2048_64	\
+	(0x02 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)
+#define SMC_ECC_MD_ECC_PAGESIZE_PS4096_128	\
+	(0x03 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)


 /* --- SMC ECC Status Register 1 (SMC_ECC_SR1) ----------------------------- */
--- a/include/libopencm3/stm32/f4/fmc.h
+++ b/include/libopencm3/stm32/f4/fmc.h
@ -144,10 +144,10 @@ error "This file should not be included directly, it is included with fsmc.h"
 * out those bits after you have computed values for CR2 and
 * TR2 and put them into CR1 and TR1
 */
-#define FMC_SDTR_DNC_MASK	( FMC_SDTR_TRP_MASK| FMC_SDTR_TRC_MASK )
-#define FMC_SDCR_DNC_MASK	( FMC_SDCR_SDCLK_MASK |\
-				  FMC_SDCR_RPIPE_MASK  |\
-				  FMC_SDCR_RBURST )
+#define FMC_SDTR_DNC_MASK	(FMC_SDTR_TRP_MASK | FMC_SDTR_TRC_MASK)
+#define FMC_SDCR_DNC_MASK	(FMC_SDCR_SDCLK_MASK | \
+				 FMC_SDCR_RPIPE_MASK  | \
+				 FMC_SDCR_RBURST)

 /* --- FMC_SDCMR values --------------------------------------------------- */

@ -240,7 +240,9 @@ enum fmc_sdram_command { SDRAM_CLK_CONF, SDRAM_NORMAL, SDRAM_PALL,
 			 SDRAM_AUTO_REFRESH, SDRAM_LOAD_MODE,
 			 SDRAM_SELF_REFRESH, SDRAM_POWER_DOWN };

-/* Send an array of timing parameters (indices above) to create SDTR register value */
+/* Send an array of timing parameters (indices above) to create SDTR register
+ * value
+ */
 uint32_t sdram_timing(struct sdram_timing *t);
 void sdram_command(enum fmc_sdram_bank bank, enum fmc_sdram_command cmd,
 			int autorefresh, int modereg);
--- a/include/libopencm3/stm32/f7/memorymap.h
+++ b/include/libopencm3/stm32/f7/memorymap.h
@ -74,12 +74,12 @@
 #define USART1_BASE			(PERIPH_BASE_APB2 + 0x1000)
 #define USART6_BASE			(PERIPH_BASE_APB2 + 0x1400)
 /* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */
-#define ADC1_BASE			(PERIPH_BASE_APB2 + 0x2000)	/* TODO */
-#define ADC2_BASE			(PERIPH_BASE_APB2 + 0x2100)	/* TODO */
-#define ADC3_BASE			(PERIPH_BASE_APB2 + 0x2200)	/* TODO */
-#define ADC_COMMON_BASE			(PERIPH_BASE_APB2 + 0x2300)	/* TODO */
+#define ADC1_BASE			(PERIPH_BASE_APB2 + 0x2000) /* TODO */
+#define ADC2_BASE			(PERIPH_BASE_APB2 + 0x2100) /* TODO */
+#define ADC3_BASE			(PERIPH_BASE_APB2 + 0x2200) /* TODO */
+#define ADC_COMMON_BASE			(PERIPH_BASE_APB2 + 0x2300) /* TODO */
 /* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */
-#define SDIO_BASE			(PERIPH_BASE_APB2 + 0x2C00)	/* SDMMC */
+#define SDIO_BASE			(PERIPH_BASE_APB2 + 0x2C00) /* SDMMC */
 /* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */
 #define SPI1_BASE			(PERIPH_BASE_APB2 + 0x3000)
 #define SPI4_BASE			(PERIPH_BASE_APB2 + 0x3400)
--- a/include/libopencm3/stm32/l4/rcc.h
+++ b/include/libopencm3/stm32/l4/rcc.h
@ -766,7 +766,7 @@ enum rcc_periph_clken {
 	SCC_FLASH = _REG_BIT(RCC_AHB1SMENR_OFFSET, 8),
 	SCC_DMA2 = _REG_BIT(RCC_AHB1SMENR_OFFSET, 1),
 	SCC_DMA1 = _REG_BIT(RCC_AHB1SMENR_OFFSET, 0),
-	
+
 	/* AHB2 peripherals in sleep mode */
 	SCC_RNG = _REG_BIT(RCC_AHB2SMENR_OFFSET, 18),
 	SCC_AES = _REG_BIT(RCC_AHB2SMENR_OFFSET, 16),
@ -895,7 +895,7 @@ enum rcc_periph_rst {
 	RST_TIM1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 11),
 	RST_SDMMC1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 10),
 	RST_SYSCFG = _REG_BIT(RCC_APB2RSTR_OFFSET, 0),
-	
+
 };
 #include <libopencm3/stm32/common/rcc_common_all.h>

--- a/include/libopencm3/stm32/otg_common.h
+++ b/include/libopencm3/stm32/otg_common.h
@ -443,12 +443,12 @@
 #define OTG_HCINT_FRMOR		(1 << 9)
 #define OTG_HCINT_BBERR		(1 << 8)
 #define OTG_HCINT_TXERR		(1 << 7)
-// Note: OTG_HCINT_NYET: Only in OTG_HS
+/* Note: OTG_HCINT_NYET: Only in OTG_HS */
 #define OTG_HCINT_NYET		(1 << 6)
 #define OTG_HCINT_ACK		(1 << 5)
 #define OTG_HCINT_NAK		(1 << 4)
 #define OTG_HCINT_STALL		(1 << 3)
-// Note: OTG_HCINT_AHBERR: Only in OTG_HS
+/* Note: OTG_HCINT_AHBERR: Only in OTG_HS */
 #define OTG_HCINT_AHBERR	(1 << 2)
 #define OTG_HCINT_CHH		(1 << 1)
 #define OTG_HCINT_XFRC		(1 << 0)
@ -459,18 +459,18 @@
 #define OTG_HCINTMSK_FRMORM		(1 << 9)
 #define OTG_HCINTMSK_BBERRM		(1 << 8)
 #define OTG_HCINTMSK_TXERRM		(1 << 7)
-// Note: OTG_HCINTMSK_NYET: Only in OTG_HS
+/* Note: OTG_HCINTMSK_NYET: Only in OTG_HS */
 #define OTG_HCINTMSK_NYET		(1 << 6)
 #define OTG_HCINTMSK_ACKM		(1 << 5)
 #define OTG_HCINTMSK_NAKM		(1 << 4)
 #define OTG_HCINTMSK_STALLM		(1 << 3)
-// Note: OTG_HCINTMSK_AHBERR: Only in OTG_HS
+/* Note: OTG_HCINTMSK_AHBERR: Only in OTG_HS */
 #define OTG_HCINTMSK_AHBERR		(1 << 2)
 #define OTG_HCINTMSK_CHHM		(1 << 1)
 #define OTG_HCINTMSK_XFRCM		(1 << 0)

 /* OTG Host channel-x transfer size register (OTG_HCTSIZx) */
-// Note: OTG_HCTSIZ_DOPING: Only in OTG_HS
+/* Note: OTG_HCTSIZ_DOPING: Only in OTG_HS */
 #define OTG_HCTSIZ_DOPING	(1 << 31)
 #define OTG_HCTSIZ_DPID_DATA0	(0x0 << 29)
 #define OTG_HCTSIZ_DPID_DATA1	(0x2 << 29)
--- a/include/libopencm3/stm32/otg_fs.h
+++ b/include/libopencm3/stm32/otg_fs.h
@ -32,67 +32,67 @@
 /***********************************************************************/

 /* Core Global Control and Status Registers */
-#define OTG_FS_GOTGCTL			MMIO32(USB_OTG_FS_BASE + OTG_GOTGCTL)
-#define OTG_FS_GOTGINT			MMIO32(USB_OTG_FS_BASE + OTG_GOTGINT)
-#define OTG_FS_GAHBCFG			MMIO32(USB_OTG_FS_BASE + OTG_GAHBCFG)
-#define OTG_FS_GUSBCFG			MMIO32(USB_OTG_FS_BASE + OTG_GUSBCFG)
-#define OTG_FS_GRSTCTL			MMIO32(USB_OTG_FS_BASE + OTG_GRSTCTL)
-#define OTG_FS_GINTSTS			MMIO32(USB_OTG_FS_BASE + OTG_GINTSTS)
-#define OTG_FS_GINTMSK			MMIO32(USB_OTG_FS_BASE + OTG_GINTMSK)
-#define OTG_FS_GRXSTSR			MMIO32(USB_OTG_FS_BASE + OTG_GRXSTSR)
-#define OTG_FS_GRXSTSP			MMIO32(USB_OTG_FS_BASE + OTG_GRXSTSP)
-#define OTG_FS_GRXFSIZ			MMIO32(USB_OTG_FS_BASE + OTG_GRXFSIZ)
-#define OTG_FS_GNPTXFSIZ		MMIO32(USB_OTG_FS_BASE + OTG_GNPTXFSIZ)
-#define OTG_FS_GNPTXSTS			MMIO32(USB_OTG_FS_BASE + OTG_GNPTXSTS)
-#define OTG_FS_GCCFG			MMIO32(USB_OTG_FS_BASE + OTG_GCCFG)
-#define OTG_FS_CID			MMIO32(USB_OTG_FS_BASE + OTG_CID)
-#define OTG_FS_HPTXFSIZ			MMIO32(USB_OTG_FS_BASE + OTG_HPTXFSIZ)
-#define OTG_FS_DIEPTXF(x)		MMIO32(USB_OTG_FS_BASE + OTG_DIEPTXF(x))
+#define OTG_FS_GOTGCTL		MMIO32(USB_OTG_FS_BASE + OTG_GOTGCTL)
+#define OTG_FS_GOTGINT		MMIO32(USB_OTG_FS_BASE + OTG_GOTGINT)
+#define OTG_FS_GAHBCFG		MMIO32(USB_OTG_FS_BASE + OTG_GAHBCFG)
+#define OTG_FS_GUSBCFG		MMIO32(USB_OTG_FS_BASE + OTG_GUSBCFG)
+#define OTG_FS_GRSTCTL		MMIO32(USB_OTG_FS_BASE + OTG_GRSTCTL)
+#define OTG_FS_GINTSTS		MMIO32(USB_OTG_FS_BASE + OTG_GINTSTS)
+#define OTG_FS_GINTMSK		MMIO32(USB_OTG_FS_BASE + OTG_GINTMSK)
+#define OTG_FS_GRXSTSR		MMIO32(USB_OTG_FS_BASE + OTG_GRXSTSR)
+#define OTG_FS_GRXSTSP		MMIO32(USB_OTG_FS_BASE + OTG_GRXSTSP)
+#define OTG_FS_GRXFSIZ		MMIO32(USB_OTG_FS_BASE + OTG_GRXFSIZ)
+#define OTG_FS_GNPTXFSIZ	MMIO32(USB_OTG_FS_BASE + OTG_GNPTXFSIZ)
+#define OTG_FS_GNPTXSTS		MMIO32(USB_OTG_FS_BASE + OTG_GNPTXSTS)
+#define OTG_FS_GCCFG		MMIO32(USB_OTG_FS_BASE + OTG_GCCFG)
+#define OTG_FS_CID		MMIO32(USB_OTG_FS_BASE + OTG_CID)
+#define OTG_FS_HPTXFSIZ		MMIO32(USB_OTG_FS_BASE + OTG_HPTXFSIZ)
+#define OTG_FS_DIEPTXF(x)	MMIO32(USB_OTG_FS_BASE + OTG_DIEPTXF(x))


 /* Host-mode Control and Status Registers */
-#define OTG_FS_HCFG			MMIO32(USB_OTG_FS_BASE + OTG_HCFG)
-#define OTG_FS_HFIR			MMIO32(USB_OTG_FS_BASE + OTG_HFIR)
-#define OTG_FS_HFNUM			MMIO32(USB_OTG_FS_BASE + OTG_HFNUM)
-#define OTG_FS_HPTXSTS			MMIO32(USB_OTG_FS_BASE + OTG_HPTXSTS)
-#define OTG_FS_HAINT			MMIO32(USB_OTG_FS_BASE + OTG_HAINT)
-#define OTG_FS_HAINTMSK			MMIO32(USB_OTG_FS_BASE + OTG_HAINTMSK)
-#define OTG_FS_HPRT			MMIO32(USB_OTG_FS_BASE + OTG_HPRT)
-#define OTG_FS_HCCHAR(x)		MMIO32(USB_OTG_FS_BASE + OTG_HCCHAR(x))
-#define OTG_FS_HCINT(x)			MMIO32(USB_OTG_FS_BASE + OTG_HCINT(x))
-#define OTG_FS_HCINTMSK(x)		MMIO32(USB_OTG_FS_BASE + OTG_HCINTMSK(x))
-#define OTG_FS_HCTSIZ(x)		MMIO32(USB_OTG_FS_BASE + OTG_HCTSIZ(x))
+#define OTG_FS_HCFG		MMIO32(USB_OTG_FS_BASE + OTG_HCFG)
+#define OTG_FS_HFIR		MMIO32(USB_OTG_FS_BASE + OTG_HFIR)
+#define OTG_FS_HFNUM		MMIO32(USB_OTG_FS_BASE + OTG_HFNUM)
+#define OTG_FS_HPTXSTS		MMIO32(USB_OTG_FS_BASE + OTG_HPTXSTS)
+#define OTG_FS_HAINT		MMIO32(USB_OTG_FS_BASE + OTG_HAINT)
+#define OTG_FS_HAINTMSK		MMIO32(USB_OTG_FS_BASE + OTG_HAINTMSK)
+#define OTG_FS_HPRT		MMIO32(USB_OTG_FS_BASE + OTG_HPRT)
+#define OTG_FS_HCCHAR(x)	MMIO32(USB_OTG_FS_BASE + OTG_HCCHAR(x))
+#define OTG_FS_HCINT(x)		MMIO32(USB_OTG_FS_BASE + OTG_HCINT(x))
+#define OTG_FS_HCINTMSK(x)	MMIO32(USB_OTG_FS_BASE + OTG_HCINTMSK(x))
+#define OTG_FS_HCTSIZ(x)	MMIO32(USB_OTG_FS_BASE + OTG_HCTSIZ(x))

 /* Device-mode Control and Status Registers */
-#define OTG_FS_DCFG			MMIO32(USB_OTG_FS_BASE + OTG_DCFG)
-#define OTG_FS_DCTL			MMIO32(USB_OTG_FS_BASE + OTG_DCTL)
-#define OTG_FS_DSTS			MMIO32(USB_OTG_FS_BASE + OTG_DSTS)
-#define OTG_FS_DIEPMSK			MMIO32(USB_OTG_FS_BASE + OTG_DIEPMSK)
-#define OTG_FS_DOEPMSK			MMIO32(USB_OTG_FS_BASE + OTG_DOEPMSK)
-#define OTG_FS_DAINT			MMIO32(USB_OTG_FS_BASE + OTG_DAINT)
-#define OTG_FS_DAINTMSK			MMIO32(USB_OTG_FS_BASE + OTG_DAINTMSK)
-#define OTG_FS_DVBUSDIS			MMIO32(USB_OTG_FS_BASE + OTG_DVBUSDIS)
-#define OTG_FS_DVBUSPULSE		MMIO32(USB_OTG_FS_BASE + OTG_DVBUSPULSE)
-#define OTG_FS_DIEPEMPMSK		MMIO32(USB_OTG_FS_BASE + OTG_DIEPEMPMSK)
-#define OTG_FS_DIEPCTL0			MMIO32(USB_OTG_FS_BASE + OTG_DIEPCTL0)
-#define OTG_FS_DIEPCTL(x)		MMIO32(USB_OTG_FS_BASE + OTG_DIEPCTL(x))
-#define OTG_FS_DOEPCTL0			MMIO32(USB_OTG_FS_BASE + OTG_DOEPCTL0)
-#define OTG_FS_DOEPCTL(x)		MMIO32(USB_OTG_FS_BASE + OTG_DOEPCTL(x))
-#define OTG_FS_DIEPINT(x)		MMIO32(USB_OTG_FS_BASE + OTG_DIEPINT(x))
-#define OTG_FS_DOEPINT(x)		MMIO32(USB_OTG_FS_BASE + OTG_DOEPINT(x))
-#define OTG_FS_DIEPTSIZ0		MMIO32(USB_OTG_FS_BASE + OTG_DIEPTSIZ0)
-#define OTG_FS_DOEPTSIZ0		MMIO32(USB_OTG_FS_BASE + OTG_DOEPTSIZ0)
-#define OTG_FS_DIEPTSIZ(x)		MMIO32(USB_OTG_FS_BASE + OTG_DIEPTSIZ(x))
-#define OTG_FS_DTXFSTS(x)		MMIO32(USB_OTG_FS_BASE + OTG_DTXFSTS(x))
-#define OTG_FS_DOEPTSIZ(x)		MMIO32(USB_OTG_FS_BASE + OTG_DOEPTSIZ(x))
+#define OTG_FS_DCFG		MMIO32(USB_OTG_FS_BASE + OTG_DCFG)
+#define OTG_FS_DCTL		MMIO32(USB_OTG_FS_BASE + OTG_DCTL)
+#define OTG_FS_DSTS		MMIO32(USB_OTG_FS_BASE + OTG_DSTS)
+#define OTG_FS_DIEPMSK		MMIO32(USB_OTG_FS_BASE + OTG_DIEPMSK)
+#define OTG_FS_DOEPMSK		MMIO32(USB_OTG_FS_BASE + OTG_DOEPMSK)
+#define OTG_FS_DAINT		MMIO32(USB_OTG_FS_BASE + OTG_DAINT)
+#define OTG_FS_DAINTMSK		MMIO32(USB_OTG_FS_BASE + OTG_DAINTMSK)
+#define OTG_FS_DVBUSDIS		MMIO32(USB_OTG_FS_BASE + OTG_DVBUSDIS)
+#define OTG_FS_DVBUSPULSE	MMIO32(USB_OTG_FS_BASE + OTG_DVBUSPULSE)
+#define OTG_FS_DIEPEMPMSK	MMIO32(USB_OTG_FS_BASE + OTG_DIEPEMPMSK)
+#define OTG_FS_DIEPCTL0		MMIO32(USB_OTG_FS_BASE + OTG_DIEPCTL0)
+#define OTG_FS_DIEPCTL(x)	MMIO32(USB_OTG_FS_BASE + OTG_DIEPCTL(x))
+#define OTG_FS_DOEPCTL0		MMIO32(USB_OTG_FS_BASE + OTG_DOEPCTL0)
+#define OTG_FS_DOEPCTL(x)	MMIO32(USB_OTG_FS_BASE + OTG_DOEPCTL(x))
+#define OTG_FS_DIEPINT(x)	MMIO32(USB_OTG_FS_BASE + OTG_DIEPINT(x))
+#define OTG_FS_DOEPINT(x)	MMIO32(USB_OTG_FS_BASE + OTG_DOEPINT(x))
+#define OTG_FS_DIEPTSIZ0	MMIO32(USB_OTG_FS_BASE + OTG_DIEPTSIZ0)
+#define OTG_FS_DOEPTSIZ0	MMIO32(USB_OTG_FS_BASE + OTG_DOEPTSIZ0)
+#define OTG_FS_DIEPTSIZ(x)	MMIO32(USB_OTG_FS_BASE + OTG_DIEPTSIZ(x))
+#define OTG_FS_DTXFSTS(x)	MMIO32(USB_OTG_FS_BASE + OTG_DTXFSTS(x))
+#define OTG_FS_DOEPTSIZ(x)	MMIO32(USB_OTG_FS_BASE + OTG_DOEPTSIZ(x))

 /* Power and clock gating control and status register */
-#define OTG_FS_PCGCCTL			MMIO32(USB_OTG_FS_BASE + OTG_PCGCCTL)
+#define OTG_FS_PCGCCTL		MMIO32(USB_OTG_FS_BASE + OTG_PCGCCTL)

 /* Data FIFO */
-#define OTG_FS_FIFO(x)			(&MMIO32(USB_OTG_FS_BASE \
-							      + (((x) + 1) \
-								 << 12)))
+#define OTG_FS_FIFO(x)		(&MMIO32(USB_OTG_FS_BASE \
+						      + (((x) + 1) \
+							 << 12)))


 #endif
--- a/include/libopencm3/stm32/otg_hs.h
+++ b/include/libopencm3/stm32/otg_hs.h
@ -27,84 +27,84 @@
 /* OTG_HS specific registers */

 /* Host-mode Control and Status Registers */
-#define OTG_HCSPLT(x)			(0x504 + 0x20*(x))
-#define OTG_HCDMA(x)			(0x514 + 0x20*(x))
+#define OTG_HCSPLT(x)		(0x504 + 0x20*(x))
+#define OTG_HCDMA(x)		(0x514 + 0x20*(x))

 /* Device-mode Control and Status Registers */
-#define OTG_DEACHHINT			0x838
-#define OTG_DEACHHINTMSK			0x83C
-#define OTG_DIEPEACHMSK1		0x844
-#define OTG_DOEPEACHMSK1		0x884
-#define OTG_DIEPDMA(x)			(0x914 + 0x20*(x))
-#define OTG_DOEPDMA(x)			(0xB14 + 0x20*(x))
+#define OTG_DEACHHINT		0x838
+#define OTG_DEACHHINTMSK	0x83C
+#define OTG_DIEPEACHMSK1	0x844
+#define OTG_DOEPEACHMSK1	0x884
+#define OTG_DIEPDMA(x)		(0x914 + 0x20*(x))
+#define OTG_DOEPDMA(x)		(0xB14 + 0x20*(x))



 /***********************************************************************/

 /* Core Global Control and Status Registers */
-#define OTG_HS_GOTGCTL			MMIO32(USB_OTG_HS_BASE + OTG_GOTGCTL)
-#define OTG_HS_GOTGINT			MMIO32(USB_OTG_HS_BASE + OTG_GOTGINT)
-#define OTG_HS_GAHBCFG			MMIO32(USB_OTG_HS_BASE + OTG_GAHBCFG)
-#define OTG_HS_GUSBCFG			MMIO32(USB_OTG_HS_BASE + OTG_GUSBCFG)
-#define OTG_HS_GRSTCTL			MMIO32(USB_OTG_HS_BASE + OTG_GRSTCTL)
-#define OTG_HS_GINTSTS			MMIO32(USB_OTG_HS_BASE + OTG_GINTSTS)
-#define OTG_HS_GINTMSK			MMIO32(USB_OTG_HS_BASE + OTG_GINTMSK)
-#define OTG_HS_GRXSTSR			MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSR)
-#define OTG_HS_GRXSTSP			MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSP)
-#define OTG_HS_GRXFSIZ			MMIO32(USB_OTG_HS_BASE + OTG_GRXFSIZ)
-#define OTG_HS_GNPTXFSIZ		MMIO32(USB_OTG_HS_BASE + OTG_GNPTXFSIZ)
-#define OTG_HS_GNPTXSTS			MMIO32(USB_OTG_HS_BASE + OTG_GNPTXSTS)
-#define OTG_HS_GCCFG			MMIO32(USB_OTG_HS_BASE + OTG_GCCFG)
-#define OTG_HS_CID			MMIO32(USB_OTG_HS_BASE + OTG_CID)
-#define OTG_HS_HPTXFSIZ			MMIO32(USB_OTG_HS_BASE + OTG_HPTXFSIZ)
-#define OTG_HS_DIEPTXF(x)		MMIO32(USB_OTG_HS_BASE + OTG_DIEPTXF(x))
+#define OTG_HS_GOTGCTL		MMIO32(USB_OTG_HS_BASE + OTG_GOTGCTL)
+#define OTG_HS_GOTGINT		MMIO32(USB_OTG_HS_BASE + OTG_GOTGINT)
+#define OTG_HS_GAHBCFG		MMIO32(USB_OTG_HS_BASE + OTG_GAHBCFG)
+#define OTG_HS_GUSBCFG		MMIO32(USB_OTG_HS_BASE + OTG_GUSBCFG)
+#define OTG_HS_GRSTCTL		MMIO32(USB_OTG_HS_BASE + OTG_GRSTCTL)
+#define OTG_HS_GINTSTS		MMIO32(USB_OTG_HS_BASE + OTG_GINTSTS)
+#define OTG_HS_GINTMSK		MMIO32(USB_OTG_HS_BASE + OTG_GINTMSK)
+#define OTG_HS_GRXSTSR		MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSR)
+#define OTG_HS_GRXSTSP		MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSP)
+#define OTG_HS_GRXFSIZ		MMIO32(USB_OTG_HS_BASE + OTG_GRXFSIZ)
+#define OTG_HS_GNPTXFSIZ	MMIO32(USB_OTG_HS_BASE + OTG_GNPTXFSIZ)
+#define OTG_HS_GNPTXSTS		MMIO32(USB_OTG_HS_BASE + OTG_GNPTXSTS)
+#define OTG_HS_GCCFG		MMIO32(USB_OTG_HS_BASE + OTG_GCCFG)
+#define OTG_HS_CID		MMIO32(USB_OTG_HS_BASE + OTG_CID)
+#define OTG_HS_HPTXFSIZ		MMIO32(USB_OTG_HS_BASE + OTG_HPTXFSIZ)
+#define OTG_HS_DIEPTXF(x)	MMIO32(USB_OTG_HS_BASE + OTG_DIEPTXF(x))

 /* Host-mode Control and Status Registers */
-#define OTG_HS_HCFG			MMIO32(USB_OTG_HS_BASE + OTG_HCFG)
-#define OTG_HS_HFIR			MMIO32(USB_OTG_HS_BASE + OTG_HFIR)
-#define OTG_HS_HFNUM			MMIO32(USB_OTG_HS_BASE + OTG_HFNUM)
-#define OTG_HS_HPTXSTS			MMIO32(USB_OTG_HS_BASE + OTG_HPTXSTS)
-#define OTG_HS_HAINT			MMIO32(USB_OTG_HS_BASE + OTG_HAINT)
-#define OTG_HS_HAINTMSK			MMIO32(USB_OTG_HS_BASE + OTG_HAINTMSK)
-#define OTG_HS_HPRT			MMIO32(USB_OTG_HS_BASE + OTG_HPRT)
-#define OTG_HS_HCCHAR(x)		MMIO32(USB_OTG_HS_BASE + OTG_HCCHAR(x))
-#define OTG_HS_HCSPLT(x) 		MMIO32(USB_OTG_HS_BASE + OTG_HCSPLT(x))
-#define OTG_HS_HCINT(x)			MMIO32(USB_OTG_HS_BASE + OTG_HCINT(x))
-#define OTG_HS_HCINTMSK(x)		MMIO32(USB_OTG_HS_BASE + OTG_HCINTMSK(x))
-#define OTG_HS_HCTSIZ(x)		MMIO32(USB_OTG_HS_BASE + OTG_HCTSIZ(x))
-#define OTG_HS_HCDMA(x)			MMIO32(USB_OTG_HS_BASE + OTG_HCDMA(x))
+#define OTG_HS_HCFG		MMIO32(USB_OTG_HS_BASE + OTG_HCFG)
+#define OTG_HS_HFIR		MMIO32(USB_OTG_HS_BASE + OTG_HFIR)
+#define OTG_HS_HFNUM		MMIO32(USB_OTG_HS_BASE + OTG_HFNUM)
+#define OTG_HS_HPTXSTS		MMIO32(USB_OTG_HS_BASE + OTG_HPTXSTS)
+#define OTG_HS_HAINT		MMIO32(USB_OTG_HS_BASE + OTG_HAINT)
+#define OTG_HS_HAINTMSK		MMIO32(USB_OTG_HS_BASE + OTG_HAINTMSK)
+#define OTG_HS_HPRT		MMIO32(USB_OTG_HS_BASE + OTG_HPRT)
+#define OTG_HS_HCCHAR(x)	MMIO32(USB_OTG_HS_BASE + OTG_HCCHAR(x))
+#define OTG_HS_HCSPLT(x)	MMIO32(USB_OTG_HS_BASE + OTG_HCSPLT(x))
+#define OTG_HS_HCINT(x)		MMIO32(USB_OTG_HS_BASE + OTG_HCINT(x))
+#define OTG_HS_HCINTMSK(x)	MMIO32(USB_OTG_HS_BASE + OTG_HCINTMSK(x))
+#define OTG_HS_HCTSIZ(x)	MMIO32(USB_OTG_HS_BASE + OTG_HCTSIZ(x))
+#define OTG_HS_HCDMA(x)		MMIO32(USB_OTG_HS_BASE + OTG_HCDMA(x))

 /* Device-mode Control and Status Registers */
-#define OTG_HS_DCFG			MMIO32(USB_OTG_HS_BASE + OTG_DCFG)
-#define OTG_HS_DCTL			MMIO32(USB_OTG_HS_BASE + OTG_DCTL)
-#define OTG_HS_DSTS			MMIO32(USB_OTG_HS_BASE + OTG_DSTS)
-#define OTG_HS_DIEPMSK			MMIO32(USB_OTG_HS_BASE + OTG_DIEPMSK)
-#define OTG_HS_DOEPMSK			MMIO32(USB_OTG_HS_BASE + OTG_DOEPMSK)
-#define OTG_HS_DAINT			MMIO32(USB_OTG_HS_BASE + OTG_DAINT)
-#define OTG_HS_DAINTMSK			MMIO32(USB_OTG_HS_BASE + OTG_DAINTMSK)
-#define OTG_HS_DVBUSDIS			MMIO32(USB_OTG_HS_BASE + OTG_DVBUSDIS)
-#define OTG_HS_DVBUSPULSE		MMIO32(USB_OTG_HS_BASE + OTG_DVBUSPULSE)
-#define OTG_HS_DIEPEMPMSK		MMIO32(USB_OTG_HS_BASE + OTG_DIEPEMPMSK)
-#define OTG_HS_DIEPCTL0			MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL0)
-#define OTG_HS_DIEPCTL(x)		MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL(x))
-#define OTG_HS_DOEPCTL0			MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL0)
-#define OTG_HS_DOEPCTL(x)		MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL(x))
-#define OTG_HS_DIEPINT(x)		MMIO32(USB_OTG_HS_BASE + OTG_DIEPINT(x))
-#define OTG_HS_DOEPINT(x)		MMIO32(USB_OTG_HS_BASE + OTG_DOEPINT(x))
-#define OTG_HS_DIEPTSIZ0		MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ0)
-#define OTG_HS_DOEPTSIZ0		MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ0)
-#define OTG_HS_DIEPTSIZ(x)		MMIO32(USB_OTG_HS_BASE + \
-						OTG_DIEPTSIZ(x))
-#define OTG_HS_DTXFSTS(x)		MMIO32(USB_OTG_HS_BASE + OTG_DTXFSTS(x))
-#define OTG_HS_DOEPTSIZ(x)		MMIO32(USB_OTG_HS_BASE + \
-						OTG_DOEPTSIZ(x))
-#define OTG_HS_DEACHHINT			MMIO32(USB_OTG_HS_BASE + OTG_DEACHHINT)
-#define OTG_HS_DEACHHINTMSK		MMIO32(USB_OTG_HS_BASE + OTG_DEACHHINTMSK)
-#define OTG_HS_DIEPEACHMSK		MMIO32(USB_OTG_HS_BASE + OTG_DIEPEACHMSK1)
-#define OTG_HS_DOEPEACHMSK		MMIO32(USB_OTG_HS_BASE + OTG_DOEPEACHMSK1)
-#define OTG_HS_DIEPDMA(x)		MMIO32(USB_OTG_HS_BASE + OTG_DIEPDMA(x))
-#define OTG_HS_DOEPDMA(x)		MMIO32(USB_OTG_HS_BASE + OTG_DOEPDMA(x))
+#define OTG_HS_DCFG		MMIO32(USB_OTG_HS_BASE + OTG_DCFG)
+#define OTG_HS_DCTL		MMIO32(USB_OTG_HS_BASE + OTG_DCTL)
+#define OTG_HS_DSTS		MMIO32(USB_OTG_HS_BASE + OTG_DSTS)
+#define OTG_HS_DIEPMSK		MMIO32(USB_OTG_HS_BASE + OTG_DIEPMSK)
+#define OTG_HS_DOEPMSK		MMIO32(USB_OTG_HS_BASE + OTG_DOEPMSK)
+#define OTG_HS_DAINT		MMIO32(USB_OTG_HS_BASE + OTG_DAINT)
+#define OTG_HS_DAINTMSK		MMIO32(USB_OTG_HS_BASE + OTG_DAINTMSK)
+#define OTG_HS_DVBUSDIS		MMIO32(USB_OTG_HS_BASE + OTG_DVBUSDIS)
+#define OTG_HS_DVBUSPULSE	MMIO32(USB_OTG_HS_BASE + OTG_DVBUSPULSE)
+#define OTG_HS_DIEPEMPMSK	MMIO32(USB_OTG_HS_BASE + OTG_DIEPEMPMSK)
+#define OTG_HS_DIEPCTL0		MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL0)
+#define OTG_HS_DIEPCTL(x)	MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL(x))
+#define OTG_HS_DOEPCTL0		MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL0)
+#define OTG_HS_DOEPCTL(x)	MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL(x))
+#define OTG_HS_DIEPINT(x)	MMIO32(USB_OTG_HS_BASE + OTG_DIEPINT(x))
+#define OTG_HS_DOEPINT(x)	MMIO32(USB_OTG_HS_BASE + OTG_DOEPINT(x))
+#define OTG_HS_DIEPTSIZ0	MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ0)
+#define OTG_HS_DOEPTSIZ0	MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ0)
+#define OTG_HS_DIEPTSIZ(x)	MMIO32(USB_OTG_HS_BASE + \
+					OTG_DIEPTSIZ(x))
+#define OTG_HS_DTXFSTS(x)	MMIO32(USB_OTG_HS_BASE + OTG_DTXFSTS(x))
+#define OTG_HS_DOEPTSIZ(x)	MMIO32(USB_OTG_HS_BASE + \
+					OTG_DOEPTSIZ(x))
+#define OTG_HS_DEACHHINT	MMIO32(USB_OTG_HS_BASE + OTG_DEACHHINT)
+#define OTG_HS_DEACHHINTMSK	MMIO32(USB_OTG_HS_BASE + OTG_DEACHHINTMSK)
+#define OTG_HS_DIEPEACHMSK	MMIO32(USB_OTG_HS_BASE + OTG_DIEPEACHMSK1)
+#define OTG_HS_DOEPEACHMSK	MMIO32(USB_OTG_HS_BASE + OTG_DOEPEACHMSK1)
+#define OTG_HS_DIEPDMA(x)	MMIO32(USB_OTG_HS_BASE + OTG_DIEPDMA(x))
+#define OTG_HS_DOEPDMA(x)	MMIO32(USB_OTG_HS_BASE + OTG_DOEPDMA(x))

 /* Power and clock gating control and status register */
 #define OTG_HS_PCGCCTL			MMIO32(USB_OTG_HS_BASE + OTG_PCGCCTL)
@ -115,22 +115,22 @@
 /* Device-mode CSRs*/
 /* OTG device each endpoint interrupt register (OTG_DEACHINT) */
 /* Bits 31:18 - Reserved */
-#define OTG_DEACHHINT_OEP1INT	(1 << 17)
+#define OTG_DEACHHINT_OEP1INT		(1 << 17)
 /* Bits 16:2 - Reserved */
-#define OTG_DEACHHINT_IEP1INT	(1 << 1)
+#define OTG_DEACHHINT_IEP1INT		(1 << 1)
 /* Bit 0 - Reserved */

 /* OTG device each in endpoint-1 interrupt register (OTG_DIEPEACHMSK1) */
 /* Bits 31:14 - Reserved */
-#define OTG_DIEPEACHMSK1_NAKM 		(1 << 13)
+#define OTG_DIEPEACHMSK1_NAKM		(1 << 13)
 /* Bits 12:10 - Reserved */
-#define OTG_DIEPEACHMSK1_BIM			(1 << 9)
+#define OTG_DIEPEACHMSK1_BIM		(1 << 9)
 #define OTG_DIEPEACHMSK1_TXFURM		(1 << 8)
 /* Bit 7 - Reserved */
-#define OTG_DIEPEACHMSK1_INEPNEM		(1 << 6)
-#define OTG_DIEPEACHMSK1_INEPNMM		(1 << 5)
+#define OTG_DIEPEACHMSK1_INEPNEM	(1 << 6)
+#define OTG_DIEPEACHMSK1_INEPNMM	(1 << 5)
 #define OTG_DIEPEACHMSK1_ITTXFEMSK	(1 << 4)
-#define OTG_DIEPEACHMSK1_TOM			(1 << 3)
+#define OTG_DIEPEACHMSK1_TOM		(1 << 3)
 /* Bit 2 - Reserved */
 #define OTG_DIEPEACHMSK1_EPDM		(1 << 1)
 #define OTG_DIEPEACHMSK1_XFRCM		(1 << 0)
@ -141,10 +141,10 @@
 #define OTG_DOEPEACHMSK1_NAKM		(1 << 13)
 #define OTG_DOEPEACHMSK1_BERRM		(1 << 12)
 /* Bits 11:10 - Reserved */
-#define OTG_DOEPEACHMSK1_BIM			(1 << 9)
+#define OTG_DOEPEACHMSK1_BIM		(1 << 9)
 #define OTG_DOEPEACHMSK1_OPEM		(1 << 8)
 /* Bits 7:3 - Reserved */
-#define OTG_DOEPEACHMSK1_AHBERRM		(1 << 2)
+#define OTG_DOEPEACHMSK1_AHBERRM	(1 << 2)
 #define OTG_DOEPEACHMSK1_EPDM		(1 << 1)
 #define OTG_DOEPEACHMSK1_XFRCM		(1 << 0)

@ -153,11 +153,11 @@
 #define OTG_HCSPLT_SPLITEN		(1 << 31)
 /* Bits 30:17 - Reserved */
 #define OTG_HCSPLT_COMPLSPLT		(1 << 16)
-#define OTG_HCSPLT_XACTPOS_ALL	(0x3 << 14)
+#define OTG_HCSPLT_XACTPOS_ALL		(0x3 << 14)
 #define OTG_HCSPLT_XACTPOS_BEGIN	(0x2 << 14)
-#define OTG_HCSPLT_XACTPOS_MID	(0x0 << 14)
-#define OTG_HCSPLT_XACTPOS_END	(0x1 << 14)
-#define OTG_HCSPLT_HUBADDR_MASK	(0x7f << 7)
+#define OTG_HCSPLT_XACTPOS_MID		(0x0 << 14)
+#define OTG_HCSPLT_XACTPOS_END		(0x1 << 14)
+#define OTG_HCSPLT_HUBADDR_MASK		(0x7f << 7)
 #define OTG_HCSPLT_PORTADDR_MASK	(0x7f << 0)

 #endif
--- a/include/libopencm3/stm32/tools.h
+++ b/include/libopencm3/stm32/tools.h
@ -35,7 +35,7 @@

 /* Clear register bit masking out some bits that must not be touched. */
 #define CLR_REG_BIT_MSK_AND_SET(REG, MSK, BIT, EXTRA_BITS) \
-		SET_REG((REG), (GET_REG((REG)) & (MSK) & (~(BIT))) | (EXTRA_BITS))
+	SET_REG((REG), (GET_REG((REG)) & (MSK) & (~(BIT))) | (EXTRA_BITS))

 #define CLR_REG_BIT_MSK(REG, MSK, BIT) \
 		CLR_REG_BIT_MSK_AND_SET((REG), (MSK), (BIT), 0)
--- a/include/libopencm3/usb/midi.h
+++ b/include/libopencm3/usb/midi.h
@ -144,9 +144,9 @@ struct usb_midi_element_descriptor_tail {
 	uint8_t bInTerminalLink;
 	uint8_t bOutTerminalLink;
 	uint8_t bElCapsSize;
-	uint16_t bmElementCaps; /* host cannot assume this is 16-bit but
-	                           device can (since highest defined bitmap
-				   value in v1.0 is bit 11) */
+	uint16_t bmElementCaps; /* host cannot assume this is 16-bit but device
+				   can (since highest defined bitmap value in
+				   v1.0 is bit 11) */
 	uint8_t iElement;
 } __attribute__((packed));

--- a/include/libopencm3/usb/usbd.h
+++ b/include/libopencm3/usb/usbd.h
@ -110,17 +110,19 @@ typedef int (*usbd_control_callback)(usbd_device *usbd_dev,
 		struct usb_setup_data *req, uint8_t **buf, uint16_t *len,
 		usbd_control_complete_callback *complete);

-typedef void (*usbd_set_config_callback)(usbd_device *usbd_dev, uint16_t wValue);
+typedef void (*usbd_set_config_callback)(usbd_device *usbd_dev,
+					 uint16_t wValue);

 typedef void (*usbd_set_altsetting_callback)(usbd_device *usbd_dev,
-		uint16_t wIndex, uint16_t wValue);
+					     uint16_t wIndex, uint16_t wValue);

 typedef void (*usbd_endpoint_callback)(usbd_device *usbd_dev, uint8_t ep);

 /* <usb_control.c> */
 /** Registers a control callback.
 *
- * The specified callback will be called if (type == (bmRequestType & type_mask))
+ * The specified callback will be called if (type == (bmRequestType
+ * & type_mask))
 * @param type Handled request type
 * @param type_mask Mask to apply before matching request type
 * @return 0 if successful
@ -137,7 +139,7 @@ extern int usbd_register_set_config_callback(usbd_device *usbd_dev,
 					  usbd_set_config_callback callback);
 /** Registers a "Set Interface" (alternate setting) callback */
 extern void usbd_register_set_altsetting_callback(usbd_device *usbd_dev,
-					  usbd_set_altsetting_callback callback);
+					usbd_set_altsetting_callback callback);

 /* Functions to be provided by the hardware abstraction layer */
 extern void usbd_poll(usbd_device *usbd_dev);
--- a/lib/efm32/lg/adc.c
+++ b/lib/efm32/lg/adc.c
@ -87,7 +87,7 @@ void adc_disable_tailgating(uint32_t adc)
 */
 void adc_set_warm_up_mode(uint32_t adc, uint32_t warmupmode)
 {
-	ADC_CTRL(adc) = (ADC_CTRL(adc) & ~ADC_CTRL_WARMUPMODE_MASK) 
+	ADC_CTRL(adc) = (ADC_CTRL(adc) & ~ADC_CTRL_WARMUPMODE_MASK)
 			| warmupmode;
 }

--- a/lib/stm32/common/spi_common_all.c
+++ b/lib/stm32/common/spi_common_all.c
@ -730,10 +730,10 @@ Mode | CPOL | CPHA

 void spi_set_standard_mode(uint32_t spi, uint8_t mode)
 {
-	if(mode > 3) {
+	if (mode > 3) {
 		return;
 	}
-	
+
 	uint32_t reg32 = SPI_CR1(spi) & ~(SPI_CR1_CPOL | SPI_CR1_CPHA);
 	SPI_CR1(spi) = reg32 | mode;
 }
--- a/lib/stm32/common/st_usbfs_core.h
+++ b/lib/stm32/common/st_usbfs_core.h
@ -44,8 +44,10 @@ void st_usbfs_endpoints_reset(usbd_device *usbd_dev);
 void st_usbfs_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall);
 uint8_t st_usbfs_ep_stall_get(usbd_device *usbd_dev, uint8_t addr);
 void st_usbfs_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak);
-uint16_t st_usbfs_ep_write_packet(usbd_device *usbd_dev, uint8_t addr, const void *buf, uint16_t len);
-uint16_t st_usbfs_ep_read_packet(usbd_device *usbd_dev, uint8_t addr, void *buf, uint16_t len);
+uint16_t st_usbfs_ep_write_packet(usbd_device *usbd_dev, uint8_t addr,
+				  const void *buf, uint16_t len);
+uint16_t st_usbfs_ep_read_packet(usbd_device *usbd_dev, uint8_t addr,
+				 void *buf, uint16_t len);
 void st_usbfs_poll(usbd_device *usbd_dev);

 /* These must be implemented by the device specific driver */
--- a/lib/stm32/f0/flash.c
+++ b/lib/stm32/f0/flash.c
@ -76,10 +76,10 @@ error, bit 5: end of operation.

 uint32_t flash_get_status_flags(void)
 {
-	return (FLASH_SR & (FLASH_SR_PGERR |
+	return FLASH_SR & (FLASH_SR_PGERR |
 			FLASH_SR_EOP |
 			FLASH_SR_WRPRTERR |
-			FLASH_SR_BSY));
+			FLASH_SR_BSY);
 }

 /*---------------------------------------------------------------------------*/
--- a/lib/stm32/f0/rcc.c
+++ b/lib/stm32/f0/rcc.c
@ -523,7 +523,7 @@ enum rcc_osc rcc_system_clock_source(void)
 *
 * @returns ::osc_t USB clock source:
 */
- 
+
 enum rcc_osc rcc_usb_clock_source(void)
 {
 	return (RCC_CFGR3 & RCC_CFGR3_USBSW) ? PLL : HSI48;
@ -669,10 +669,10 @@ void rcc_clock_setup_in_hsi48_out_48mhz(void)
 {
 	rcc_osc_on(HSI48);
 	rcc_wait_for_osc_ready(HSI48);
-	
+
 	rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
 	rcc_set_ppre(RCC_CFGR_PPRE_NODIV);
-	
+
 	flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);

 	rcc_set_sysclk_source(HSI48);
--- a/lib/stm32/f1/flash.c
+++ b/lib/stm32/f1/flash.c
@ -128,8 +128,9 @@ void flash_lock_upper(void)

 void flash_clear_pgerr_flag_upper(void)
 {
-	if (MEMORY_SIZE_REG > 512)
+	if (MEMORY_SIZE_REG > 512) {
 		FLASH_SR2 |= FLASH_SR_PGERR;
+	}
 }

 /*---------------------------------------------------------------------------*/
@ -139,8 +140,9 @@ void flash_clear_pgerr_flag_upper(void)

 void flash_clear_eop_flag_upper(void)
 {
-	if (MEMORY_SIZE_REG > 512)
+	if (MEMORY_SIZE_REG > 512) {
 		FLASH_SR2 |= FLASH_SR_EOP;
+	}
 }

 /*---------------------------------------------------------------------------*/
@ -150,8 +152,9 @@ void flash_clear_eop_flag_upper(void)

 void flash_clear_wrprterr_flag_upper(void)
 {
-	if (MEMORY_SIZE_REG > 512)
+	if (MEMORY_SIZE_REG > 512) {
 		FLASH_SR2 |= FLASH_SR_WRPRTERR;
+	}
 }

 /*---------------------------------------------------------------------------*/
@ -161,8 +164,9 @@ void flash_clear_wrprterr_flag_upper(void)

 void flash_clear_bsy_flag_upper(void)
 {
-	if (MEMORY_SIZE_REG > 512)
+	if (MEMORY_SIZE_REG > 512) {
 		FLASH_SR2 &= ~FLASH_SR_BSY;
+	}
 }

 /*---------------------------------------------------------------------------*/
@ -204,12 +208,14 @@ uint32_t flash_get_status_flags(void)
 			FLASH_SR_EOP |
 			FLASH_SR_WRPRTERR |
 			FLASH_SR_BSY));
-	if (MEMORY_SIZE_REG > 512)
+	if (MEMORY_SIZE_REG > 512) {
 		flags |= (FLASH_SR2 & (FLASH_SR_PGERR |
 			FLASH_SR_EOP |
 			FLASH_SR_WRPRTERR |
 			FLASH_SR_BSY));
-    return flags;
+	}
+
+	return flags;
 }

 /*---------------------------------------------------------------------------*/
@ -229,17 +235,21 @@ void flash_program_half_word(uint32_t address, uint16_t data)
 {
 	flash_wait_for_last_operation();

-	if ((MEMORY_SIZE_REG > 512) && (address >= FLASH_BASE+0x00080000))
+	if ((MEMORY_SIZE_REG > 512) && (address >= FLASH_BASE+0x00080000)) {
 		FLASH_CR2 |= FLASH_CR_PG;
-	else FLASH_CR |= FLASH_CR_PG;
+	} else {
+		FLASH_CR |= FLASH_CR_PG;
+	}

 	MMIO16(address) = data;

 	flash_wait_for_last_operation();

-	if ((MEMORY_SIZE_REG > 512) && (address >= FLASH_BASE+0x00080000))
+	if ((MEMORY_SIZE_REG > 512) && (address >= FLASH_BASE+0x00080000)) {
 		FLASH_CR2 &= ~FLASH_CR_PG;
-	else FLASH_CR &= ~FLASH_CR_PG;
+	} else {
+		FLASH_CR &= ~FLASH_CR_PG;
+	}
 }

 /*---------------------------------------------------------------------------*/
@ -259,7 +269,8 @@ void flash_erase_page(uint32_t page_address)
 {
 	flash_wait_for_last_operation();

-	if ((MEMORY_SIZE_REG > 512) && (page_address >= FLASH_BASE+0x00080000)) {
+	if ((MEMORY_SIZE_REG > 512)
+	    && (page_address >= FLASH_BASE+0x00080000)) {
 		FLASH_CR2 |= FLASH_CR_PER;
 		FLASH_AR2 = page_address;
 		FLASH_CR2 |= FLASH_CR_STRT;
@ -271,10 +282,12 @@ void flash_erase_page(uint32_t page_address)

 	flash_wait_for_last_operation();

-	if ((MEMORY_SIZE_REG > 512) && (page_address >= FLASH_BASE+0x00080000))
+	if ((MEMORY_SIZE_REG > 512)
+	    && (page_address >= FLASH_BASE+0x00080000)) {
 		FLASH_CR2 &= ~FLASH_CR_PER;
-	else
+	} else {
 		FLASH_CR &= ~FLASH_CR_PER;
+	}
 }

 /*---------------------------------------------------------------------------*/
--- a/lib/stm32/f1/rcc.c
+++ b/lib/stm32/f1/rcc.c
@ -509,7 +509,7 @@ void rcc_set_pllxtpre(uint32_t pllxtpre)

 uint32_t rcc_rtc_clock_enabled_flag(void)
 {
-        return RCC_BDCR & RCC_BDCR_RTCEN;
+	return RCC_BDCR & RCC_BDCR_RTCEN;
 }

 /*---------------------------------------------------------------------------*/
@ -638,10 +638,11 @@ The prescale factor can be set to 1 (no prescale) for use when the PLL clock is

 void rcc_set_usbpre(uint32_t usbpre)
 {
-	if (usbpre)
+	if (usbpre) {
 		RCC_CFGR |= RCC_CFGR_USBPRE;
-	else
+	} else {
 		RCC_CFGR &= ~RCC_CFGR_USBPRE;
+	}
 }

 void rcc_set_prediv1(uint32_t prediv)
@ -658,10 +659,11 @@ void rcc_set_prediv2(uint32_t prediv)

 void rcc_set_prediv1_source(uint32_t rccsrc)
 {
-	if (rccsrc)
+	if (rccsrc) {
 		RCC_CFGR2 |= RCC_CFGR2_PREDIV1SRC;
-	else
+	} else {
 		RCC_CFGR2 &= ~RCC_CFGR2_PREDIV1SRC;
+	}
 }

 /*---------------------------------------------------------------------------*/
--- a/lib/stm32/f3/adc.c
+++ b/lib/stm32/f3/adc.c
@ -375,7 +375,7 @@ void adc_disable_eoc_interrupt_injected(uint32_t adc)

 void adc_enable_eos_interrupt_injected(uint32_t adc)
 {
-        ADC_IER(adc) |= ADC_IER_JEOSIE;
+	ADC_IER(adc) |= ADC_IER_JEOSIE;
 }

 /*---------------------------------------------------------------------------*/
@ -387,7 +387,7 @@ void adc_enable_eos_interrupt_injected(uint32_t adc)

 void adc_disable_eos_interrupt_injected(uint32_t adc)
 {
-        ADC_IER(adc) &= ~ADC_IER_JEOSIE;
+	ADC_IER(adc) &= ~ADC_IER_JEOSIE;
 }


@ -452,7 +452,7 @@ void adc_disable_eoc_interrupt(uint32_t adc)

 void adc_enable_eos_interrupt(uint32_t adc)
 {
-        ADC_IER(adc) |= ADC_IER_EOSIE;
+	ADC_IER(adc) |= ADC_IER_EOSIE;
 }

 /*---------------------------------------------------------------------------*/
@ -464,7 +464,7 @@ void adc_enable_eos_interrupt(uint32_t adc)

 void adc_disable_eos_interrupt(uint32_t adc)
 {
-        ADC_IER(adc) &= ~ADC_IER_EOSIE;
+	ADC_IER(adc) &= ~ADC_IER_EOSIE;
 }


--- a/lib/stm32/f3/rcc.c
+++ b/lib/stm32/f3/rcc.c
@ -475,8 +475,10 @@ void rcc_usb_prescale_1(void)

 void rcc_adc_prescale(uint32_t prescale1, uint32_t prescale2)
 {
-	uint32_t clear_mask = (RCC_CFGR2_ADCxPRES_MASK << RCC_CFGR2_ADC12PRES_SHIFT) |
-		(RCC_CFGR2_ADCxPRES_MASK << RCC_CFGR2_ADC34PRES_SHIFT);
+	uint32_t clear_mask = (RCC_CFGR2_ADCxPRES_MASK
+			       << RCC_CFGR2_ADC12PRES_SHIFT)
+			      | (RCC_CFGR2_ADCxPRES_MASK
+				 << RCC_CFGR2_ADC34PRES_SHIFT);
 	uint32_t set = (prescale1 << RCC_CFGR2_ADC12PRES_SHIFT) |
 		(prescale2 << RCC_CFGR2_ADC34PRES_SHIFT);
 	RCC_CFGR2 &= ~(clear_mask);
--- a/lib/stm32/f4/fmc.c
+++ b/lib/stm32/f4/fmc.c
@ -51,7 +51,7 @@ sdram_timing(struct sdram_timing *t) {
 */
 void
 sdram_command(enum fmc_sdram_bank bank,
-              enum fmc_sdram_command cmd, int autorefresh, int modereg) {
+	      enum fmc_sdram_command cmd, int autorefresh, int modereg) {
 	uint32_t tmp_reg = 0;

 	switch (bank) {
@ -68,31 +68,31 @@ sdram_command(enum fmc_sdram_bank bank,
 	tmp_reg |= autorefresh << FMC_SDCMR_NRFS_SHIFT;
 	tmp_reg |= modereg << FMC_SDCMR_MRD_SHIFT;
 	switch (cmd) {
-		case SDRAM_CLK_CONF:
-			tmp_reg |= FMC_SDCMR_MODE_CLOCK_CONFIG_ENA;
-			break;
-		case SDRAM_AUTO_REFRESH:
-			tmp_reg |= FMC_SDCMR_MODE_AUTO_REFRESH;
-			break;
-		case SDRAM_LOAD_MODE:
-			tmp_reg |= FMC_SDCMR_MODE_LOAD_MODE_REGISTER;
-			break;
-		case SDRAM_PALL:
-			tmp_reg |= FMC_SDCMR_MODE_PALL;
-			break;
-		case SDRAM_SELF_REFRESH:
-			tmp_reg |= FMC_SDCMR_MODE_SELF_REFRESH;
-			break;
-		case SDRAM_POWER_DOWN:
-			tmp_reg |= FMC_SDCMR_MODE_POWER_DOWN;
-			break;
-		case SDRAM_NORMAL:
-		default:
-			break;
+	case SDRAM_CLK_CONF:
+		tmp_reg |= FMC_SDCMR_MODE_CLOCK_CONFIG_ENA;
+		break;
+	case SDRAM_AUTO_REFRESH:
+		tmp_reg |= FMC_SDCMR_MODE_AUTO_REFRESH;
+		break;
+	case SDRAM_LOAD_MODE:
+		tmp_reg |= FMC_SDCMR_MODE_LOAD_MODE_REGISTER;
+		break;
+	case SDRAM_PALL:
+		tmp_reg |= FMC_SDCMR_MODE_PALL;
+		break;
+	case SDRAM_SELF_REFRESH:
+		tmp_reg |= FMC_SDCMR_MODE_SELF_REFRESH;
+		break;
+	case SDRAM_POWER_DOWN:
+		tmp_reg |= FMC_SDCMR_MODE_POWER_DOWN;
+		break;
+	case SDRAM_NORMAL:
+	default:
+		break;
 	}

 	/* Wait for the next chance to talk to the controller */
-	while (FMC_SDSR & FMC_SDSR_BUSY) ;
+	while (FMC_SDSR & FMC_SDSR_BUSY);

 	/* Send the next command */
 	FMC_SDCMR = tmp_reg;
--- a/lib/stm32/l0/rcc.c
+++ b/lib/stm32/l0/rcc.c
@ -293,14 +293,16 @@ void rcc_wait_for_osc_ready(enum rcc_osc osc)
 /*---------------------------------------------------------------------------*/
 /** @brief RCC Set HSI48 clock source to the RC48 (CRS)
 */
-void rcc_set_hsi48_source_rc48(void) {
+void rcc_set_hsi48_source_rc48(void)
+{
 	RCC_CCIPR |= RCC_CCIPR_HSI48SEL;
 }

 /*---------------------------------------------------------------------------*/
 /** @brief RCC Set HSI48 clock source to the PLL
 */
-void rcc_set_hsi48_source_pll(void) {
+void rcc_set_hsi48_source_pll(void)
+{
 	RCC_CCIPR &= ~RCC_CCIPR_HSI48SEL;
 }

@ -343,7 +345,8 @@ void rcc_set_sysclk_source(enum rcc_osc osc)

 void rcc_set_pll_multiplier(uint32_t factor)
 {
-	uint32_t reg = RCC_CFGR & ~(RCC_CFGR_PLLMUL_MASK<<RCC_CFGR_PLLMUL_SHIFT);
+	uint32_t reg = RCC_CFGR
+		       & ~(RCC_CFGR_PLLMUL_MASK << RCC_CFGR_PLLMUL_SHIFT);
 	RCC_CFGR = reg | (factor << RCC_CFGR_PLLMUL_SHIFT);
 }

@ -358,7 +361,8 @@ void rcc_set_pll_multiplier(uint32_t factor)

 void rcc_set_pll_divider(uint32_t factor)
 {
-	uint32_t reg = RCC_CFGR & ~(RCC_CFGR_PLLDIV_MASK<<RCC_CFGR_PLLDIV_SHIFT);
+	uint32_t reg = RCC_CFGR
+		       & ~(RCC_CFGR_PLLDIV_MASK << RCC_CFGR_PLLDIV_SHIFT);
 	RCC_CFGR = reg | (factor << RCC_CFGR_PLLDIV_SHIFT);
 }

@ -372,7 +376,8 @@ void rcc_set_pll_divider(uint32_t factor)

 void rcc_set_ppre1(uint32_t ppre)
 {
-	uint32_t reg = RCC_CFGR & ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
+	uint32_t reg = RCC_CFGR
+		       & ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
 	RCC_CFGR = reg | (ppre << RCC_CFGR_PPRE1_SHIFT);
 }

@ -386,7 +391,8 @@ void rcc_set_ppre1(uint32_t ppre)

 void rcc_set_ppre2(uint32_t ppre)
 {
-	uint32_t reg = RCC_CFGR & ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
+	uint32_t reg = RCC_CFGR
+		       & ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
 	RCC_CFGR = reg | (ppre << RCC_CFGR_PPRE2_SHIFT);
 }

--- a/lib/stm32/l1/flash.c
+++ b/lib/stm32/l1/flash.c
@ -121,39 +121,46 @@ void flash_set_ws(uint32_t ws)
 	FLASH_ACR = reg32;
 }

-void flash_unlock_pecr(void) {
+void flash_unlock_pecr(void)
+{
 	FLASH_PEKEYR = FLASH_PEKEYR_PEKEY1;
 	FLASH_PEKEYR = FLASH_PEKEYR_PEKEY2;
 }

-void flash_lock_pecr(void) {
+void flash_lock_pecr(void)
+{
 	FLASH_PECR |= FLASH_PECR_PELOCK;
 }

-void flash_unlock_progmem(void) {
+void flash_unlock_progmem(void)
+{
 	flash_unlock_pecr();
 	FLASH_PRGKEYR = FLASH_PRGKEYR_PRGKEY1;
 	FLASH_PRGKEYR = FLASH_PRGKEYR_PRGKEY2;
 }

-void flash_lock_progmem(void) {
+void flash_lock_progmem(void)
+{
 	FLASH_PECR |= FLASH_PECR_PRGLOCK;
 }

-void flash_unlock_option_bytes(void) {
+void flash_unlock_option_bytes(void)
+{
 	flash_unlock_pecr();
 	FLASH_OPTKEYR = FLASH_OPTKEYR_OPTKEY1;
 	FLASH_OPTKEYR = FLASH_OPTKEYR_OPTKEY2;
 }

-void flash_lock_option_bytes(void) {
+void flash_lock_option_bytes(void)
+{
 	FLASH_PECR |= FLASH_PECR_OPTLOCK;
 }

 /** @brief Unlock all segments of flash
 *
 */
-void flash_unlock(void) {
+void flash_unlock(void)
+{
 	flash_unlock_pecr();
 	flash_unlock_progmem();
 	flash_unlock_option_bytes();
@ -162,7 +169,8 @@ void flash_unlock(void) {
 /** @brief Lock all segments of flash
 *
 */
-void flash_lock(void) {
+void flash_lock(void)
+{
 	flash_lock_option_bytes();
 	flash_lock_progmem();
 	flash_lock_pecr();
@ -173,7 +181,8 @@ void flash_lock(void) {
 * @param address assumed to be in the eeprom space, no checking
 * @param data word to write
 */
-void eeprom_program_word(uint32_t address, uint32_t data) {
+void eeprom_program_word(uint32_t address, uint32_t data)
+{
 	flash_unlock_pecr();
 	/* erase only if needed */
 	FLASH_PECR &= ~FLASH_PECR_FTDW;
@ -183,8 +192,9 @@ void eeprom_program_word(uint32_t address, uint32_t data) {

 /** @brief Write a block of words to eeprom
 *
- * Writes a block of words to EEPROM at the requested address, erasing if necessary,
- * and locking afterwards.  Only wordwise writing is safe for writing any value
+ * Writes a block of words to EEPROM at the requested address, erasing if
+ * necessary, and locking afterwards.  Only wordwise writing is safe for
+ * writing any value
 *
 * @param[in] address must point to EEPROM space, no checking!
 * @param[in] data pointer to data to write
@ -192,16 +202,16 @@ void eeprom_program_word(uint32_t address, uint32_t data) {
 */
 void eeprom_program_words(uint32_t address, uint32_t *data, int length_in_words)
 {
-       int i;
-       flash_unlock_pecr();
-       while (FLASH_SR & FLASH_SR_BSY);
-       /* erase only if needed */
-       FLASH_PECR &= ~FLASH_PECR_FTDW;
-       for (i = 0; i < length_in_words; i++) {
-               MMIO32(address + (i * sizeof(uint32_t))) = *(data+i);
-               while (FLASH_SR & FLASH_SR_BSY);
-       }
-       flash_lock_pecr();
+	int i;
+	flash_unlock_pecr();
+	while (FLASH_SR & FLASH_SR_BSY);
+	/* erase only if needed */
+	FLASH_PECR &= ~FLASH_PECR_FTDW;
+	for (i = 0; i < length_in_words; i++) {
+		MMIO32(address + (i * sizeof(uint32_t))) = *(data+i);
+		while (FLASH_SR & FLASH_SR_BSY);
+	}
+	flash_lock_pecr();
 }


--- a/lib/usb/usb_control.c
+++ b/lib/usb/usb_control.c
@ -59,7 +59,8 @@ static void stall_transaction(usbd_device *usbd_dev)
 * @param ep_size
 * @return
 */
-static bool needs_zlp(uint16_t len, uint16_t wLength, uint8_t ep_size) {
+static bool needs_zlp(uint16_t len, uint16_t wLength, uint8_t ep_size)
+{
 	if (len < wLength) {
 		if (len && (len % ep_size == 0)) {
 			return true;
@ -109,7 +110,8 @@ static void usb_control_send_chunk(usbd_device *usbd_dev)
 				     usbd_dev->control_state.ctrl_len);

 		usbd_dev->control_state.state =
-			usbd_dev->control_state.needs_zlp ? DATA_IN : LAST_DATA_IN;
+			usbd_dev->control_state.needs_zlp ?
+			DATA_IN : LAST_DATA_IN;
 		usbd_dev->control_state.needs_zlp = false;
 		usbd_dev->control_state.ctrl_len = 0;
 		usbd_dev->control_state.ctrl_buf = NULL;
--- a/lib/usb/usb_efm32lg.c
+++ b/lib/usb/usb_efm32lg.c
@ -51,7 +51,7 @@ static usbd_device *efm32lg_usbd_init(void)
 	CMU_CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV;

 	/* wait till clock not selected */
-	while(!(CMU_STATUS & CMU_STATUS_USBCHFCLKSEL));
+	while (!(CMU_STATUS & CMU_STATUS_USBCHFCLKSEL));

 	USB_GINTSTS = USB_GINTSTS_MMIS;

@ -179,7 +179,8 @@ static void efm32lg_endpoints_reset(usbd_device *usbd_dev)
 	usbd_dev->fifo_mem_top = usbd_dev->fifo_mem_top_ep0;
 }

-static void efm32lg_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall)
+static void efm32lg_ep_stall_set(usbd_device *usbd_dev, uint8_t addr,
+				 uint8_t stall)
 {
 	(void)usbd_dev;
 	if (addr == 0) {
--- a/lib/usb/usb_fx07_common.c
+++ b/lib/usb/usb_fx07_common.c
@ -132,7 +132,8 @@ void stm32fx07_endpoints_reset(usbd_device *usbd_dev)
 	}

 	/* Flush all tx/rx fifos */
-	REBASE(OTG_GRSTCTL) = OTG_GRSTCTL_TXFFLSH | OTG_GRSTCTL_TXFNUM_ALL | OTG_GRSTCTL_RXFFLSH;
+	REBASE(OTG_GRSTCTL) = OTG_GRSTCTL_TXFFLSH | OTG_GRSTCTL_TXFNUM_ALL
+			      | OTG_GRSTCTL_RXFFLSH;
 }

 void stm32fx07_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall)
--- a/lib/usb/usb_msc.c
+++ b/lib/usb/usb_msc.c
@ -153,8 +153,9 @@ struct usb_msc_trans {

 	uint32_t bytes_to_read;
 	uint32_t bytes_to_write;
-	uint32_t byte_count;		/* Either read until equal to bytes_to_read or
-					   write until equal to bytes_to_write. */
+	uint32_t byte_count;		/* Either read until equal to
+					   bytes_to_read or write until equal
+					   to bytes_to_write. */
 	uint32_t lba_start;
 	uint32_t block_count;
 	uint32_t current_block;
@ -288,7 +289,8 @@ static void scsi_write_6(usbd_mass_storage *ms,

 		buf = get_cbw_buf(trans);

-		trans->lba_start = ((0x1f & buf[1]) << 16) | (buf[2] << 8) | buf[3];
+		trans->lba_start = ((0x1f & buf[1]) << 16)
+				    | (buf[2] << 8) | buf[3];
 		trans->block_count = buf[4];
 		trans->current_block = 0;

@ -325,7 +327,8 @@ static void scsi_read_10(usbd_mass_storage *ms,

 		buf = get_cbw_buf(trans);

-		trans->lba_start = (buf[2] << 24) | (buf[3] << 16) | (buf[4] << 8) | buf[5];
+		trans->lba_start = (buf[2] << 24) | (buf[3] << 16)
+				   | (buf[4] << 8) | buf[5];
 		trans->block_count = (buf[7] << 8) | buf[8];

 		/* TODO: Check the lba & block_count for range. */
@ -384,7 +387,8 @@ static void scsi_request_sense(usbd_mass_storage *ms,
 		buf = &trans->cbw.cbw.CBWCB[0];

 		trans->bytes_to_write = buf[4];	/* allocation length */
-		memcpy(trans->msd_buf, _spc3_request_sense, sizeof(_spc3_request_sense));
+		memcpy(trans->msd_buf, _spc3_request_sense,
+		       sizeof(_spc3_request_sense));

 		trans->msd_buf[2] = ms->sense.key;
 		trans->msd_buf[12] = ms->sense.asc;
@ -445,7 +449,8 @@ static void scsi_inquiry(usbd_mass_storage *ms,
 		if (0 == evpd) {
 			size_t len;
 			trans->bytes_to_write = sizeof(_spc3_inquiry_response);
-			memcpy(trans->msd_buf, _spc3_inquiry_response, sizeof(_spc3_inquiry_response));
+			memcpy(trans->msd_buf, _spc3_inquiry_response,
+			       sizeof(_spc3_inquiry_response));

 			len = strlen(ms->vendor_id);
 			len = MIN(len, 8);
@ -457,9 +462,11 @@ static void scsi_inquiry(usbd_mass_storage *ms,

 			len = strlen(ms->product_revision_level);
 			len = MIN(len, 4);
-			memcpy(&trans->msd_buf[32], ms->product_revision_level, len);
+			memcpy(&trans->msd_buf[32], ms->product_revision_level,
+			       len);

-			trans->csw.csw.dCSWDataResidue = sizeof(_spc3_inquiry_response);
+			trans->csw.csw.dCSWDataResidue =
+				sizeof(_spc3_inquiry_response);

 			set_sbc_status_good(ms);
 		} else {
@ -564,7 +571,7 @@ static void msc_data_rx_cb(usbd_device *usbd_dev, uint8_t ep)

 	if (trans->byte_count < trans->bytes_to_read) {
 		if (0 < trans->block_count) {
-			if ((0 == trans->byte_count) && (NULL != ms->lock)){
+			if ((0 == trans->byte_count) && (NULL != ms->lock)) {
 				(*ms->lock)();
 			}
 		}
@ -580,7 +587,8 @@ static void msc_data_rx_cb(usbd_device *usbd_dev, uint8_t ep)
 				uint32_t lba;

 				lba = trans->lba_start + trans->current_block;
-				if (0 != (*ms->write_block)(lba, trans->msd_buf)) {
+				if (0 != (*ms->write_block)(lba,
+							    trans->msd_buf)) {
 					/* Error */
 				}
 				trans->current_block++;
@ -596,7 +604,8 @@ static void msc_data_rx_cb(usbd_device *usbd_dev, uint8_t ep)
 				uint32_t lba;

 				lba = trans->lba_start + trans->current_block;
-				if (0 != (*ms->read_block)(lba, trans->msd_buf)) {
+				if (0 != (*ms->read_block)(lba,
+							   trans->msd_buf)) {
 					/* Error */
 				}
 				trans->current_block++;
@ -614,12 +623,13 @@ static void msc_data_rx_cb(usbd_device *usbd_dev, uint8_t ep)
 				uint32_t lba;

 				lba = trans->lba_start + trans->current_block;
-				if (0 != (*ms->write_block)(lba, trans->msd_buf)) {
+				if (0 != (*ms->write_block)(lba,
+							    trans->msd_buf)) {
 					/* Error */
 				}

 				trans->current_block = 0;
-				if (NULL != ms->unlock){
+				if (NULL != ms->unlock) {
 					(*ms->unlock)();
 				}
 			}
@ -633,7 +643,8 @@ static void msc_data_rx_cb(usbd_device *usbd_dev, uint8_t ep)
 		if (0 < left) {
 			max_len = MIN(ms->ep_out_size, left);
 			p = &trans->csw.buf[trans->csw_sent];
-			len = usbd_ep_write_packet(usbd_dev, ms->ep_in, p, max_len);
+			len = usbd_ep_write_packet(usbd_dev, ms->ep_in, p,
+						   max_len);
 			trans->csw_sent += len;
 		}
 	}
@ -656,7 +667,8 @@ static void msc_data_tx_cb(usbd_device *usbd_dev, uint8_t ep)
 				uint32_t lba;

 				lba = trans->lba_start + trans->current_block;
-				if (0 != (*ms->read_block)(lba, trans->msd_buf)) {
+				if (0 != (*ms->read_block)(lba,
+							   trans->msd_buf)) {
 					/* Error */
 				}
 				trans->current_block++;
@ -672,7 +684,7 @@ static void msc_data_tx_cb(usbd_device *usbd_dev, uint8_t ep)
 		if (0 < trans->block_count) {
 			if (trans->current_block == trans->block_count) {
 				trans->current_block = 0;
-				if (NULL != ms->unlock){
+				if (NULL != ms->unlock) {
 					(*ms->unlock)();
 				}
 			}
@ -707,8 +719,9 @@ static void msc_data_tx_cb(usbd_device *usbd_dev, uint8_t ep)
 *	   interface.
 */
 static int msc_control_request(usbd_device *usbd_dev,
-				struct usb_setup_data *req, uint8_t **buf, uint16_t *len,
-				usbd_control_complete_callback *complete)
+			       struct usb_setup_data *req, uint8_t **buf,
+			       uint16_t *len,
+			       usbd_control_complete_callback *complete)
 {
 	(void)complete;
 	(void)usbd_dev;
@ -777,8 +790,10 @@ usbd_mass_storage *usb_msc_init(usbd_device *usbd_dev,
 				 const char *product_id,
 				 const char *product_revision_level,
 				 const uint32_t block_count,
-				 int (*read_block)(uint32_t lba, uint8_t *copy_to),
-				 int (*write_block)(uint32_t lba, const uint8_t *copy_from))
+				 int (*read_block)(uint32_t lba,
+						   uint8_t *copy_to),
+				 int (*write_block)(uint32_t lba,
+						    const uint8_t *copy_from))
 {
 	_mass_storage.usbd_dev = usbd_dev;
 	_mass_storage.ep_in = ep_in;
--- a/lib/usb/usb_standard.c
+++ b/lib/usb/usb_standard.c
@ -45,8 +45,9 @@ int usbd_register_set_config_callback(usbd_device *usbd_dev,
 	int i;

 	for (i = 0; i < MAX_USER_SET_CONFIG_CALLBACK; i++) {
-		if (usbd_dev->user_callback_set_config[i])
+		if (usbd_dev->user_callback_set_config[i]) {
 			continue;
+		}

 		usbd_dev->user_callback_set_config[i] = callback;
 		return 0;
@ -56,7 +57,7 @@ int usbd_register_set_config_callback(usbd_device *usbd_dev,
 }

 void usbd_register_set_altsetting_callback(usbd_device *usbd_dev,
-					   usbd_set_altsetting_callback callback)
+					usbd_set_altsetting_callback callback)
 {
 	usbd_dev->user_callback_set_altsetting = callback;
 }
@ -253,9 +254,10 @@ static int usb_standard_set_configuration(usbd_device *usbd_dev,
 	(void)buf;
 	(void)len;

-	if(req->wValue > 0) {
+	if (req->wValue > 0) {
 		for (i = 0; i < usbd_dev->desc->bNumConfigurations; i++) {
-			if (req->wValue == usbd_dev->config[i].bConfigurationValue) {
+			if (req->wValue
+			    == usbd_dev->config[i].bConfigurationValue) {
 				found_index = i;
 				break;
 			}
@ -310,7 +312,8 @@ static int usb_standard_get_configuration(usbd_device *usbd_dev,
 	if (*len > 1) {
 		*len = 1;
 	}
-	const struct usb_config_descriptor *cfg = &usbd_dev->config[usbd_dev->current_config - 1];
+	const struct usb_config_descriptor *cfg =
+		&usbd_dev->config[usbd_dev->current_config - 1];
 	(*buf)[0] = cfg->bConfigurationValue;

 	return 1;
@ -320,7 +323,8 @@ static int usb_standard_set_interface(usbd_device *usbd_dev,
 				      struct usb_setup_data *req,
 				      uint8_t **buf, uint16_t *len)
 {
-	const struct usb_config_descriptor *cfx = &usbd_dev->config[usbd_dev->current_config - 1];
+	const struct usb_config_descriptor *cfx =
+		&usbd_dev->config[usbd_dev->current_config - 1];
 	const struct usb_interface *iface;

 	(void)buf;
@ -343,7 +347,8 @@ static int usb_standard_set_interface(usbd_device *usbd_dev,

 	if (usbd_dev->user_callback_set_altsetting) {
 			usbd_dev->user_callback_set_altsetting(usbd_dev,
-							req->wIndex, req->wValue);
+							       req->wIndex,
+							       req->wValue);
 	}

 	*len = 0;
@ -356,7 +361,8 @@ static int usb_standard_get_interface(usbd_device *usbd_dev,
 				      uint8_t **buf, uint16_t *len)
 {
 	uint8_t *cur_altsetting;
-	const struct usb_config_descriptor *cfx = &usbd_dev->config[usbd_dev->current_config - 1];
+	const struct usb_config_descriptor *cfx =
+		&usbd_dev->config[usbd_dev->current_config - 1];

 	if (req->wIndex >= cfx->bNumInterfaces) {
 		return USBD_REQ_NOTSUPP;
--- a/lib/vf6xx/ccm.c
+++ b/lib/vf6xx/ccm.c
@ -102,8 +102,7 @@ uint32_t ccm_get_pll_pfd(uint32_t pfd_sel, uint32_t pll_pfd, uint32_t pll_clk)
 	uint64_t pll_pfd_clk;
 	uint32_t pll_pfd_frac = pll_pfd;

-	switch(pfd_sel)
-	{
+	switch (pfd_sel) {
 	case CCM_CCSR_PLL_PFD_CLK_SEL_MAIN:
 		return pll_clk;
 	case CCM_CCSR_PLL_PFD_CLK_SEL_PFD1:
@ -164,8 +163,7 @@ void ccm_calculate_clocks()
 	ipg_clk_div += 1;

 	/* Get Cortex-A5 core clock from system clock selection */
-	switch(ccsr & CCM_CCSR_SYS_CLK_SEL_MASK)
-	{
+	switch (ccsr & CCM_CCSR_SYS_CLK_SEL_MASK) {
 	case CCM_CCSR_SYS_CLK_SEL_FAST:
 		ccm_core_clk = 24000000;
 		break;
--- a/tests/gadget-zero/main-stm32f072disco.c
+++ b/tests/gadget-zero/main-stm32f072disco.c
@ -25,7 +25,7 @@
 #include <stdio.h>
 #include "usb-gadget0.h"

-// no trace on cm0 #define ER_DEBUG
+/* no trace on cm0 #define ER_DEBUG */
 #ifdef ER_DEBUG
 #define ER_DPRINTF(fmt, ...) \
    do { printf(fmt, ## __VA_ARGS__); } while (0)
@ -35,7 +35,8 @@
 #endif

 #include "trace.h"
-void trace_send_blocking8(int stimulus_port, char c) {
+void trace_send_blocking8(int stimulus_port, char c)
+{
 	(void)stimulus_port;
 	(void)c;
 }
@ -52,7 +53,8 @@ int main(void)
 	gpio_mode_setup(GPIOC, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO7);
 	gpio_set(GPIOC, GPIO7);

-	usbd_device *usbd_dev = gadget0_init(&st_usbfs_v2_usb_driver, "stm32f072disco");
+	usbd_device *usbd_dev = gadget0_init(&st_usbfs_v2_usb_driver,
+					     "stm32f072disco");

 	ER_DPRINTF("bootup complete\n");
 	gpio_clear(GPIOC, GPIO7);
--- a/tests/gadget-zero/main-stm32f103-generic.c
+++ b/tests/gadget-zero/main-stm32f103-generic.c
@ -51,13 +51,15 @@ int main(void)
 	gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ,
 		GPIO_CNF_OUTPUT_PUSHPULL, GPIO12);
 	gpio_clear(GPIOA, GPIO11);
-	for (unsigned int i = 0; i < 800000; i++)
+	for (unsigned int i = 0; i < 800000; i++) {
 		__asm__("nop");
+	}

 	rcc_periph_clock_enable(RCC_OTGFS);


-	usbd_device *usbd_dev = gadget0_init(&st_usbfs_v1_usb_driver, "stm32f103-generic");
+	usbd_device *usbd_dev = gadget0_init(&st_usbfs_v1_usb_driver,
+					     "stm32f103-generic");

 	ER_DPRINTF("bootup complete\n");
 	gpio_clear(GPIOC, GPIO13);
--- a/tests/gadget-zero/main-stm32f4disco.c
+++ b/tests/gadget-zero/main-stm32f4disco.c
@ -36,17 +36,17 @@
 int main(void)
 {
 	rcc_clock_setup_hse_3v3(&hse_8mhz_3v3[CLOCK_3V3_168MHZ]);
-        rcc_periph_clock_enable(RCC_GPIOA);
-        rcc_periph_clock_enable(RCC_OTGFS);
+	rcc_periph_clock_enable(RCC_GPIOA);
+	rcc_periph_clock_enable(RCC_OTGFS);

-        gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE,
-                        GPIO9 | GPIO11 | GPIO12);
-        gpio_set_af(GPIOA, GPIO_AF10, GPIO9 | GPIO11 | GPIO12);
+	gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE,
+			GPIO9 | GPIO11 | GPIO12);
+	gpio_set_af(GPIOA, GPIO_AF10, GPIO9 | GPIO11 | GPIO12);

 	/* LEDS on discovery board */
-        rcc_periph_clock_enable(RCC_GPIOD);
-        gpio_mode_setup(GPIOD, GPIO_MODE_OUTPUT,
-                        GPIO_PUPD_NONE, GPIO12 | GPIO13 | GPIO14 | GPIO15);
+	rcc_periph_clock_enable(RCC_GPIOD);
+	gpio_mode_setup(GPIOD, GPIO_MODE_OUTPUT,
+			GPIO_PUPD_NONE, GPIO12 | GPIO13 | GPIO14 | GPIO15);

 	usbd_device *usbd_dev = gadget0_init(&otgfs_usb_driver, "stm32f4disco");

--- a/tests/gadget-zero/main-stm32l053disco.c
+++ b/tests/gadget-zero/main-stm32l053disco.c
@ -26,7 +26,7 @@
 #include <stdio.h>
 #include "usb-gadget0.h"

-// no trace on cm0 #define ER_DEBUG
+/* no trace on cm0 #define ER_DEBUG */
 #ifdef ER_DEBUG
 #define ER_DPRINTF(fmt, ...) \
    do { printf(fmt, ## __VA_ARGS__); } while (0)
@ -36,7 +36,8 @@
 #endif

 #include "trace.h"
-void trace_send_blocking8(int stimulus_port, char c) {
+void trace_send_blocking8(int stimulus_port, char c)
+{
 	(void)stimulus_port;
 	(void)c;
 }
@ -44,8 +45,8 @@ void trace_send_blocking8(int stimulus_port, char c) {
 int main(void)
 {
 	/* LED for boot progress */
-        rcc_periph_clock_enable(RCC_GPIOA);
-        gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO5);
+	rcc_periph_clock_enable(RCC_GPIOA);
+	gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO5);
 	gpio_set(GPIOA, GPIO5);

 	/* jump up to 16mhz, leave PLL setup for later. */
@ -56,8 +57,8 @@ int main(void)
 	/* HSI48 needs the vrefint turned on */
 	rcc_periph_clock_enable(RCC_SYSCFG);
 	SYSCFG_CFGR3 |= SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT;
-	while(!(SYSCFG_CFGR3 & SYSCFG_CFGR3_REF_HSI48_RDYF));
-	
+	while (!(SYSCFG_CFGR3 & SYSCFG_CFGR3_REF_HSI48_RDYF));
+
 	/* For USB, but can't use HSI48 as a sysclock on L0 */
 	crs_autotrim_usb_enable();
 	rcc_set_hsi48_source_rc48();
@ -65,7 +66,8 @@ int main(void)
 	rcc_osc_on(HSI48);
 	rcc_wait_for_osc_ready(HSI48);

-	usbd_device *usbd_dev = gadget0_init(&st_usbfs_v2_usb_driver, "stm32l053disco");
+	usbd_device *usbd_dev = gadget0_init(&st_usbfs_v2_usb_driver,
+					     "stm32l053disco");

 	ER_DPRINTF("bootup complete\n");
 	gpio_clear(GPIOA, GPIO5);
--- a/tests/gadget-zero/main-stm32l1-generic.c
+++ b/tests/gadget-zero/main-stm32l1-generic.c
@ -34,19 +34,19 @@
    do { } while (0)
 #endif

-const clock_scale_t this_clock_config =
-        { /* 32MHz PLL from 8MHz HSE */
-                .pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
-                .pll_mul = RCC_CFGR_PLLMUL_MUL12,
-                .pll_div = RCC_CFGR_PLLDIV_DIV3,
-                .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
-                .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
-                .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
-                .voltage_scale = RANGE1,
-                .flash_config = FLASH_ACR_LATENCY_1WS,
-                .apb1_frequency = 32000000,
-                .apb2_frequency = 32000000,
-        };
+const clock_scale_t this_clock_config = {
+		/* 32MHz PLL from 8MHz HSE */
+		.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
+		.pll_mul = RCC_CFGR_PLLMUL_MUL12,
+		.pll_div = RCC_CFGR_PLLDIV_DIV3,
+		.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
+		.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
+		.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
+		.voltage_scale = RANGE1,
+		.flash_config = FLASH_ACR_LATENCY_1WS,
+		.apb1_frequency = 32000000,
+		.apb2_frequency = 32000000,
+	};


 int main(void)
@ -57,7 +57,8 @@ int main(void)
 	gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO1);
 	gpio_set(GPIOB, GPIO1);

-	usbd_device *usbd_dev = gadget0_init(&st_usbfs_v1_usb_driver, "stm32l1-generic");
+	usbd_device *usbd_dev = gadget0_init(&st_usbfs_v1_usb_driver,
+					     "stm32l1-generic");

 	ER_DPRINTF("bootup complete\n");
 	gpio_clear(GPIOB, GPIO1);
--- a/tests/gadget-zero/usb-gadget0.c
+++ b/tests/gadget-zero/usb-gadget0.c
@ -111,7 +111,7 @@ static const struct usb_interface_descriptor iface_loopback[] = {
 	{
 		.bLength = USB_DT_INTERFACE_SIZE,
 		.bDescriptorType = USB_DT_INTERFACE,
-		.bInterfaceNumber = 0, // still 0, as it's a different config...?
+		.bInterfaceNumber = 0, /* still 0, as it's a different config...? */
 		.bAlternateSetting = 0,
 		.bNumEndpoints = 2,
 		.bInterfaceClass = USB_CLASS_VENDOR,
@ -141,7 +141,7 @@ static const struct usb_config_descriptor config[] = {
 		.wTotalLength = 0,
 		.bNumInterfaces = 1,
 		.bConfigurationValue = GZ_CFG_SOURCESINK,
-		.iConfiguration = 4, // string index
+		.iConfiguration = 4, /* string index */
 		.bmAttributes = 0x80,
 		.bMaxPower = 0x32,
 		.interface = ifaces_sourcesink,
@ -152,7 +152,7 @@ static const struct usb_config_descriptor config[] = {
 		.wTotalLength = 0,
 		.bNumInterfaces = 1,
 		.bConfigurationValue = GZ_CFG_LOOPBACK,
-		.iConfiguration = 5, // string index
+		.iConfiguration = 5, /* string index */
 		.bmAttributes = 0x80,
 		.bMaxPower = 0x32,
 		.interface = ifaces_loopback,
@ -160,7 +160,7 @@ static const struct usb_config_descriptor config[] = {
 };

 static char serial[] = "0123456789.0123456789.0123456789";
-static const char * usb_strings[] = {
+static const char *usb_strings[] = {
 	"libopencm3",
 	"Gadget-Zero",
 	serial,
@ -184,8 +184,8 @@ static struct {
 static void gadget0_ss_out_cb(usbd_device *usbd_dev, uint8_t ep)
 {
 	(void) ep;
-	// TODO - if you're really keen, perf test this. tiva implies it matters
-	//char buf[64] __attribute__ ((aligned(4)));
+	/* TODO - if you're really keen, perf test this. tiva implies it matters */
+	/* char buf[64] __attribute__ ((aligned(4))); */
 	char buf[64];
 	trace_send_blocking8(0, 'O');
 	uint16_t x = usbd_ep_read_packet(usbd_dev, ep, buf, sizeof(buf));
@ -214,21 +214,21 @@ static void gadget0_ss_in_cb(usbd_device *usbd_dev, uint8_t ep)
 	if (x != sizeof(buf)) {
 		ER_DPRINTF("failed to write?: %d\n", x);
 	}
-	//assert(x == sizeof(buf));
+	/*assert(x == sizeof(buf));*/
 }

 static void gadget0_rx_cb_loopback(usbd_device *usbd_dev, uint8_t ep)
 {
 	(void) usbd_dev;
 	ER_DPRINTF("loop rx %x\n", ep);
-	// TODO - unimplemented - consult linux source on proper behaviour
+	/* TODO - unimplemented - consult linux source on proper behaviour */
 }

 static void gadget0_tx_cb_loopback(usbd_device *usbd_dev, uint8_t ep)
 {
 	(void) usbd_dev;
 	ER_DPRINTF("loop tx %x\n", ep);
-	// TODO - unimplemented - consult linux source on proper behaviour
+	/* TODO - unimplemented - consult linux source on proper behaviour */
 }

 static int gadget0_control_request(usbd_device *usbd_dev,
@ -242,9 +242,10 @@ static int gadget0_control_request(usbd_device *usbd_dev,
 	(void) buf;
 	(void) len;
 	ER_DPRINTF("ctrl breq: %x, bmRT: %x, windex :%x, wlen: %x, wval :%x\n",
-		req->bRequest, req->bmRequestType, req->wIndex, req->wLength, req->wValue);
+		req->bRequest, req->bmRequestType, req->wIndex, req->wLength,
+		req->wValue);

-	// TODO - what do the return values mean again?
+	/* TODO - what do the return values mean again? */
 	switch (req->bRequest) {
 	case GZ_REQ_SET_PATTERN:
 		state.pattern_counter = 0;
@ -301,7 +302,7 @@ static void gadget0_set_config(usbd_device *usbd_dev, uint16_t wValue)
 	}
 }

-usbd_device* gadget0_init(const usbd_driver *driver, const char *userserial)
+usbd_device *gadget0_init(const usbd_driver *driver, const char *userserial)
 {
 #ifdef ER_DEBUG
 	setbuf(stdout, NULL);
--- a/tests/gadget-zero/usb-gadget0.h
+++ b/tests/gadget-zero/usb-gadget0.h
@ -30,6 +30,6 @@
 *	to the hardware.
 * @return the usbd_device created.
 */
-usbd_device* gadget0_init(const usbd_driver *driver, const char *userserial);
+usbd_device *gadget0_init(const usbd_driver *driver, const char *userserial);

 #endif
--- a/tests/shared/trace.c
+++ b/tests/shared/trace.c
@ -4,32 +4,34 @@
 #include <libopencm3/cm3/itm.h>
 #include "trace.h"

-void trace_send_blocking8(int stimulus_port, char c) {
+void trace_send_blocking8(int stimulus_port, char c)
+{
 	if (!(ITM_TER[0] & (1<<stimulus_port))) {
 		return;
 	}
-	while (!(ITM_STIM8(stimulus_port) & ITM_STIM_FIFOREADY))
-		;
+	while (!(ITM_STIM8(stimulus_port) & ITM_STIM_FIFOREADY));
 	ITM_STIM8(stimulus_port) = c;
 }

-void trace_send8(int stimulus_port, char val) {
+void trace_send8(int stimulus_port, char val)
+{
 	if (!(ITM_TER[0] & (1<<stimulus_port))) {
 		return;
 	}
 	ITM_STIM8(stimulus_port) = val;
 }

-void trace_send_blocking16(int stimulus_port, uint16_t val) {
+void trace_send_blocking16(int stimulus_port, uint16_t val)
+{
 	if (!(ITM_TER[0] & (1<<stimulus_port))) {
 		return;
 	}
-	while (!(ITM_STIM16(stimulus_port) & ITM_STIM_FIFOREADY))
-		;
+	while (!(ITM_STIM16(stimulus_port) & ITM_STIM_FIFOREADY));
 	ITM_STIM16(stimulus_port) = val;
 }

-void trace_send16(int stimulus_port, uint16_t val) {
+void trace_send16(int stimulus_port, uint16_t val)
+{
 	if (!(ITM_TER[0] & (1<<stimulus_port))) {
 		return;
 	}
@ -37,16 +39,17 @@ void trace_send16(int stimulus_port, uint16_t val) {
 }


-void trace_send_blocking32(int stimulus_port, uint32_t val) {
+void trace_send_blocking32(int stimulus_port, uint32_t val)
+{
 	if (!(ITM_TER[0] & (1<<stimulus_port))) {
 		return;
 	}
-	while (!(ITM_STIM32(stimulus_port) & ITM_STIM_FIFOREADY))
-		;
+	while (!(ITM_STIM32(stimulus_port) & ITM_STIM_FIFOREADY));
 	ITM_STIM32(stimulus_port) = val;
 }

-void trace_send32(int stimulus_port, uint32_t val) {
+void trace_send32(int stimulus_port, uint32_t val)
+{
 	if (!(ITM_TER[0] & (1<<stimulus_port))) {
 		return;
 	}
--- a/tests/shared/trace.h
+++ b/tests/shared/trace.h
@ -1,4 +1,4 @@
-/* 
+/*
 * File:   trace.h
 * Author: karlp
 *