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@ -61,12 +61,9 @@ |
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#define FLASH_OPTCR1 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18) |
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/*@}*/ |
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/** @defgroup flash_acr_values FLASH_ACR values
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* @ingroup flash_registers |
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* @brief Access Control register values |
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/** @defgroup flash_latency FLASH Wait States
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@ingroup flash_defines |
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@{*/ |
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#define FLASH_ACR_LATENCY_SHIFT 0 |
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#define FLASH_ACR_LATENCY_MASK 0x0f |
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#define FLASH_ACR_LATENCY(w) ((w) & FLASH_ACR_LATENCY_MASK) |
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#define FLASH_ACR_LATENCY_0WS 0x00 |
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#define FLASH_ACR_LATENCY_1WS 0x01 |
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@ -76,8 +73,16 @@ |
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#define FLASH_ACR_LATENCY_5WS 0x05 |
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#define FLASH_ACR_LATENCY_6WS 0x06 |
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#define FLASH_ACR_LATENCY_7WS 0x07 |
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#define FLASH_ACR_PRFTEN (1 << 8) |
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/*@}*/ |
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#define FLASH_ACR_LATENCY_SHIFT 0 |
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#define FLASH_ACR_LATENCY_MASK 0x0f |
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/** @defgroup flash_acr_values FLASH_ACR values
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* @ingroup flash_registers |
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* @brief Access Control register values |
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* @{*/ |
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#define FLASH_ACR_PRFTEN (1 << 8) |
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/**@}*/ |
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/* --- FLASH_SR values ----------------------------------------------------- */ |
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