efm32: cmu: support switching HFCLK to USHFRCODIV2

Allow for the high frequency clock that controlls things such as the
main CPU to be switched over to USHFRCODIV2.  This is a 24 MHz PLL
that is trimmed using clock recovery from the USB signal, and is
accurate to within 1% of 24 MHz.

Signed-off-by: Sean Cross <sean@xobs.io>

lib/efm32/hg/cmu.c

@@ -105,6 +105,9 @@ void cmu_osc_on(enum cmu_osc osc)
 	case AUXHFRCO:
 		CMU_OSCENCMD = CMU_OSCENCMD_AUXHFRCOEN;
 		break;
+	default:
+		/* not applicable */
+		break;
 	}
 }
 
@@ -133,6 +136,9 @@ void cmu_osc_off(enum cmu_osc osc)
 	case AUXHFRCO:
 		CMU_OSCENCMD = CMU_OSCENCMD_AUXHFRCODIS;
 		break;
+	default:
+		/* not applicable */
+		break;
 	}
 }
 
@@ -163,6 +169,9 @@ bool cmu_osc_ready_flag(enum cmu_osc osc)
 	case AUXHFRCO:
 		return (CMU_STATUS & CMU_STATUS_AUXHFRCORDY) != 0;
 		break;
+	default:
+		/* not applicable */
+		break;
 	}
 
 	return false;
@@ -193,6 +202,9 @@ void cmu_wait_for_osc_ready(enum cmu_osc osc)
 	case AUXHFRCO:
 		while ((CMU_STATUS & CMU_STATUS_AUXHFRCORDY) == 0);
 		break;
+	default:
+		/* not applicable */
+		break;
 	}
 }
 
@@ -218,6 +230,9 @@ void cmu_set_hfclk_source(enum cmu_osc osc)
 	case LFRCO:
 		CMU_CMD = CMU_CMD_HFCLKSEL_LFRCO;
 		break;
+	case USHFRCODIV2:
+		CMU_CMD = CMU_CMD_HFCLKSEL_USHFRCODIV2;
+		break;
 	default:
 		/* not applicable */
 		return;
@@ -239,6 +254,8 @@ enum cmu_osc cmu_get_hfclk_source(void)
 		return HFXO;
 	} else if (status & CMU_STATUS_HFRCOSEL) {
 		return HFRCO;
+	} else if (status & CMU_STATUS_USHFRCODIV2SEL) {
+		return USHFRCODIV2;
 	}
 
 	/* never reached */