diff --git a/tests/gadget-zero/main-stm32f072disco.c b/tests/gadget-zero/main-stm32f072disco.c
index 8a7807d8..6d382748 100644
--- a/tests/gadget-zero/main-stm32f072disco.c
+++ b/tests/gadget-zero/main-stm32f072disco.c
@@ -46,7 +46,7 @@ int main(void)
 {
 	rcc_clock_setup_in_hsi48_out_48mhz();
 	crs_autotrim_usb_enable();
-	rcc_set_usbclk_source(HSI48);
+	rcc_set_usbclk_source(RCC_HSI48);
 
 	/* LED on for boot progress */
 	rcc_periph_clock_enable(RCC_GPIOC);
diff --git a/tests/gadget-zero/main-stm32f4disco.c b/tests/gadget-zero/main-stm32f4disco.c
index ab6e42c3..b87d0baf 100644
--- a/tests/gadget-zero/main-stm32f4disco.c
+++ b/tests/gadget-zero/main-stm32f4disco.c
@@ -35,7 +35,7 @@
 
 int main(void)
 {
-	rcc_clock_setup_hse_3v3(&hse_8mhz_3v3[CLOCK_3V3_168MHZ]);
+	rcc_clock_setup_hse_3v3(&rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_168MHZ]);
 	rcc_periph_clock_enable(RCC_GPIOA);
 	rcc_periph_clock_enable(RCC_OTGFS);
 
diff --git a/tests/gadget-zero/main-stm32l053disco.c b/tests/gadget-zero/main-stm32l053disco.c
index 144318f6..891256d7 100644
--- a/tests/gadget-zero/main-stm32l053disco.c
+++ b/tests/gadget-zero/main-stm32l053disco.c
@@ -50,9 +50,9 @@ int main(void)
 	gpio_set(GPIOA, GPIO5);
 
 	/* jump up to 16mhz, leave PLL setup for later. */
-	rcc_osc_on(HSI16);
-	rcc_wait_for_osc_ready(HSI16);
-	rcc_set_sysclk_source(HSI16);
+	rcc_osc_on(RCC_HSI16);
+	rcc_wait_for_osc_ready(RCC_HSI16);
+	rcc_set_sysclk_source(RCC_HSI16);
 
 	/* HSI48 needs the vrefint turned on */
 	rcc_periph_clock_enable(RCC_SYSCFG);
@@ -63,8 +63,8 @@ int main(void)
 	crs_autotrim_usb_enable();
 	rcc_set_hsi48_source_rc48();
 
-	rcc_osc_on(HSI48);
-	rcc_wait_for_osc_ready(HSI48);
+	rcc_osc_on(RCC_HSI48);
+	rcc_wait_for_osc_ready(RCC_HSI48);
 
 	usbd_device *usbd_dev = gadget0_init(&st_usbfs_v2_usb_driver,
 					     "stm32l053disco");
diff --git a/tests/gadget-zero/main-stm32l1-generic.c b/tests/gadget-zero/main-stm32l1-generic.c
index b22353a1..9d707468 100644
--- a/tests/gadget-zero/main-stm32l1-generic.c
+++ b/tests/gadget-zero/main-stm32l1-generic.c
@@ -34,7 +34,7 @@
     do { } while (0)
 #endif
 
-const clock_scale_t this_clock_config = {
+const struct rcc_clock_scale this_clock_config = {
 		/* 32MHz PLL from 8MHz HSE */
 		.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
 		.pll_mul = RCC_CFGR_PLLMUL_MUL12,
@@ -42,7 +42,7 @@ const clock_scale_t this_clock_config = {
 		.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
 		.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
 		.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
-		.voltage_scale = RANGE1,
+		.voltage_scale = PWR_SCALE1,
 		.flash_config = FLASH_ACR_LATENCY_1WS,
 		.apb1_frequency = 32000000,
 		.apb2_frequency = 32000000,