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@ -34,7 +34,7 @@ |
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do { } while (0) |
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#endif |
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const clock_scale_t this_clock_config = { |
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const struct rcc_clock_scale this_clock_config = { |
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/* 32MHz PLL from 8MHz HSE */ |
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.pll_source = RCC_CFGR_PLLSRC_HSE_CLK, |
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.pll_mul = RCC_CFGR_PLLMUL_MUL12, |
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@ -42,7 +42,7 @@ const clock_scale_t this_clock_config = { |
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.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, |
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.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV, |
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.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, |
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.voltage_scale = RANGE1, |
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.voltage_scale = PWR_SCALE1, |
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.flash_config = FLASH_ACR_LATENCY_1WS, |
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.apb1_frequency = 32000000, |
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.apb2_frequency = 32000000, |
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