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@ -49,15 +49,12 @@ |
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/* --- SYSTICK registers --------------------------------------------------- */ |
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/* Control and status register (STK_CTRL) */ |
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#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) |
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#define STK_CSR MMIO32(SYS_TICK_BASE + 0x00) |
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/* reload value register (STK_LOAD) */ |
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#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) |
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#define STK_RVR MMIO32(SYS_TICK_BASE + 0x04) |
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/* current value register (STK_VAL) */ |
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#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) |
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#define STK_CVR MMIO32(SYS_TICK_BASE + 0x08) |
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/* calibration value register (STK_CALIB) */ |
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@ -66,14 +63,10 @@ |
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/* --- STK_CSR values ------------------------------------------------------ */ |
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/* Bits [31:17] Reserved, must be kept cleared. */ |
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/* COUNTFLAG: */ |
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#define STK_CTRL_COUNTFLAG (1 << 16) |
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#define STK_CSR_COUNTFLAG (1 << 16) |
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/* Bits [15:3] Reserved, must be kept cleared. */ |
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/* CLKSOURCE: Clock source selection */ |
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#define STK_CTRL_CLKSOURCE_LSB 2 |
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#define STK_CTRL_CLKSOURCE (1 << STK_CTRL_CLKSOURCE_LSB) |
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#define STK_CSR_CLKSOURCE_LSB 2 |
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#define STK_CSR_CLKSOURCE (1 << STK_CSR_CLKSOURCE_LSB) |
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@ -85,19 +78,14 @@ |
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#define STK_CSR_CLKSOURCE_EXT (0 << STK_CSR_CLKSOURCE_LSB) |
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#define STK_CSR_CLKSOURCE_AHB (1 << STK_CSR_CLKSOURCE_LSB) |
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#else |
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#define STK_CTRL_CLKSOURCE_AHB_DIV8 (0 << STK_CSR_CLKSOURCE_LSB) |
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#define STK_CTRL_CLKSOURCE_AHB (1 << STK_CSR_CLKSOURCE_LSB) |
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#define STK_CSR_CLKSOURCE_AHB_DIV8 (0 << STK_CSR_CLKSOURCE_LSB) |
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#define STK_CSR_CLKSOURCE_AHB (1 << STK_CSR_CLKSOURCE_LSB) |
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#endif |
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/**@}*/ |
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/* TICKINT: SysTick exception request enable */ |
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#define STK_CTRL_TICKINT (1 << 1) |
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#define STK_CSR_TICKINT (1 << 1) |
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/* ENABLE: Counter enable */ |
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#define STK_CTRL_ENABLE (1 << 0) |
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#define STK_CSR_ENABLE (1 << 0) |
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/* --- STK_RVR values ------------------------------------------------------ */ |
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