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Merge pull request #73 RNG 

Merge remote-tracking branch 'oojah/master'
pull/74/merge
Piotr Esden-Tempski 12 years ago
parent
1f9911e35b b9180a81d8
commit
c03cbc41a1
6 changed files with 102 additions and 54 deletions
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  1. 2
      examples/stm32/f4/stm32f4-discovery/random/random.c
  2. 22
      include/libopencm3/lpc17xx/gpio.h
  3. 2
      include/libopencm3/lpc17xx/memorymap.h
  4. 61
      include/libopencm3/stm32/common/rng_common_f24.h
  5. 24
      include/libopencm3/stm32/f2/rng.h
  6. 45
      include/libopencm3/stm32/f4/rng.h

2
examples/stm32/f4/stm32f4-discovery/random/random.c
View File

@ -40,7 +40,7 @@ static void rng_setup(void)
/* Enable the random number generation by setting the RNGEN bit in the RNG_CR
register. This activates the analog part, the RNG_LFSR and the error detector.
*/
RNG_CR |= RNG_CR_EN;
RNG_CR |= RNG_CR_RNGEN;
}
static void gpio_setup(void)

22
include/libopencm3/lpc17xx/gpio.h
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@ -110,27 +110,27 @@
/* GPIO interrupt register map */
/* Interrupt enable rising edge */
#define GPIO0_IER MMIO32(GPIOINTERRPUT_BASE + 0x90)
#define GPIO2_IER MMIO32(GPIOINTERRPUT_BASE + 0xB0)
#define GPIO0_IER MMIO32(GPIOINTERRUPT_BASE + 0x90)
#define GPIO2_IER MMIO32(GPIOINTERRUPT_BASE + 0xB0)
/* Interrupt enable falling edge */
#define GPIO0_IEF MMIO32(GPIOINTERRPUT_BASE + 0x94)
#define GPIO2_IEF MMIO32(GPIOINTERRPUT_BASE + 0xB4)
#define GPIO0_IEF MMIO32(GPIOINTERRUPT_BASE + 0x94)
#define GPIO2_IEF MMIO32(GPIOINTERRUPT_BASE + 0xB4)
/* Interrupt status rising edge */
#define GPIO0_ISR MMIO32(GPIOINTERRPUT_BASE + 0x84)
#define GPIO2_ISR MMIO32(GPIOINTERRPUT_BASE + 0xA4)
#define GPIO0_ISR MMIO32(GPIOINTERRUPT_BASE + 0x84)
#define GPIO2_ISR MMIO32(GPIOINTERRUPT_BASE + 0xA4)
/* Interrupt status falling edge */
#define GPIO0_ISF MMIO32(GPIOINTERRPUT_BASE + 0x88)
#define GPIO2_ISF MMIO32(GPIOINTERRPUT_BASE + 0xA8)
#define GPIO0_ISF MMIO32(GPIOINTERRUPT_BASE + 0x88)
#define GPIO2_ISF MMIO32(GPIOINTERRUPT_BASE + 0xA8)
/* Interrupt clear */
#define GPIO0_IC MMIO32(GPIOINTERRPUT_BASE + 0x8C)
#define GPIO1_IC MMIO32(GPIOINTERRPUT_BASE + 0xAC)
#define GPIO0_IC MMIO32(GPIOINTERRUPT_BASE + 0x8C)
#define GPIO1_IC MMIO32(GPIOINTERRUPT_BASE + 0xAC)
/* Overall interrupt status */
#define GPIO_IS MMIO32(GPIOINTERRPUT_BASE + 0x80)
#define GPIO_IS MMIO32(GPIOINTERRUPT_BASE + 0x80)
BEGIN_DECLS

2
include/libopencm3/lpc17xx/memorymap.h
View File

@ -42,7 +42,7 @@
#define I2C0_BASE (PERIPH_BASE_APB0 + 0x1c000)
#define SPI_BASE (PERIPH_BASE_APB0 + 0x20000)
#define RTC_BASE (PERIPH_BASE_APB0 + 0x24000)
#define GPIOINTERRPUT_BASE (PERIPH_BASE_APB0 + 0x28000)
#define GPIOINTERRUPT_BASE (PERIPH_BASE_APB0 + 0x28000)
#define PINCONNECT_BASE (PERIPH_BASE_APB0 + 0x2c000)
#define SSP1_BASE (PERIPH_BASE_APB0 + 0x30000)
#define ADC_BASE (PERIPH_BASE_APB0 + 0x34000)

61
include/libopencm3/stm32/common/rng_common_f24.h
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@ -0,0 +1,61 @@
/*
* This file is part of the libopencm3 project.
*
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_RNG_COMMON_F24_H
#define LIBOPENCM3_RNG_COMMON_F24_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/* --- Random number generator registers ----------------------------------- */
/* Control register */
#define RNG_CR MMIO32(RNG_BASE + 0x00)
/* Status register */
#define RNG_SR MMIO32(RNG_BASE + 0x04)
/* Data register */
#define RNG_DR MMIO32(RNG_BASE + 0x08)
/* --- RNG_CR values ------------------------------------------------------- */
/* RNG ENABLE */
#define RNG_CR_RNGEN (1 << 2)
/* RNG interupt enable */
#define RNG_CR_IE (1 << 3)
/* --- RNG_SR values ------------------------------------------------------- */
/* Data ready */
#define RNG_SR_DRDY (1 << 0)
/* Clock error current status */
#define RNG_SR_CECS (1 << 1)
/* Seed error current status */
#define RNG_SR_SECS (1 << 2)
/* Clock error interup status */
#define RNG_SR_CEIS (1 << 5)
/* Seed error interup status */
#define RNG_SR_SEIS (1 << 6)
#endif

24
include/libopencm3/stm32/f2/rng.h
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@ -0,0 +1,24 @@
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_RNG_F2_H
#define LIBOPENCM3_RNG_F2_H
#include <libopencm3/stm32/f2/memorymap.h>
#include <libopencm3/stm32/common/rng_common_f24.h>
#endif

45
include/libopencm3/stm32/f4/rng.h
View File

@ -1,7 +1,6 @@
/*
* This file is part of the libopencm3 project.
*
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@ -16,46 +15,10 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_RNG_H
#define LIBOPENCM3_RNG_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/* --- Random number generator registers ----------------------------------- */
/* Control register */
#define RNG_CR MMIO32(RNG_BASE + 0x00)
/* Status register */
#define RNG_SR MMIO32(RNG_BASE + 0x04)
/* Data register */
#define RNG_DR MMIO32(RNG_BASE + 0x08)
/* --- RNG_CR values ------------------------------------------------------- */
/* RNG ENABLE */
#define RNG_CR_EN (1 << 2)
/* RNG interupt enable */
#define RNG_CR_IE (1 << 3)
/* --- RNG_SR values ------------------------------------------------------- */
/* Data ready */
#define RNG_SR_DRDY (1 << 0)
/* Clock error current status */
#define RNG_SR_CECS (1 << 1)
/* Seed error current status */
#define RNG_SR_SECS (1 << 2)
/* Clock error interup status */
#define RNG_SR_CEIS (1 << 5)
#ifndef LIBOPENCM3_RNG_F4_H
#define LIBOPENCM3_RNG_F4_H
/* Seed error interup status */
#define RNG_SR_SEIS (1 << 6)
#include <libopencm3/stm32/f4/memorymap.h>
#include <libopencm3/stm32/common/rng_common_f24.h>
#endif

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