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@ -1324,9 +1324,9 @@ |
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* @li CLOCK_DEEP_SLEEP - Deep-Sleep Mode |
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* @li CLOCK_DEEP_SLEEP - Deep-Sleep Mode |
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*/ |
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*/ |
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enum msp432_clock_mode { |
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enum msp432_clock_mode { |
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CLOCK_RUN = 0x600, |
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CLOCK_RUN = 0x600, |
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CLOCK_SLEEP = 0x700, |
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CLOCK_SLEEP = 0x700, |
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CLOCK_DEEP_SLEEP = 0x800 |
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CLOCK_DEEP_SLEEP = 0x800 |
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}; |
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}; |
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/**
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/**
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@ -1339,8 +1339,8 @@ enum msp432_clock_mode { |
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* is powered and receives a clock regardless of the value of power mode. |
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* is powered and receives a clock regardless of the value of power mode. |
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*/ |
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*/ |
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enum msp432_power_mode { |
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enum msp432_power_mode { |
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POWER_DISABLE = false, |
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POWER_DISABLE = false, |
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POWER_ENABLE = true |
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POWER_ENABLE = true |
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}; |
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}; |
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#define _REG_BIT(base, bit) (((base) << 5) + (bit)) |
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#define _REG_BIT(base, bit) (((base) << 5) + (bit)) |
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@ -1354,95 +1354,95 @@ enum msp432_power_mode { |
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*/ |
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*/ |
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enum msp432_periph { |
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enum msp432_periph { |
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PERIPH_WD0 = _REG_BIT(0x00, 0), |
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PERIPH_WD0 = _REG_BIT(0x00, 0), |
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PERIPH_WD1, |
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PERIPH_WD1, |
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PERIPH_TIMER0 = _REG_BIT(0x04, 0), |
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PERIPH_TIMER0 = _REG_BIT(0x04, 0), |
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PERIPH_TIMER1, |
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PERIPH_TIMER1, |
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PERIPH_TIMER2, |
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PERIPH_TIMER2, |
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PERIPH_TIMER3, |
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PERIPH_TIMER3, |
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PERIPH_TIMER4, |
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PERIPH_TIMER4, |
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PERIPH_TIMER5, |
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PERIPH_TIMER5, |
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PERIPH_TIMER6, |
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PERIPH_TIMER6, |
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PERIPH_TIMER7, |
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PERIPH_TIMER7, |
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PERIPH_GPIOA = _REG_BIT(0x08, 0), |
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PERIPH_GPIOA = _REG_BIT(0x08, 0), |
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PERIPH_GPIOB, |
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PERIPH_GPIOB, |
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PERIPH_GPIOC, |
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PERIPH_GPIOC, |
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PERIPH_GPIOD, |
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PERIPH_GPIOD, |
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PERIPH_GPIOE, |
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PERIPH_GPIOE, |
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PERIPH_GPIOF, |
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PERIPH_GPIOF, |
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PERIPH_GPIOG, |
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PERIPH_GPIOG, |
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PERIPH_GPIOH, |
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PERIPH_GPIOH, |
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PERIPH_GPIOJ, |
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PERIPH_GPIOJ, |
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PERIPH_GPIOK, |
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PERIPH_GPIOK, |
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PERIPH_GPIOL, |
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PERIPH_GPIOL, |
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PERIPH_GPIOM, |
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PERIPH_GPIOM, |
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PERIPH_GPION, |
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PERIPH_GPION, |
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PERIPH_GPIOP, |
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PERIPH_GPIOP, |
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PERIPH_GPIOQ, |
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PERIPH_GPIOQ, |
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PERIPH_GPIOR, |
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PERIPH_GPIOR, |
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PERIPH_GPIOS, |
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PERIPH_GPIOS, |
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PERIPH_GPIOT, |
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PERIPH_GPIOT, |
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PERIPH_DMA = _REG_BIT(0x0C, 0), |
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PERIPH_DMA = _REG_BIT(0x0C, 0), |
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PERIPH_EPI = _REG_BIT(0x10, 0), |
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PERIPH_EPI = _REG_BIT(0x10, 0), |
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PERIPH_HIB = _REG_BIT(0x14, 0), |
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PERIPH_HIB = _REG_BIT(0x14, 0), |
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PERIPH_UART0 = _REG_BIT(0x18, 0), |
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PERIPH_UART0 = _REG_BIT(0x18, 0), |
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PERIPH_UART1, |
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PERIPH_UART1, |
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PERIPH_UART2, |
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PERIPH_UART2, |
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PERIPH_UART3, |
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PERIPH_UART3, |
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PERIPH_UART4, |
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PERIPH_UART4, |
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PERIPH_UART5, |
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PERIPH_UART5, |
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PERIPH_UART6, |
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PERIPH_UART6, |
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PERIPH_UART7, |
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PERIPH_UART7, |
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PERIPH_SSI0 = _REG_BIT(0x1C, 0), |
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PERIPH_SSI0 = _REG_BIT(0x1C, 0), |
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PERIPH_SSI1, |
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PERIPH_SSI1, |
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PERIPH_SSI2, |
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PERIPH_SSI2, |
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PERIPH_SSI3, |
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PERIPH_SSI3, |
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PERIPH_I2C0 = _REG_BIT(0x20, 0), |
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PERIPH_I2C0 = _REG_BIT(0x20, 0), |
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PERIPH_I2C1, |
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PERIPH_I2C1, |
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PERIPH_I2C2, |
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PERIPH_I2C2, |
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PERIPH_I2C3, |
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PERIPH_I2C3, |
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PERIPH_I2C4, |
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PERIPH_I2C4, |
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PERIPH_I2C5, |
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PERIPH_I2C5, |
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PERIPH_I2C6, |
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PERIPH_I2C6, |
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PERIPH_I2C7, |
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PERIPH_I2C7, |
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PERIPH_I2C8, |
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PERIPH_I2C8, |
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PERIPH_I2C9, |
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PERIPH_I2C9, |
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PERIPH_USB0 = _REG_BIT(0x28, 0), |
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PERIPH_USB0 = _REG_BIT(0x28, 0), |
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PERIPH_EPHY = _REG_BIT(0x30, 0), |
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PERIPH_EPHY = _REG_BIT(0x30, 0), |
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PERIPH_CAN0 = _REG_BIT(0x34, 0), |
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PERIPH_CAN0 = _REG_BIT(0x34, 0), |
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PERIPH_CAN1, |
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PERIPH_CAN1, |
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PERIPH_ADC0 = _REG_BIT(0x38, 0), |
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PERIPH_ADC0 = _REG_BIT(0x38, 0), |
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PERIPH_ADC1, |
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PERIPH_ADC1, |
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PERIPH_ACMP = _REG_BIT(0x3C, 0), |
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PERIPH_ACMP = _REG_BIT(0x3C, 0), |
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PERIPH_PWM = _REG_BIT(0x40, 0), |
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PERIPH_PWM = _REG_BIT(0x40, 0), |
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PERIPH_QEI = _REG_BIT(0x44, 0), |
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PERIPH_QEI = _REG_BIT(0x44, 0), |
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PERIPH_EEPROM = _REG_BIT(0x58, 0), |
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PERIPH_EEPROM = _REG_BIT(0x58, 0), |
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PERIPH_CCM = _REG_BIT(0x74, 0), |
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PERIPH_CCM = _REG_BIT(0x74, 0), |
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PERIPH_LCD = _REG_BIT(0x90, 0), |
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PERIPH_LCD = _REG_BIT(0x90, 0), |
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PERIPH_OWIRE = _REG_BIT(0x98, 0), |
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PERIPH_OWIRE = _REG_BIT(0x98, 0), |
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PERIPH_EMAC = _REG_BIT(0x9C, 0), |
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PERIPH_EMAC = _REG_BIT(0x9C, 0), |
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PERIPH_PRB = _REG_BIT(0xA0, 0) |
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PERIPH_PRB = _REG_BIT(0xA0, 0) |
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}; |
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}; |
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#undef _REG_BIT |
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#undef _REG_BIT |
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@ -1452,9 +1452,9 @@ enum msp432_periph { |
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BEGIN_DECLS |
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BEGIN_DECLS |
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void sysctl_periph_clock_enable(enum msp432_clock_mode clock_mode, |
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void sysctl_periph_clock_enable(enum msp432_clock_mode clock_mode, |
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enum msp432_periph periph); |
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enum msp432_periph periph); |
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void sysctl_periph_clock_disable(enum msp432_clock_mode clock_mode, |
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void sysctl_periph_clock_disable(enum msp432_clock_mode clock_mode, |
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enum msp432_periph periph); |
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enum msp432_periph periph); |
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void sysctl_periph_reset(enum msp432_periph periph); |
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void sysctl_periph_reset(enum msp432_periph periph); |
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void sysctl_periph_clear_reset(enum msp432_periph periph); |
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void sysctl_periph_clear_reset(enum msp432_periph periph); |
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@ -1462,7 +1462,7 @@ void sysctl_periph_clear_reset(enum msp432_periph periph); |
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bool sysctl_periph_is_present(enum msp432_periph periph); |
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bool sysctl_periph_is_present(enum msp432_periph periph); |
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bool sysctl_periph_is_ready(enum msp432_periph periph); |
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bool sysctl_periph_is_ready(enum msp432_periph periph); |
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void sysctl_periph_set_power_state(enum msp432_power_mode power_mode, |
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void sysctl_periph_set_power_state(enum msp432_power_mode power_mode, |
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enum msp432_periph periph); |
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enum msp432_periph periph); |
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END_DECLS |
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END_DECLS |
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