stm32f1: Add missing peripheral base address for F100

include/libopencm3/stm32/f1/memorymap.h

@@ -66,7 +66,8 @@
 #define BACKUP_REGS_BASE		(PERIPH_BASE_APB1 + 0x6c00)
 #define POWER_CONTROL_BASE		(PERIPH_BASE_APB1 + 0x7000)
 #define DAC_BASE			(PERIPH_BASE_APB1 + 0x7400)
-/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 FFFF): Reserved */
+#define CEC_BASE			(PERIPH_BASE_APB1 + 0x7800)
+/* PERIPH_BASE_APB1 + 0x7c00 (0x4000 7c00 - 0x4000 FFFF): Reserved */
 
 /* APB2 */
 #define AFIO_BASE			(PERIPH_BASE_APB2 + 0x0000)
@@ -85,7 +86,9 @@
 #define TIM8_BASE			(PERIPH_BASE_APB2 + 0x3400)
 #define USART1_BASE			(PERIPH_BASE_APB2 + 0x3800)
 #define ADC3_BASE			(PERIPH_BASE_APB2 + 0x3c00)
-/* PERIPH_BASE_APB2 + 0x4000 (0x4001 4000 - 0x4001 4FFF): Reserved */
+#define TIM15_BASE			(PERIPH_BASE_APB2 + 0x4000)
+#define TIM16_BASE			(PERIPH_BASE_APB2 + 0x4400)
+#define TIM17_BASE			(PERIPH_BASE_APB2 + 0x4800)
 #define TIM9_BASE			(PERIPH_BASE_APB2 + 0x4c00)
 #define TIM10_BASE			(PERIPH_BASE_APB2 + 0x5000)
 #define TIM11_BASE			(PERIPH_BASE_APB2 + 0x5400)