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@ -490,7 +490,7 @@ void dma_set_dma_flow_control(u32 dma, u8 stream) |
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void dma_enable_transfer_error_interrupt(u32 dma, u8 stream) |
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{ |
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dma_clear_interrupt_flags(dma, stream, DMA_ISR_TEIF); |
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dma_clear_interrupt_flags(dma, stream, DMA_TEIF); |
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DMA_SCR(dma, stream) |= DMA_SxCR_TEIE; |
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} |
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@ -515,7 +515,7 @@ void dma_disable_transfer_error_interrupt(u32 dma, u8 stream) |
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void dma_enable_half_transfer_interrupt(u32 dma, u8 stream) |
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{ |
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dma_clear_interrupt_flags(dma, stream, DMA_ISR_HTIF); |
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dma_clear_interrupt_flags(dma, stream, DMA_HTIF); |
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DMA_SCR(dma, stream) |= DMA_SxCR_HTIE; |
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} |
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@ -540,7 +540,7 @@ void dma_disable_half_transfer_interrupt(u32 dma, u8 stream) |
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void dma_enable_transfer_complete_interrupt(u32 dma, u8 stream) |
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{ |
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dma_clear_interrupt_flags(dma, stream, DMA_ISR_TCIF); |
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dma_clear_interrupt_flags(dma, stream, DMA_TCIF); |
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DMA_SCR(dma, stream) |= DMA_SxCR_TCIE; |
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} |
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@ -565,7 +565,7 @@ void dma_disable_transfer_complete_interrupt(u32 dma, u8 stream) |
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void dma_enable_direct_mode_error_interrupt(u32 dma, u8 stream) |
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{ |
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dma_clear_interrupt_flags(dma, stream, DMA_ISR_DMEIF); |
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dma_clear_interrupt_flags(dma, stream, DMA_DMEIF); |
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DMA_SCR(dma, stream) |= DMA_SxCR_DMEIE; |
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} |
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@ -590,7 +590,7 @@ void dma_disable_direct_mode_error_interrupt(u32 dma, u8 stream) |
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void dma_enable_fifo_error_interrupt(u32 dma, u8 stream) |
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{ |
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dma_clear_interrupt_flags(dma, stream, DMA_ISR_FEIF); |
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dma_clear_interrupt_flags(dma, stream, DMA_FEIF); |
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DMA_SFCR(dma, stream) |= DMA_SxFCR_FEIE; |
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} |
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