From cbb4756440fe60b09dd1e19e06178495bf9205fb Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Fri, 26 Apr 2013 12:12:03 +0930 Subject: [PATCH] As requested (6 Feb 2013) change DMA interrupt flag names in STM32/common, for dma_common_f24, to match those used in dma_common_f13. Examples compile OK --- include/libopencm3/stm32/common/dma_common_f24.h | 12 ++++++------ lib/stm32/common/dma_common_f24.c | 10 +++++----- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/include/libopencm3/stm32/common/dma_common_f24.h b/include/libopencm3/stm32/common/dma_common_f24.h index c8aab3ea..011c88d6 100644 --- a/include/libopencm3/stm32/common/dma_common_f24.h +++ b/include/libopencm3/stm32/common/dma_common_f24.h @@ -250,20 +250,20 @@ being at the same relative location */ @{*/ /** Transfer Complete Interrupt Flag */ -#define DMA_ISR_TCIF (1 << 5) +#define DMA_TCIF (1 << 5) /** Half Transfer Interrupt Flag */ -#define DMA_ISR_HTIF (1 << 4) +#define DMA_HTIF (1 << 4) /** Transfer Error Interrupt Flag */ -#define DMA_ISR_TEIF (1 << 3) +#define DMA_TEIF (1 << 3) /** Direct Mode Error Interrupt Flag */ -#define DMA_ISR_DMEIF (1 << 2) +#define DMA_DMEIF (1 << 2) /** FIFO Error Interrupt Flag */ -#define DMA_ISR_FEIF (1 << 0) +#define DMA_FEIF (1 << 0) /**@}*/ /* Offset within interrupt status register to start of stream interrupt flag field */ #define DMA_ISR_OFFSET(stream) (6*(stream & 0x01)+16*((stream & 0x02) >> 1)) -#define DMA_ISR_FLAGS (DMA_ISR_TCIF | DMA_ISR_HTIF | DMA_ISR_TEIF | DMA_ISR_DMEIF | DMA_ISR_FEIF) +#define DMA_ISR_FLAGS (DMA_TCIF | DMA_HTIF | DMA_TEIF | DMA_DMEIF | DMA_FEIF) #define DMA_ISR_MASK(stream) DMA_ISR_FLAGS << DMA_ISR_OFFSET(stream) /* --- DMA_LISR values ----------------------------------------------------- */ diff --git a/lib/stm32/common/dma_common_f24.c b/lib/stm32/common/dma_common_f24.c index aa20e392..6f341a7a 100644 --- a/lib/stm32/common/dma_common_f24.c +++ b/lib/stm32/common/dma_common_f24.c @@ -490,7 +490,7 @@ void dma_set_dma_flow_control(u32 dma, u8 stream) void dma_enable_transfer_error_interrupt(u32 dma, u8 stream) { - dma_clear_interrupt_flags(dma, stream, DMA_ISR_TEIF); + dma_clear_interrupt_flags(dma, stream, DMA_TEIF); DMA_SCR(dma, stream) |= DMA_SxCR_TEIE; } @@ -515,7 +515,7 @@ void dma_disable_transfer_error_interrupt(u32 dma, u8 stream) void dma_enable_half_transfer_interrupt(u32 dma, u8 stream) { - dma_clear_interrupt_flags(dma, stream, DMA_ISR_HTIF); + dma_clear_interrupt_flags(dma, stream, DMA_HTIF); DMA_SCR(dma, stream) |= DMA_SxCR_HTIE; } @@ -540,7 +540,7 @@ void dma_disable_half_transfer_interrupt(u32 dma, u8 stream) void dma_enable_transfer_complete_interrupt(u32 dma, u8 stream) { - dma_clear_interrupt_flags(dma, stream, DMA_ISR_TCIF); + dma_clear_interrupt_flags(dma, stream, DMA_TCIF); DMA_SCR(dma, stream) |= DMA_SxCR_TCIE; } @@ -565,7 +565,7 @@ void dma_disable_transfer_complete_interrupt(u32 dma, u8 stream) void dma_enable_direct_mode_error_interrupt(u32 dma, u8 stream) { - dma_clear_interrupt_flags(dma, stream, DMA_ISR_DMEIF); + dma_clear_interrupt_flags(dma, stream, DMA_DMEIF); DMA_SCR(dma, stream) |= DMA_SxCR_DMEIE; } @@ -590,7 +590,7 @@ void dma_disable_direct_mode_error_interrupt(u32 dma, u8 stream) void dma_enable_fifo_error_interrupt(u32 dma, u8 stream) { - dma_clear_interrupt_flags(dma, stream, DMA_ISR_FEIF); + dma_clear_interrupt_flags(dma, stream, DMA_FEIF); DMA_SFCR(dma, stream) |= DMA_SxFCR_FEIE; }