From cec41eb0c4bd3d2a65f09019f505ca80fbbcb4c4 Mon Sep 17 00:00:00 2001 From: Taylor Vesely Date: Wed, 21 Mar 2012 17:13:45 -0600 Subject: [PATCH] Filled in the APB0 memory map for the lpc17xx. Also set values for the GPIO on AHB. --- .gitignore | 1 + include/libopencm3/lpc17xx/memorymap.h | 63 ++++++++++++-------------- 2 files changed, 31 insertions(+), 33 deletions(-) diff --git a/.gitignore b/.gitignore index 42d67612..f0c86ce4 100644 --- a/.gitignore +++ b/.gitignore @@ -6,5 +6,6 @@ *.srec *.a *.elf +*.swp \#* .\#* diff --git a/include/libopencm3/lpc17xx/memorymap.h b/include/libopencm3/lpc17xx/memorymap.h index 879a97d3..11144422 100644 --- a/include/libopencm3/lpc17xx/memorymap.h +++ b/include/libopencm3/lpc17xx/memorymap.h @@ -25,44 +25,41 @@ /* --- LPC17XX specific peripheral definitions ----------------------------- */ /* Memory map for all busses */ -#define PERIPH_BASE_APB 0x40000000 +#define PERIPH_BASE_APB0 0x40000000 +#define PERIPH_BASE_APB1 0x40080000 #define PERIPH_BASE_AHB 0x20000000 /* Register boundary addresses */ -/* APB */ -#define WDT_BASE (PERIPH_BASE_APB + 0x00000) -#define TIMER0_BASE (PERIPH_BASE_APB + 0x04000) -#define TIMER1_BASE (PERIPH_BASE_APB + 0x08000) -#define TIMER0_16BIT_BASE (PERIPH_BASE_APB + 0x0c000) -#define TIMER1_16BIT_BASE (PERIPH_BASE_APB + 0x10000) -#define TIMER0_32BIT_BASE (PERIPH_BASE_APB + 0x14000) -#define TIMER1_32BIT_BASE (PERIPH_BASE_APB + 0x18000) -#define ADC_BASE (PERIPH_BASE_APB + 0x1c000) -#define USB_BASE (PERIPH_BASE_APB + 0x20000) - -#define I2C_BASE (PERIPH_BASE_APB + 0x00000) -#define WDT_BASE (PERIPH_BASE_APB + 0x04000) -#define UART_BASE (PERIPH_BASE_APB + 0x08000) -#define TIMER0_16BIT_BASE (PERIPH_BASE_APB + 0x0c000) -#define TIMER1_16BIT_BASE (PERIPH_BASE_APB + 0x10000) -#define TIMER0_32BIT_BASE (PERIPH_BASE_APB + 0x14000) -#define TIMER1_32BIT_BASE (PERIPH_BASE_APB + 0x18000) -#define ADC_BASE (PERIPH_BASE_APB + 0x1c000) -#define USB_BASE (PERIPH_BASE_APB + 0x20000) -/* PERIPH_BASE_APB + 0x28000 (0x4002 8000 - 0x4003 7FFF): Reserved */ -#define PMU_BASE (PERIPH_BASE_APB + 0x38000) -#define FLASH_BASE (PERIPH_BASE_APB + 0x3c000) -#define SSP_BASE (PERIPH_BASE_APB + 0x40000) -#define IOCONFIG_BASE (PERIPH_BASE_APB + 0x44000) -#define SYSCTRL_BASE (PERIPH_BASE_APB + 0x48000) -/* PERIPH_BASE_APB + 0x4c000 (0x4004 c000 - 0x4007 FFFF): Reserved */ +/* APB0 */ +#define WDT_BASE (PERIPH_BASE_APB0 + 0x00000) +#define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000) +#define TIMER1_BASE (PERIPH_BASE_APB0 + 0x08000) +#define UART0_BASE (PERIPH_BASE_APB0 + 0x0c000) +#define UART1_BASE (PERIPH_BASE_APB0 + 0x10000) +/* PERIPH_BASE_APB0 + 0X14000 (0x4001 4000 - 0x4001 7FFF): Reserved */ +#define PWM1_BASE (PERIPH_BASE_APB0 + 0x18000) +#define I2C0_BASE (PERIPH_BASE_APB0 + 0x1c000) +#define SPI_BASE (PERIPH_BASE_APB0 + 0x20000) +#define RTC_BASE (PERIPH_BASE_APB0 + 0x24000) +#define GPIOINTERRPUT_BASE (PERIPH_BASE_APB0 + 0x28000) +#define PINCONNECT_BASE (PERIPH_BASE_APB0 + 0x2c000) +#define SSP1_BASE (PERIPH_BASE_APB0 + 0x30000) +#define ADC_BASE (PERIPH_BASE_APB0 + 0x34000) +#define CANAFRAM_BASE (PERIPH_BASE_APB0 + 0x38000) +#define CANAFREG_BASE (PERIPH_BASE_APB0 + 0x3C000) +#define CANCOMMONREG_BASE (PERIPH_BASE_APB0 + 0x40000) +#define CAN1_BASE (PERIPH_BASE_APB0 + 0x44000) +#define CAN2_BASE (PERIPH_BASE_APB0 + 0x48000) +/* PERIPH_BASE_APB0 + 0X4C000 (0x4004 C000 - 0x4005 BFFF): Reserved */ +#define I2C1_BASE (PERIPH_BASE_APB0 + 0x5C000) +/* PERIPH_BASE_APB0 + 0X60000 (0x6000 0000 - 0x4007 BFFF): Reserved */ /* AHB */ -#define GPIO_PIO0_BASE (PERIPH_BASE_AHB + 0x00000) -#define GPIO_PIO1_BASE (PERIPH_BASE_AHB + 0x10000) -#define GPIO_PIO2_BASE (PERIPH_BASE_AHB + 0x20000) -#define GPIO_PIO3_BASE (PERIPH_BASE_AHB + 0x30000) -/* PERIPH_BASE_AHB + 0x40000 (0x5004 0000 - 0x501F FFFF): Reserved */ +#define GPIO_PIO0_BASE (PERIPH_BASE_AHB + 0x9c000) +#define GPIO_PIO1_BASE (PERIPH_BASE_AHB + 0x9c020) +#define GPIO_PIO2_BASE (PERIPH_BASE_AHB + 0x9c040) +#define GPIO_PIO3_BASE (PERIPH_BASE_AHB + 0x9c060) +#define GPIO_PIO4_BASE (PERIPH_BASE_AHB + 0x9c080) #endif