stm32g4/g0: adc: fix clock prescalers

CCR register definitions were completely wrong, both decimal/hex mixups,
and straightup transcriptions from the reference manual errors.

Unify the styles for both g0 and g4, using the same (duplicated)
function for both implmentations.

Reviewed-by: Karl Palsson <karlp@tweak.au>

include/libopencm3/stm32/g0/adc.h

@@ -95,8 +95,8 @@
 /** @defgroup adc_ccr_presc ADC clock prescaler
  *@{*/
 #define ADC_CCR_PRESC_NODIV		(0x0)
-#define ADC_CCR_PRESC_DIV1		(0x1)
-#define ADC_CCR_PRESC_DIV2		(0x2)
+#define ADC_CCR_PRESC_DIV2		(0x1)
+#define ADC_CCR_PRESC_DIV4		(0x2)
 #define ADC_CCR_PRESC_DIV6		(0x3)
 #define ADC_CCR_PRESC_DIV8		(0x4)
 #define ADC_CCR_PRESC_DIV10		(0x5)
@@ -104,8 +104,8 @@
 #define ADC_CCR_PRESC_DIV16		(0x7)
 #define ADC_CCR_PRESC_DIV32		(0x8)
 #define ADC_CCR_PRESC_DIV64		(0x9)
-#define ADC_CCR_PRESC_DIV128	(0x10)
-#define ADC_CCR_PRESC_DIV256	(0x11)
+#define ADC_CCR_PRESC_DIV128	(0xa)
+#define ADC_CCR_PRESC_DIV256	(0xb)
 /**@}*/
 
 /**@}*/

include/libopencm3/stm32/g4/adc.h

@@ -459,25 +459,25 @@
 #define ADC_CSR_ADRDY_MST		(1 << 0)
 
 
-/*-------- ADC_CCR values ------------*/
+/** @addtogroup adc_ccr
+@{*/
 
-/* Bits 21:18 PRESC[21:18]: ADC Prescaler */
 #define ADC_CCR_PRESC_MASK		(0xf)
 #define ADC_CCR_PRESC_SHIFT		(18)
 /** @defgroup adc_ccr_presc ADC clock prescaler
  *@{*/
-#define ADC_CCR_PRESC_NODIV		(0x0 << ADC_CCR_PRESC_SHIFT)
-#define ADC_CCR_PRESC_DIV1		(0x1 << ADC_CCR_PRESC_SHIFT)
-#define ADC_CCR_PRESC_DIV2		(0x2 << ADC_CCR_PRESC_SHIFT)
-#define ADC_CCR_PRESC_DIV6		(0x3 << ADC_CCR_PRESC_SHIFT)
-#define ADC_CCR_PRESC_DIV8		(0x4 << ADC_CCR_PRESC_SHIFT)
-#define ADC_CCR_PRESC_DIV10		(0x5 << ADC_CCR_PRESC_SHIFT)
-#define ADC_CCR_PRESC_DIV12		(0x6 << ADC_CCR_PRESC_SHIFT)
-#define ADC_CCR_PRESC_DIV16		(0x7 << ADC_CCR_PRESC_SHIFT)
-#define ADC_CCR_PRESC_DIV32		(0x8 << ADC_CCR_PRESC_SHIFT)
-#define ADC_CCR_PRESC_DIV64		(0x9 << ADC_CCR_PRESC_SHIFT)
-#define ADC_CCR_PRESC_DIV128		(0x10 << ADC_CCR_PRESC_SHIFT)
-#define ADC_CCR_PRESC_DIV256		(0x11 << ADC_CCR_PRESC_SHIFT)
+#define ADC_CCR_PRESC_NODIV		(0x0)
+#define ADC_CCR_PRESC_DIV2		(0x1)
+#define ADC_CCR_PRESC_DIV4		(0x2)
+#define ADC_CCR_PRESC_DIV6		(0x3)
+#define ADC_CCR_PRESC_DIV8		(0x4)
+#define ADC_CCR_PRESC_DIV10		(0x5)
+#define ADC_CCR_PRESC_DIV12		(0x6)
+#define ADC_CCR_PRESC_DIV16		(0x7)
+#define ADC_CCR_PRESC_DIV32		(0x8)
+#define ADC_CCR_PRESC_DIV64		(0x9)
+#define ADC_CCR_PRESC_DIV128		(0xa)
+#define ADC_CCR_PRESC_DIV256		(0xb)
 /**@}*/
 
 /* CKMODE[1:0]: ADC clock mode */
@@ -500,6 +500,8 @@
 /* DELAY: Delay between 2 sampling phases */
 #define ADC_CCR_DELAY_SHIFT		8
 
+/**@}*/
+
 /* DUAL[4:0]: Dual ADC mode selection */
 /****************************************************************************/
 /** @defgroup adc_multi_mode ADC Multi mode selection
@@ -594,7 +596,7 @@ bool adc_eos_injected(uint32_t adc);
 uint32_t adc_read_injected(uint32_t adc, uint8_t reg);
 void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset);
 void adc_set_clk_source(uint32_t adc, uint32_t source);
-void adc_set_clk_prescale(uint32_t adc, uint32_t prescaler);
+void adc_set_clk_prescale(uint32_t adc, uint32_t prescale);
 void adc_set_multi_mode(uint32_t adc, uint32_t mode);
 void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger,
 					 uint32_t polarity);

lib/stm32/g4/adc.c

@@ -540,13 +540,14 @@ void adc_set_clk_source(uint32_t adc, uint32_t source)
  * The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8.
  *
  * @param adc peripheral of choice @ref adc_reg_base
- * @param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref
- * adc_ccr_adcpre
+ * @param[in] prescale Prescale value for ADC Clock @ref adc_ccr_presc
  */
-void adc_set_clk_prescale(uint32_t adc, uint32_t ckmode)
+void adc_set_clk_prescale(uint32_t adc, uint32_t prescale)
 {
-	uint32_t reg32 = ((ADC_CCR(adc) & ~ADC_CCR_CKMODE_MASK) | ckmode);
-	ADC_CCR(adc) = reg32;
+	uint32_t reg32 = ADC_CCR(adc);
+
+	reg32  &= ~(ADC_CCR_PRESC_MASK << ADC_CCR_PRESC_SHIFT);
+	ADC_CCR(adc) = (reg32 | (prescale << ADC_CCR_PRESC_SHIFT));
 }
 
 /*---------------------------------------------------------------------------*/