stm32: rcc: Rationalize MCO definitions

Some parts used HSICLK, some used HSI.  Most used NOCLK, f3 used
DISABLED.  Try and move all to the shorter, simpler forms, instead of
having mixed defines for different targets for the same thing.  Just
because the bits themselves are different doesn't mean we should make it
more difficult for users to port code.

include/libopencm3/stm32/f1/rcc.h

@@ -113,11 +113,11 @@
 #define RCC_CFGR_MCO_MASK			0xf
 #define RCC_CFGR_MCO_NOCLK			0x0
 #define RCC_CFGR_MCO_SYSCLK			0x4
-#define RCC_CFGR_MCO_HSICLK			0x5
-#define RCC_CFGR_MCO_HSECLK			0x6
-#define RCC_CFGR_MCO_PLLCLK_DIV2		0x7
-#define RCC_CFGR_MCO_PLL2CLK			0x8 /* (**) */
-#define RCC_CFGR_MCO_PLL3CLK_DIV2		0x9 /* (**) */
+#define RCC_CFGR_MCO_HSI			0x5
+#define RCC_CFGR_MCO_HSE			0x6
+#define RCC_CFGR_MCO_PLL_DIV2			0x7
+#define RCC_CFGR_MCO_PLL2			0x8 /* (**) */
+#define RCC_CFGR_MCO_PLL3_DIV2			0x9 /* (**) */
 #define RCC_CFGR_MCO_XT1			0xa /* (**) */
 #define RCC_CFGR_MCO_PLL3			0xb /* (**) */
 /**@}*/

include/libopencm3/stm32/f3/rcc.h

@@ -90,7 +90,7 @@
 /* MCO: Microcontroller clock output */
 #define RCC_CFGR_MCO_SHIFT			24
 #define RCC_CFGR_MCO_MASK			0x7
-#define RCC_CFGR_MCO_DISABLED			0x0
+#define RCC_CFGR_MCO_NOCLK			0x0
 /*Reserve RCC_CFGR_MCO				0x1*/
 #define RCC_CFGR_MCO_LSI			0x2
 #define RCC_CFGR_MCO_LSE			0x3

include/libopencm3/stm32/l0/rcc.h

@@ -129,13 +129,13 @@
 /* MCO: Microcontroller clock output */
 #define RCC_CFGR_MCO_NOCLK			0x0
 #define RCC_CFGR_MCO_SYSCLK			0x1
-#define RCC_CFGR_MCO_HSI16CLK			0x2
-#define RCC_CFGR_MCO_MSICLK			0x3
-#define RCC_CFGR_MCO_HSECLK			0x4
-#define RCC_CFGR_MCO_PLLCLK			0x5
-#define RCC_CFGR_MCO_LSICLK			0x6
-#define RCC_CFGR_MCO_LSECLK			0x7
-#define RCC_CFGR_MCO_HSI48CLK			0x8
+#define RCC_CFGR_MCO_HSI16			0x2
+#define RCC_CFGR_MCO_MSI			0x3
+#define RCC_CFGR_MCO_HSE			0x4
+#define RCC_CFGR_MCO_PLL			0x5
+#define RCC_CFGR_MCO_LSI			0x6
+#define RCC_CFGR_MCO_LSE			0x7
+#define RCC_CFGR_MCO_HSI48			0x8
 #define RCC_CFGR_MCO_SHIFT			24
 #define RCC_CFGR_MCO_MASK			0xf
 

include/libopencm3/stm32/l1/rcc.h

@@ -131,12 +131,12 @@
 /* MCO: Microcontroller clock output */
 #define RCC_CFGR_MCO_NOCLK			0x0
 #define RCC_CFGR_MCO_SYSCLK			0x1
-#define RCC_CFGR_MCO_HSICLK			0x2
-#define RCC_CFGR_MCO_MSICLK			0x3
-#define RCC_CFGR_MCO_HSECLK			0x4
-#define RCC_CFGR_MCO_PLLCLK			0x5
-#define RCC_CFGR_MCO_LSICLK			0x6
-#define RCC_CFGR_MCO_LSECLK			0x7
+#define RCC_CFGR_MCO_HSI			0x2
+#define RCC_CFGR_MCO_MSI			0x3
+#define RCC_CFGR_MCO_HSE			0x4
+#define RCC_CFGR_MCO_PLL			0x5
+#define RCC_CFGR_MCO_LSI			0x6
+#define RCC_CFGR_MCO_LSE			0x7
 #define RCC_CFGR_MCO_SHIFT			24
 #define RCC_CFGR_MCO_MASK			0x7
 

include/libopencm3/stm32/l4/rcc.h

@@ -160,12 +160,12 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz,
 /* MCO: Microcontroller clock output */
 #define RCC_CFGR_MCO_NOCLK			0x0
 #define RCC_CFGR_MCO_SYSCLK			0x1
-#define RCC_CFGR_MCO_MSICLK			0x2
-#define RCC_CFGR_MCO_HSI16CLK			0x3
-#define RCC_CFGR_MCO_HSECLK			0x4
-#define RCC_CFGR_MCO_PLLCLK			0x5
-#define RCC_CFGR_MCO_LSICLK			0x6
-#define RCC_CFGR_MCO_LSECLK			0x7
+#define RCC_CFGR_MCO_MSI			0x2
+#define RCC_CFGR_MCO_HSI16			0x3
+#define RCC_CFGR_MCO_HSE			0x4
+#define RCC_CFGR_MCO_PLL			0x5
+#define RCC_CFGR_MCO_LSI			0x6
+#define RCC_CFGR_MCO_LSE			0x7
 #define RCC_CFGR_MCO_SHIFT			24
 #define RCC_CFGR_MCO_MASK			0xf