Alexandru Gagniuc
12 years ago
2 changed files with 370 additions and 0 deletions
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/*
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* This file is part of the libopencm3 project. |
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* |
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* Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com> |
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* |
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* This library is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU Lesser General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* This library is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public License |
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#ifndef LIBOPENCM3_LM4F_USB_H |
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#define LIBOPENCM3_LM4F_USB_H |
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#include <libopencm3/lm4f/memorymap.h> |
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#include <libopencm3/cm3/common.h> |
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/* =============================================================================
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* USB registers |
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* ---------------------------------------------------------------------------*/ |
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/* USB Device Functional Address */ |
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#define USB_FADDR MMIO8 (USB_BASE + 0x00) |
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/* USB Power */ |
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#define USB_POWER MMIO8 (USB_BASE + 0x01) |
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/* USB Transmit Interrupt Status */ |
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#define USB_TXIS MMIO16(USB_BASE + 0x02) |
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/* USB Receive Interrupt Status */ |
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#define USB_RXIS MMIO16(USB_BASE + 0x04) |
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/* USB Transmit Interrupt Enable */ |
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#define USB_TXIE MMIO16(USB_BASE + 0x06) |
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/* USB Receive Interrupt Enable */ |
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#define USB_RXIE MMIO16(USB_BASE + 0x08) |
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/* USB General Interrupt Status */ |
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#define USB_IS MMIO8 (USB_BASE + 0x0A) |
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/* USB Interrupt Enable */ |
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#define USB_IE MMIO8 (USB_BASE + 0x0B) |
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/* USB Frame Value */ |
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#define USB_FRAME MMIO16(USB_BASE + 0x0C) |
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/* USB Endpoint Index */ |
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#define USB_EPIDX MMIO8 (USB_BASE + 0x0E) |
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/* USB Test Mode */ |
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#define USB_TEST MMIO8 (USB_BASE + 0x0F) |
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/* USB FIFO Endpoint [0-7] */ |
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#define USB_FIFO8(n) MMIO8(USB_BASE + 0x20 + n*0x04) |
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#define USB_FIFO16(n) MMIO16(USB_BASE + 0x20 + n*0x04) |
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#define USB_FIFO32(n) MMIO32(USB_BASE + 0x20 + n*0x04) |
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/* USB Transmit Dynamic FIFO Sizing */ |
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#define USB_TXFIFOSZ MMIO8 (USB_BASE + 0x62) |
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/* USB Receive Dynamic FIFO Sizing */ |
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#define USB_RXFIFOSZ MMIO8 (USB_BASE + 0x63) |
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/* USB Transmit FIFO Start Address */ |
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#define USB_TXFIFOADD MMIO16(USB_BASE + 0x64) |
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/* USB Receive FIFO Start Address */ |
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#define USB_RXFIFOADD MMIO16(USB_BASE + 0x66) |
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/* USB Connect Timing */ |
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#define USB_CONTIM MMIO8 (USB_BASE + 0x7A) |
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/* USB Full-Speed Last Transaction to End of Frame Timing */ |
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#define USB_FSEOF MMIO8 (USB_BASE + 0x7D) |
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/* USB Low-Speed Last Transaction to End of Frame Timing */ |
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#define USB_LSEOF MMIO8 (USB_BASE + 0x7E) |
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/* USB Control and Status Endpoint 0 Low */ |
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#define USB_CSRL0 MMIO8 (USB_BASE + 0x102) |
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/* USB Control and Status Endpoint 0 High */ |
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#define USB_CSRH0 MMIO8 (USB_BASE + 0x103) |
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/* USB Receive Byte Count Endpoint 0 */ |
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#define USB_COUNT0 MMIO8 (USB_BASE + 0x108) |
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/* USB Maximum Transmit Data Endpoint [1-7] */ |
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#define USB_TXMAXP(n) MMIO16(USB_BASE + 0x100 + n*0x10) |
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/* USB Transmit Control and Status Endpoint [1-7] Low */ |
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#define USB_TXCSRL(n) MMIO8 (USB_BASE + 0x102 + n*0x10) |
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/* USB Transmit Control and Status Endpoint [1-7] High */ |
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#define USB_TXCSRH(n) MMIO8 (USB_BASE + 0x103 + n*0x10) |
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/* USB Maximum Receive Data Endpoint [1-7] */ |
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#define USB_RXMAXP(n) MMIO16(USB_BASE + 0x104 + n*0x10) |
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/* USB Receive Control and Status Endpoint [1-7] Low */ |
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#define USB_RXCSRL(n) MMIO8 (USB_BASE + 0x106 + n*0x10) |
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/* USB Receive Control and Status Endpoint [1-7] High */ |
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#define USB_RXCSRH(n) MMIO8 (USB_BASE + 0x107 + n*0x10) |
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/* USB Receive Byte Count Endpoint [1-7] */ |
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#define USB_RXCOUNT(n) MMIO16(USB_BASE + 0x108 + n*0x10) |
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/* USB Receive Double Packet Buffer Disable */ |
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#define USB_RXDPKTBUFDIS MMIO16(USB_BASE + 0x340) |
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/* USB Transmit Double Packet Buffer Disable */ |
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#define USB_TXDPKTBUFDIS MMIO16(USB_BASE + 0x342) |
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/* USB Device RESUME Raw Interrupt Status */ |
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#define USB_DRRIS MMIO32(USB_BASE + 0x410) |
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/* USB Device RESUME Interrupt Mask */ |
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#define USB_DRIM MMIO32(USB_BASE + 0x414) |
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/* USB Device RESUME Interrupt Status and Clear */ |
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#define USB_DRISC MMIO32(USB_BASE + 0x418) |
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/* USB DMA Select */ |
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#define USB_DMASEL MMIO32(USB_BASE + 0x450) |
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/* USB Peripheral Properties */ |
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#define USB_PP MMIO32(USB_BASE + 0xFC0) |
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/* =============================================================================
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* USB_FADDR values |
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* ---------------------------------------------------------------------------*/ |
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/** Function Address */ |
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#define USB_FADDR_FUNCADDR_MASK (0x3f << 0) |
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/* =============================================================================
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* USB_POWER values |
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* ---------------------------------------------------------------------------*/ |
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/** Isochronous Update */ |
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#define USB_POWER_ISOUP (1 << 7) |
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/** Soft Connect/Disconnect */ |
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#define USB_POWER_SOFTCONN (1 << 6) |
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/** RESET signaling */ |
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#define USB_POWER_RESET (1 << 3) |
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/** RESUME signaling */ |
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#define USB_POWER_RESUME (1 << 2) |
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/** SUSPEND mode */ |
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#define USB_POWER_SUSPEND (1 << 1) |
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/** Power down PHY */ |
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#define USB_POWER_PWRDNPHY (1 << 0) |
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/* =============================================================================
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* Endpoint bitmasks for interrupt status and control registers |
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* Applies to USB_TXIS, USB_RXIS, USB_TXIE, USB_RXIE, USB_RXDPKTBUFDIS, |
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* USB_TXDPKTBUFDIS |
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* ---------------------------------------------------------------------------*/ |
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#define USB_EP7 (1 << 7) |
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#define USB_EP6 (1 << 6) |
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#define USB_EP5 (1 << 5) |
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#define USB_EP4 (1 << 4) |
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#define USB_EP3 (1 << 3) |
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#define USB_EP2 (1 << 2) |
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#define USB_EP1 (1 << 1) |
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#define USB_EP0 (1 << 0) |
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/* =============================================================================
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* USB interrupt mask values |
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* |
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* These are interchangeable across USB_IS, and USB_IE registers. |
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* ---------------------------------------------------------------------------*/ |
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/** USB disconnect interrupt */ |
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#define USB_IM_DISCON (1 << 5) |
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/** Start of frame */ |
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#define USB_IM_SOF (1 << 3) |
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/** RESET signaling detected */ |
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#define USB_IM_RESET (1 << 2) |
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/** RESUME signaling detected */ |
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#define USB_IM_RESUME (1 << 1) |
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/** SUSPEND signaling detected */ |
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#define USB_IM_SUSPEND (1 << 0) |
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/* =============================================================================
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* USB_FRAME values |
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* ---------------------------------------------------------------------------*/ |
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/** Frame number */ |
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#define USB_FRAME_MASK (0x03FF) |
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/* =============================================================================
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* USB_IDX values |
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* ---------------------------------------------------------------------------*/ |
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/** Endpoint Index */ |
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#define USB_EPIDX_MASK (0x0F) |
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/* =============================================================================
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* USB_TEST values |
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* ---------------------------------------------------------------------------*/ |
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/** FIFO access */ |
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#define USB_TEST_FIFOACC (1 << 6) |
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/** Force full-speed mode */ |
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#define USB_TEST_FORCEFS (1 << 5) |
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/* =============================================================================
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* USB_TXFIFOSZ and USB_RXFIFOSZ values |
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* ---------------------------------------------------------------------------*/ |
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/** Double packet buffer support */ |
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#define USB_FIFOSZ_DPB (1 << 4) |
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/* USB Transmit Dynamic FIFO Sizing */ |
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#define USB_FIFOSZ_SIZE_MASK (0x0F << 0) |
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#define USB_FIFOSZ_SIZE_8 (0x00 << 0) |
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#define USB_FIFOSZ_SIZE_16 (0x01 << 0) |
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#define USB_FIFOSZ_SIZE_32 (0x02 << 0) |
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#define USB_FIFOSZ_SIZE_64 (0x03 << 0) |
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#define USB_FIFOSZ_SIZE_128 (0x04 << 0) |
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#define USB_FIFOSZ_SIZE_256 (0x05 << 0) |
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#define USB_FIFOSZ_SIZE_512 (0x06 << 0) |
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#define USB_FIFOSZ_SIZE_1024 (0x07 << 0) |
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#define USB_FIFOSZ_SIZE_2048 (0x08 << 0) |
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/* =============================================================================
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* USB_CONTIM values |
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* ---------------------------------------------------------------------------*/ |
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/** Connect wait */ |
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#define USB_CONTIM_WTCON_MASK (0x0F << 4) |
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/** Wait ID */ |
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#define USB_CONTIM_WTID_MASK (0x0F << 0) |
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/* =============================================================================
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* USB_CSRL0 values |
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* ---------------------------------------------------------------------------*/ |
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/** Setup End Clear */ |
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#define USB_CSRL0_SETENDC (1 << 7) |
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/** RXRDY Clear */ |
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#define USB_CSRL0_RXRDYC (1 << 6) |
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/** Send Stall */ |
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#define USB_CSRL0_STALL (1 << 5) |
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/** Setup End */ |
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#define USB_CSRL0_SETEND (1 << 4) |
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/** Data End */ |
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#define USB_CSRL0_DATAEND (1 << 3) |
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/** Endpoint Stalled */ |
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#define USB_CSRL0_STALLED (1 << 2) |
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/** Transmit Packet Ready */ |
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#define USB_CSRL0_TXRDY (1 << 1) |
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/** Receive Packet Ready */ |
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#define USB_CSRL0_RXRDY (1 << 0) |
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/* =============================================================================
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* USB_CSRH0 values |
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* ---------------------------------------------------------------------------*/ |
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/** Flush FIFO */ |
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#define USB_CSRH0_FLUSH (1 << 0) |
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/* =============================================================================
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* USB_TXCSRLx values |
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* ---------------------------------------------------------------------------*/ |
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/** Clear data toggle */ |
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#define USB_TXCSRL_CLRDT (1 << 6) |
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/** Endpoint Stalled */ |
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#define USB_TXCSRL_STALLED (1 << 5) |
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/** Send Stall */ |
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#define USB_TXCSRL_STALL (1 << 4) |
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/** Flush FIFO */ |
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#define USB_TXCSRL_FLUSH (1 << 3) |
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/** Underrun */ |
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#define USB_TXCSRL_UNDRN (1 << 2) |
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/** FIFO not empty */ |
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#define USB_TXCSRL_FIFONE (1 << 1) |
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/** Transmit Packet Ready */ |
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#define USB_TXCSRL_TXRDY (1 << 0) |
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/* =============================================================================
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* USB_TXCSRHx values |
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* ---------------------------------------------------------------------------*/ |
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/** Auto set */ |
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#define USB_TXCSRH_AUTOSET (1 << 7) |
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/** Isochronous transfers */ |
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#define USB_TXCSRH_ISO (1 << 6) |
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/** Mode */ |
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#define USB_TXCSRH_MODE (1 << 5) |
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/** DMA request enable */ |
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#define USB_TXCSRH_DMAEN (1 << 4) |
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/** Force data toggle */ |
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#define USB_TXCSRH_FDT (1 << 3) |
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/** DMA request mode */ |
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#define USB_TXCSRH_DMAMOD (1 << 2) |
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/* =============================================================================
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* USB_RXCSRLx values |
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* ---------------------------------------------------------------------------*/ |
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/** Clear data toggle */ |
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#define USB_RXCSRL_CLRDT (1 << 7) |
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/** Endpoint Stalled */ |
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#define USB_RXCSRL_STALLED (1 << 6) |
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/** Send Stall */ |
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#define USB_RXCSRL_STALL (1 << 5) |
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/** Flush FIFO */ |
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#define USB_RXCSRL_FLUSH (1 << 4) |
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/** Data error */ |
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#define USB_RXCSRL_DATAERR (1 << 2) |
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/** Overrun */ |
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#define USB_RXCSRL_OVER (1 << 2) |
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/** FIFO full */ |
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#define USB_RXCSRL_FULL (1 << 1) |
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/** Receive Packet Ready */ |
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#define USB_RXCSRL_RXRDY (1 << 0) |
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/* =============================================================================
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* USB_RXCSRHx values |
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* ---------------------------------------------------------------------------*/ |
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/** Auto clear */ |
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#define USB_RXCSRH_AUTOCL (1 << 7) |
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/** Isochronous transfers */ |
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#define USB_RXCSRH_ISO (1 << 6) |
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/** DMA request enable */ |
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#define USB_RXCSRH_DMAEN (1 << 5) |
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/** Disable NYET / PID error */ |
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#define USB_RXCSRH_PIDERR (1 << 4) |
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/** DMA request mode */ |
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#define USB_RXCSRH_DMAMOD (1 << 3) |
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/* =============================================================================
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* USB_DRRIS values |
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* ---------------------------------------------------------------------------*/ |
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/** RESUME interrupt status */ |
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#define USB_DRRIS_RESUME (1 << 0) |
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/* =============================================================================
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* USB_DRIM values |
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* ---------------------------------------------------------------------------*/ |
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/** RESUME interrupt mask */ |
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#define USB_DRIM_RESUME (1 << 0) |
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/* =============================================================================
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* USB_DRISC values |
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* ---------------------------------------------------------------------------*/ |
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/** RESUME interrupt status and clear */ |
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#define USB_DRISC_RESUME (1 << 0) |
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/* =============================================================================
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* USB_PP values |
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* ---------------------------------------------------------------------------*/ |
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/** Endpoint count */ |
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#define USB_PP_ECNT_MASK (0xFF << 8) |
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/** USB capability */ |
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#define USB_PP_USB_MASK (0x03 << 6) |
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#define USB_PP_USB_NA (0x00 << 6) |
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#define USB_PP_USB_DEVICE (0x01 << 6) |
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#define USB_PP_USB_HOST (0x02 << 6) |
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#define USB_PP_USB_OTG (0x03 << 6) |
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/** PHY present */ |
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#define USB_PP_PHY (1 << 4) |
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/** Controller type */ |
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#define USB_PP_TYPE_MASK (0x0F << 0) |
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#endif /* LIBOPENCM3_LM4F_USB_H */ |
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