Piotr Esden-Tempski
12 years ago
13 changed files with 352 additions and 215 deletions
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/** @addtogroup spi_defines
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@author @htmlonly © @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com> |
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*/ |
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/*
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* This file is part of the libopencm3 project. |
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* |
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* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com> |
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* |
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* This library is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU Lesser General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* This library is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public License |
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H
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The order of header inclusion is important. spi.h includes the device |
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specific memorymap.h header before including this header file.*/ |
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/** @cond */ |
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#ifdef LIBOPENCM3_SPI_H |
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/** @endcond */ |
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#ifndef LIBOPENCM3_SPI_COMMON_F0124_H |
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#define LIBOPENCM3_SPI_COMMON_F0124_H |
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/**@{*/ |
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#include <libopencm3/stm32/common/spi_common_all.h> |
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/*
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* This file extends the common STM32 version with definitions only |
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* applicable to the STM32F0/1/2/4 series of devices. |
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*/ |
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/* DFF: Data frame format */ |
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/****************************************************************************/ |
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/** @defgroup spi_dff SPI data frame format
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@ingroup spi_defines |
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@{*/ |
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#define SPI_CR1_DFF_8BIT (0 << 11) |
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#define SPI_CR1_DFF_16BIT (1 << 11) |
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/**@}*/ |
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#define SPI_CR1_DFF (1 << 11) |
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#endif |
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/** @cond */ |
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#else |
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#warning "spi_common_f24.h should not be included explicitly, only via spi.h" |
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#endif |
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/** @endcond */ |
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/**@}*/ |
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/** @addtogroup spi_file
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@author @htmlonly © @endhtmlonly 2009 |
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Uwe Hermann <uwe@hermann-uwe.de> |
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@author @htmlonly © @endhtmlonly 2012 |
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Ken Sarkies <ksarkies@internode.on.net> |
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Devices can have up to three SPI peripherals. The common 4-wire full-duplex |
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mode of operation is supported, along with 3-wire variants using unidirectional |
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communication modes or half-duplex bidirectional communication. A variety of |
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options allows many of the SPI variants to be supported. Multimaster operation |
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is also supported. A CRC can be generated and checked in hardware. |
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@note Some JTAG pins need to be remapped if SPI is to be used. |
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@note The I2S protocol shares the SPI hardware so the two protocols cannot be |
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used at the same time on the same peripheral. |
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Example: 1Mbps, positive clock polarity, leading edge trigger, 8-bit words, |
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LSB first. |
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@code |
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spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, |
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SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, |
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SPI_CR1_LSBFIRST); |
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spi_write(SPI1, 0x55); // 8-bit write
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spi_write(SPI1, 0xaa88); // 16-bit write
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reg8 = spi_read(SPI1); // 8-bit read
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reg16 = spi_read(SPI1); // 16-bit read
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@endcode |
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@todo need additional functions to aid ISRs in retrieving status |
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*/ |
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/*
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* This file is part of the libopencm3 project. |
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* |
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> |
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* |
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* This library is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU Lesser General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* This library is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public License |
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#include <libopencm3/stm32/spi.h> |
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#include <libopencm3/stm32/rcc.h> |
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/*
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* SPI and I2S code. |
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* |
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* Examples: |
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* spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, |
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* SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, |
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* SPI_CR1_LSBFIRST); |
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* spi_write(SPI1, 0x55); // 8-bit write
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* spi_write(SPI1, 0xaa88); // 16-bit write
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* reg8 = spi_read(SPI1); // 8-bit read
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* reg16 = spi_read(SPI1); // 16-bit read
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*/ |
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/**@{*/ |
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/*---------------------------------------------------------------------------*/ |
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/** @brief Configure the SPI as Master.
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The SPI peripheral is configured as a master with communication parameters |
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baudrate, data format 8/16 bits, frame format lsb/msb first, clock polarity |
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and phase. The SPI enable, CRC enable and CRC next controls are not affected. |
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These must be controlled separately. |
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@todo NSS pin handling. |
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. |
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@param[in] br Unsigned int32. Baudrate @ref spi_baudrate. |
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@param[in] cpol Unsigned int32. Clock polarity @ref spi_cpol. |
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@param[in] cpha Unsigned int32. Clock Phase @ref spi_cpha. |
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@param[in] dff Unsigned int32. Data frame format 8/16 bits @ref spi_dff. |
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@param[in] lsbfirst Unsigned int32. Frame format lsb/msb first @ref |
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spi_lsbfirst. |
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@returns int. Error code. |
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*/ |
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int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha, |
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uint32_t dff, uint32_t lsbfirst) |
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{ |
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uint32_t reg32 = SPI_CR1(spi); |
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/* Reset all bits omitting SPE, CRCEN and CRCNEXT bits. */ |
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reg32 &= SPI_CR1_SPE | SPI_CR1_CRCEN | SPI_CR1_CRCNEXT; |
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reg32 |= SPI_CR1_MSTR; /* Configure SPI as master. */ |
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reg32 |= br; /* Set baud rate bits. */ |
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reg32 |= cpol; /* Set CPOL value. */ |
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reg32 |= cpha; /* Set CPHA value. */ |
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reg32 |= dff; /* Set data format (8 or 16 bits). */ |
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reg32 |= lsbfirst; /* Set frame format (LSB- or MSB-first). */ |
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/* TODO: NSS pin handling. */ |
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SPI_CR1(spi) = reg32; |
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return 0; /* TODO */ |
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} |
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/*---------------------------------------------------------------------------*/ |
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/** @brief SPI Set Data Frame Format to 8 bits
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. |
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*/ |
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void spi_set_dff_8bit(uint32_t spi) |
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{ |
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SPI_CR1(spi) &= ~SPI_CR1_DFF; |
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} |
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/*---------------------------------------------------------------------------*/ |
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/** @brief SPI Set Data Frame Format to 16 bits
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. |
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*/ |
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void spi_set_dff_16bit(uint32_t spi) |
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{ |
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SPI_CR1(spi) |= SPI_CR1_DFF; |
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} |
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/**@}*/ |
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@ -0,0 +1,60 @@ |
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/*
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* This file is part of the libopencm3 project. |
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* |
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> |
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* |
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* This library is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU Lesser General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* This library is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public License |
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#include <libopencm3/stm32/spi.h> |
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#include <libopencm3/stm32/rcc.h> |
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void spi_send8(uint32_t spi, uint8_t data) |
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{ |
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/* Wait for transfer finished. */ |
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while (!(SPI_SR(spi) & SPI_SR_TXE)); |
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/* Write data (8 or 16 bits, depending on DFF) into DR. */ |
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SPI_DR8(spi) = data; |
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} |
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uint8_t spi_read8(uint32_t spi) |
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{ |
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/* Wait for transfer finished. */ |
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while (!(SPI_SR(spi) & SPI_SR_RXNE)); |
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/* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ |
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return SPI_DR8(spi); |
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} |
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void spi_set_data_size(uint32_t spi, uint16_t data_s) |
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{ |
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SPI_CR2(spi) = (SPI_CR2(spi) & ~SPI_CR2_DS_MASK) | |
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(data_s & SPI_CR2_DS_MASK); |
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} |
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void spi_fifo_reception_threshold_8bit(uint32_t spi) |
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{ |
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SPI_CR2(spi) |= SPI_CR2_FRXTH; |
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} |
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void spi_fifo_reception_threshold_16bit(uint32_t spi) |
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{ |
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SPI_CR2(spi) &= ~SPI_CR2_FRXTH; |
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} |
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void spi_i2s_mode_spi_mode(uint32_t spi) |
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{ |
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SPI_I2SCFGR(spi) &= ~SPI_I2SCFGR_I2SMOD; |
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} |
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