diff --git a/include/libopencm3/stm32/f4/rcc.h b/include/libopencm3/stm32/f4/rcc.h
index 151c73f7..2d9f7541 100644
--- a/include/libopencm3/stm32/f4/rcc.h
+++ b/include/libopencm3/stm32/f4/rcc.h
@@ -1080,6 +1080,7 @@ void rcc_osc_on(enum rcc_osc osc);
 void rcc_osc_off(enum rcc_osc osc);
 void rcc_css_enable(void);
 void rcc_css_disable(void);
+void rcc_plli2s_config(uint16_t n, uint8_t r);
 void rcc_pllsai_config(uint16_t n, uint16_t p, uint16_t q, uint16_t r);
 void rcc_pllsai_postscalers(uint8_t q, uint8_t r);
 void rcc_set_sysclk_source(uint32_t clk);
diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c
index 66c3d4a1..3d0e00fa 100644
--- a/lib/stm32/f4/rcc.c
+++ b/lib/stm32/f4/rcc.c
@@ -542,6 +542,18 @@ void rcc_css_disable(void)
 	RCC_CR &= ~RCC_CR_CSSON;
 }
 
+/**
+ * Set the dividers for the PLLI2S clock outputs
+ * @param n valid range depends on target device, check your RefManual.
+ * @param r valid range is 2..7
+ */
+void rcc_plli2s_config(uint16_t n, uint8_t r)
+{
+	RCC_PLLI2SCFGR = (
+	  ((n & RCC_PLLI2SCFGR_PLLI2SN_MASK) << RCC_PLLI2SCFGR_PLLI2SN_SHIFT) |
+	  ((r & RCC_PLLI2SCFGR_PLLI2SR_MASK) << RCC_PLLI2SCFGR_PLLI2SR_SHIFT));
+}
+
 /**
  * Set the dividers for the PLLSAI clock outputs
  * divider p is only available on F4x9 parts, pass 0 for other parts.