From f4eca5400e917b1a102d1229c59b96ff0441493d Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Tue, 7 May 2013 01:59:10 -0500 Subject: [PATCH] lm4f: Properly set PLL divisor rcc_set_pll_divisor() would take the number we wanted to divide the 400MHz clock and put it directly in the RCC2 register. This caused the clock to always be one speed tier slower than expected. The value of the divisor must be decremented by 1, so a divisor of 5 will be written as 4 in the RCC2. Signed-off-by: Alexandru Gagniuc --- lib/lm4f/rcc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/lm4f/rcc.c b/lib/lm4f/rcc.c index 29f281ce..426aa80b 100644 --- a/lib/lm4f/rcc.c +++ b/lib/lm4f/rcc.c @@ -277,7 +277,7 @@ void rcc_set_pll_divisor(u8 div400) reg32 = SYSCTL_RCC2; reg32 &= ~SYSCTL_RCC2_SYSDIV400_MASK; - reg32 |= (div400 << 22) & SYSCTL_RCC2_SYSDIV400_MASK; + reg32 |= ((div400 - 1) << 22) & SYSCTL_RCC2_SYSDIV400_MASK; /* We are expecting a divider from 400MHz */ reg32 |= SYSCTL_RCC2_DIV400; SYSCTL_RCC2 = reg32;