Changes to doxygen markup to solve a few problems that upset

doxygen, and to correct minor errors.

HACKING_COMMON_DOC

@@ -35,6 +35,20 @@ NOTE: The common source files MUST have the "dispatch" header so that
 compilation will use the specific defines for the subfamily being compiled.
 These can differ between subfamilies.
 
+NOTE: The common source files must have a line of the form
+
+#ifdef LIBOPENCM3_xxx_H
+
+where xxx is the associated peripheral name. This prevents the common files
+from being included accidentally into a user's application. This however
+causes doxygen to skip processing of the remainder of the file. Thus a
+
+@cond ... @endcond
+
+directive must be placed around the statement to prevent doxygen from
+processing it. This works only for doxygen 1.8.4 or later. At the present
+time most distros have an earlier buggy version.
+
 Documentation
 -------------
 

doc/HACKING

@@ -33,7 +33,7 @@ functions and defines in the documentation.
 The header and source files for each peripheral in each family must have a
 heading section in which an @defgroup defines the group name for the particular
 peripheral. This group name will be the same across all families as each one
-is documented deparately. Thus for a peripheral xxx the header will have a
+is documented separately. Thus for a peripheral xxx the header will have a
 group name xxx_defines and the source file will have xxx_file. This will allow
 the group to appear separately. An @ingroup must be provided to place the group
 as a subgroup of the appropriate family grouping. Note that @file is not used.
@@ -78,6 +78,7 @@ LAYOUT_FILE = DoxygenLayout_$processor.xml
 WARN_LOGFILE = doxygen_$processor.log
 TAGFILES = ../cm3/cm3.tag=../../cm3/html
 GENERATE_TAGFILE = $processor.tag
+PREDEFINED = list of macro definitions
 
 For the top level Doxyfile
 

doc/stm32f1/Doxyfile

@@ -33,6 +33,6 @@ TAGFILES               = ../cm3/cm3.tag=../../cm3/html
 
 GENERATE_TAGFILE       = stm32f1.tag
 
-ENABLE_PREPROCESSING    = NO
+ENABLE_PREPROCESSING   = YES
 
 

doc/stm32f2/Doxyfile

@@ -32,6 +32,6 @@ TAGFILES               = ../cm3/cm3.tag=../../cm3/html
 
 GENERATE_TAGFILE       = stm32f2.tag
 
-ENABLE_PREPROCESSING    = NO
+ENABLE_PREPROCESSING    = YES
 
 

doc/stm32f4/Doxyfile

@@ -32,6 +32,6 @@ TAGFILES               = ../cm3/cm3.tag=../../cm3/html
 
 GENERATE_TAGFILE       = stm32f4.tag
 
-ENABLE_PREPROCESSING    = NO
+ENABLE_PREPROCESSING    = YES
 
 

doc/stm32l1/Doxyfile

@@ -36,6 +36,6 @@ TAGFILES               = ../cm3/cm3.tag=../../cm3/html
 
 GENERATE_TAGFILE       = stm32l1.tag
 
-ENABLE_PREPROCESSING    = NO
+ENABLE_PREPROCESSING    = YES
 
 

include/libopencm3/stm32/common/crc_common_all.h

@@ -27,7 +27,9 @@
 The order of header inclusion is important. crc.h includes the device
 specific memorymap.h header before including this header file.*/
 
+/** @cond */
 #ifdef LIBOPENCM3_CRC_H
+/** @endcond */
 #ifndef LIBOPENCM3_CRC_COMMON_ALL_H
 #define LIBOPENCM3_CRC_COMMON_ALL_H
 
@@ -94,7 +96,9 @@ END_DECLS
 /**@}*/
 
 #endif
+/** @cond */
 #else
 #warning "crc_common_all.h should not be included explicitly, only via crc.h"
 #endif
+/** @endcond */
 

include/libopencm3/stm32/common/dac_common_all.h

@@ -29,7 +29,9 @@
 The order of header inclusion is important. dac.h includes the device
 specific memorymap.h header before including this header file.*/
 
+/** @cond */
 #ifdef LIBOPENCM3_DAC_H
+/** @endcond */
 #ifndef LIBOPENCM3_DAC_COMMON_ALL_H
 #define LIBOPENCM3_DAC_COMMON_ALL_H
 
@@ -93,7 +95,7 @@ specific memorymap.h header before including this header file.*/
  */
 #define DAC_CR_MAMP2_SHIFT		24
 /** @defgroup dac_mamp2 DAC Channel 2 LFSR Mask and Triangle Wave Amplitude values
-@ingroup STM32F_dac_defines
+@ingroup dac_defines
 
 Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1
 @{*/
@@ -122,7 +124,7 @@ Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1
 #define DAC_CR_WAVE2_SHIFT		22
 #define DAC_CR_WAVE2_DIS		(0x3 << DAC_CR_WAVE2_SHIFT)
 /** @defgroup dac_wave2_en DAC Channel 2 Waveform Generation Enable
-@ingroup STM32F_dac_defines
+@ingroup dac_defines
 
 @li NOISE: Noise wave generation enabled
 @li TRI: Triangle wave generation enabled
@@ -153,7 +155,7 @@ Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1
  */
 #define DAC_CR_TSEL2_SHIFT		19
 /** @defgroup dac_trig2_sel DAC Channel 2 Trigger Source Selection
-@ingroup STM32F_dac_defines
+@ingroup dac_defines
 
 @li T6: Timer 6 TRGO event
 @li T3: Timer 3 TRGO event
@@ -205,7 +207,7 @@ Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1
  */
 #define DAC_CR_MAMP1_SHIFT		8
 /** @defgroup dac_mamp1 DAC Channel 1 LFSR Mask and Triangle Wave Amplitude values
-@ingroup STM32F_dac_defines
+@ingroup dac_defines
 
 Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1
 @{*/
@@ -234,7 +236,7 @@ Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1
 #define DAC_CR_WAVE1_SHIFT		6
 #define DAC_CR_WAVE1_DIS		(0x3 << DAC_CR_WAVE1_SHIFT)
 /** @defgroup dac_wave1_en DAC Channel 1 Waveform Generation Enable
-@ingroup STM32F_dac_defines
+@ingroup dac_defines
 
 @li DIS: wave generation disabled
 @li NOISE: Noise wave generation enabled
@@ -266,7 +268,7 @@ Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1
  */
 #define DAC_CR_TSEL1_SHIFT		3
 /** @defgroup dac_trig1_sel DAC Channel 1 Trigger Source Selection
-@ingroup STM32F_dac_defines
+@ingroup dac_defines
 
 @li T6: Timer 6 TRGO event
 @li T3: Timer 3 TRGO event
@@ -408,9 +410,11 @@ void dac_software_trigger(data_channel dac_channel);
 END_DECLS
 
 #endif
+/** @cond */
 #else
 #warning "dac_common_all.h should not be included explicitly, only via dac.h"
 #endif
+/** @endcond */
 
 /**@}*/
 

include/libopencm3/stm32/common/dma_common_f13.h

@@ -31,7 +31,9 @@
 The order of header inclusion is important. dma.h includes the device
 specific memorymap.h header before including this header file.*/
 
+/** @cond */
 #ifdef LIBOPENCM3_DMA_H
+/** @endcond */
 #ifndef LIBOPENCM3_DMA_COMMON_F13_H
 #define LIBOPENCM3_DMA_COMMON_F13_H
 
@@ -395,9 +397,11 @@ void dma_set_number_of_data(u32 dma, u8 channel, u16 number);
 END_DECLS
 
 #endif
+/** @cond */
 #else
 #warning "dma_common_f13.h should not be included explicitly, only via dma.h"
 #endif
+/** @endcond */
 
 /**@}*/
 

include/libopencm3/stm32/common/dma_common_f24.h

@@ -28,7 +28,9 @@
 The order of header inclusion is important. dma.h includes the device
 specific memorymap.h header before including this header file.*/
 
+/** @cond */
 #ifdef LIBOPENCM3_DMA_H
+/** @endcond */
 #ifndef LIBOPENCM3_DMA_COMMON_F24_H
 #define LIBOPENCM3_DMA_COMMON_F24_H
 
@@ -608,7 +610,9 @@ void dma_set_number_of_data(u32 dma, u8 stream, u16 number);
 END_DECLS
 /**@}*/
 #endif
+/** @cond */
 #else
 #warning "dma_common_f24.h should not be included explicitly, only via dma.h"
 #endif
+/** @endcond */
 

include/libopencm3/stm32/common/flash_common_f24.h

@@ -25,7 +25,9 @@
  * http://www.st.com/st-web-ui/static/active/en/resource/technical/document/programming_manual/DM00023388.pdf
  */
 
+/** @cond */
 #ifdef LIBOPENCM3_FLASH_H
+/** @endcond */
 #ifndef LIBOPENCM3_FLASH_COMMON_F24_H
 #define LIBOPENCM3_FLASH_COMMON_F24_H
 
@@ -150,7 +152,9 @@ void flash_program_option_bytes(u32 data);
 END_DECLS
 
 #endif
+/** @cond */
 #else
 #warning "flash_common_f24.h should not be included explicitly, only via flash.h"
 #endif
+/** @endcond */
 

include/libopencm3/stm32/common/gpio_common_all.h

@@ -29,7 +29,9 @@
 The order of header inclusion is important. gpio.h includes the device
 specific memorymap.h header before including this header file.*/
 
+/** @cond */
 #if defined (LIBOPENCM3_GPIO_H) || defined (LIBOPENCM3_GPIO_COMMON_F24_H)
+/** @endcond */
 #ifndef LIBOPENCM3_GPIO_COMMON_ALL_H
 #define LIBOPENCM3_GPIO_COMMON_ALL_H
 
@@ -82,7 +84,9 @@ END_DECLS
 
 /**@}*/
 #endif
+/** @cond */
 #else
 #warning "gpio_common_all.h should not be included explicitly, only via gpio.h"
 #endif
+/** @endcond */
 

include/libopencm3/stm32/common/gpio_common_f24.h

@@ -28,7 +28,9 @@
 The order of header inclusion is important. gpio.h includes the device
 specific memorymap.h header before including this header file.*/
 
+/** @cond */
 #ifdef LIBOPENCM3_GPIO_H
+/** @endcond */
 #ifndef LIBOPENCM3_GPIO_COMMON_F24_H
 #define LIBOPENCM3_GPIO_COMMON_F24_H
 
@@ -290,7 +292,9 @@ void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios);
 END_DECLS
 /**@}*/
 #endif
+/** @cond */
 #else
 #warning "gpio_common_f24.h should not be included explicitly, only via gpio.h"
 #endif
+/** @endcond */
 

include/libopencm3/stm32/common/i2c_common_all.h

@@ -27,7 +27,9 @@
 The order of header inclusion is important. i2c.h includes the device
 specific memorymap.h header before including this header file.*/
 
+/** @cond */
 #if defined (LIBOPENCM3_I2C_H) || defined (LIBOPENCM3_I2C_COMMON_F24_H)
+/** @endcond */
 #ifndef LIBOPENCM3_I2C_COMMON_ALL_H
 #define LIBOPENCM3_I2C_COMMON_ALL_H
 
@@ -386,8 +388,10 @@ void i2c_clear_dma_last_transfer(u32 i2c);
 END_DECLS
 
 #endif
+/** @cond */
 #else
 #warning "i2c_common_all.h should not be included explicitly, only via i2c.h"
 #endif
+/** @endcond */
 /**@}*/
 

include/libopencm3/stm32/common/i2c_common_f24.h

@@ -27,7 +27,9 @@
 The order of header inclusion is important. i2c.h includes the device
 specific memorymap.h header before including this header file.*/
 
+/** @cond */
 #ifdef LIBOPENCM3_I2C_H
+/** @endcond */
 #ifndef LIBOPENCM3_I2C_COMMON_F24_H
 #define LIBOPENCM3_I2C_COMMON_F24_H
 
@@ -40,6 +42,9 @@ specific memorymap.h header before including this header file.*/
 /**@}*/
 
 #endif
+/** @cond */
 #else
 #warning "i2c_common_f24.h should not be included explicitly, only via i2c.h"
 #endif
+/** @endcond */
+

include/libopencm3/stm32/common/iwdg_common_all.h

@@ -26,7 +26,9 @@
 The order of header inclusion is important. iwdg.h includes the device
 specific memorymap.h header before including this header file.*/
 
+/** @cond */
 #ifdef LIBOPENCM3_IWDG_H
+/** @endcond */
 #ifndef LIBOPENCM3_IWDG_COMMON_ALL_H
 #define LIBOPENCM3_IWDG_COMMON_ALL_H
 
@@ -112,8 +114,10 @@ void iwdg_reset(void);
 END_DECLS
 
 #endif
+/** @cond */
 #else
 #warning "iwdg_common_all.h should not be included explicitly, only via iwdg.h"
 #endif
+/** @endcond */
 /**@}*/
 

include/libopencm3/stm32/common/pwr_common_all.h

@@ -27,7 +27,9 @@
 The order of header inclusion is important. pwr.h includes the device
 specific memorymap.h header before including this header file.*/
 
+/** @cond */
 #ifdef LIBOPENCM3_PWR_H
+/** @endcond */
 #ifndef LIBOPENCM3_PWR_COMMON_ALL_H
 #define LIBOPENCM3_PWR_COMMON_ALL_H
 
@@ -124,7 +126,9 @@ END_DECLS
 
 /**@}*/
 #endif
+/** @cond */
 #else
 #warning "pwr_common_all.h should not be included explicitly, only via pwr.h"
 #endif
+/** @endcond */
 

include/libopencm3/stm32/common/rng_common_f24.h

@@ -20,7 +20,9 @@
 The order of header inclusion is important. rng.h includes the device
 specific memorymap.h header before including this header file.*/
 
+/** @cond */
 #ifdef LIBOPENCM3_RNG_H
+/** @endcond */
 #ifndef LIBOPENCM3_RNG_COMMON_F24_H
 #define LIBOPENCM3_RNG_COMMON_F24_H
 
@@ -64,7 +66,9 @@ specific memorymap.h header before including this header file.*/
 #define RNG_SR_SEIS		(1 << 6)
 
 #endif
+/** @cond */
 #else
 #warning "rng_common_f24.h should not be included explicitly, only via rng.h"
 #endif
+/** @endcond */
 

include/libopencm3/stm32/common/rtc_common_bcd.h

@@ -34,7 +34,9 @@
 The order of header inclusion is important. rtc.h includes the device
 specific memorymap.h header before including this header file.*/
 
+/** @cond */
 #ifdef LIBOPENCM3_RTC_H
+/** @endcond */
 #ifndef LIBOPENCM3_RTC2_H
 #define LIBOPENCM3_RTC2_H
 
@@ -319,8 +321,10 @@ END_DECLS
 /**@}*/
 
 #endif  /* RTC2_H */
+/** @cond */
 #else
 #warning "rtc_common_bcd.h should not be included explicitly, only via rtc.h"
 #endif
+/** @endcond */
 
 

include/libopencm3/stm32/common/spi_common_all.h

@@ -27,7 +27,9 @@
 The order of header inclusion is important. spi.h includes the device
 specific memorymap.h header before including this header file.*/
 
+/** @cond */
 #if defined (LIBOPENCM3_SPI_H) || defined (LIBOPENCM3_SPI_COMMON_F24_H)
+/** @endcond */
 #ifndef LIBOPENCM3_SPI_COMMON_ALL_H
 #define LIBOPENCM3_SPI_COMMON_ALL_H
 
@@ -405,7 +407,9 @@ END_DECLS
 /**@}*/
 
 #endif
+/** @cond */
 #else
 #warning "spi_common_all.h should not be included explicitly, only via spi.h"
 #endif
+/** @endcond */
 

include/libopencm3/stm32/common/spi_common_f24.h

@@ -26,7 +26,9 @@
 The order of header inclusion is important. spi.h includes the device
 specific memorymap.h header before including this header file.*/
 
+/** @cond */
 #ifdef LIBOPENCM3_SPI_H
+/** @endcond */
 #ifndef LIBOPENCM3_SPI_COMMON_F24_H
 #define LIBOPENCM3_SPI_COMMON_F24_H
 
@@ -53,8 +55,10 @@ specific memorymap.h header before including this header file.*/
 #define SPI_SR_TIFRFE			(1 << 8)
 
 #endif
+/** @cond */
 #else
 #warning "spi_common_f24.h should not be included explicitly, only via spi.h"
 #endif
+/** @endcond */
 /**@}*/
 

include/libopencm3/stm32/common/timer_common_all.h

@@ -29,7 +29,9 @@
 The order of header inclusion is important. timer.h includes the device
 specific memorymap.h header before including this header file.*/
 
+/** @cond */
 #if defined (LIBOPENCM3_TIMER_H) || defined (LIBOPENCM3_TIMER_COMMON_F24_H)
+/** @endcond */
 #ifndef LIBOPENCM3_TIMER_COMMON_H
 #define LIBOPENCM3_TIMER_COMMON_H
 
@@ -1105,8 +1107,10 @@ void timer_slave_set_trigger(u32 timer, u8 trigger);
 END_DECLS
 
 #endif
+/** @cond */
 #else
 #warning "timer_common_all.h should not be included explicitly, only via timer.h"
 #endif
+/** @endcond */
 /**@}*/
 

include/libopencm3/stm32/common/timer_common_f24.h

@@ -27,7 +27,9 @@
 The order of header inclusion is important. timer.h includes the device
 specific memorymap.h header before including this header file.*/
 
+/** @cond */
 #ifdef LIBOPENCM3_TIMER_H
+/** @endcond */
 #ifndef LIBOPENCM3_TIMER_COMMON_F24_H
 #define LIBOPENCM3_TIMER_COMMON_F24_H
 
@@ -102,6 +104,9 @@ void timer_ic_set_polarity(u32 timer, enum tim_ic_id ic, enum tim_ic_pol pol);
 END_DECLS
 
 #endif
+/** @cond */
 #else
 #warning "timer_common_f24.h should not be included explicitly, only via timer.h"
 #endif
+/** @endcond */
+

include/libopencm3/stm32/common/usart_common_all.h

@@ -29,7 +29,9 @@
 The order of header inclusion is important. usart.h includes the device
 specific memorymap.h header before including this header file.*/
 
+/** @cond */
 #if defined (LIBOPENCM3_USART_H) || defined (LIBOPENCM3_USART_COMMON_F24_H)
+/** @endcond */
 #ifndef LIBOPENCM3_USART_COMMON_ALL_H
 #define LIBOPENCM3_USART_COMMON_ALL_H
 
@@ -374,8 +376,10 @@ bool usart_get_interrupt_source(u32 usart, u32 flag);
 END_DECLS
 
 #endif
+/** @cond */
 #else
 #warning "usart_common_all.h should not be included explicitly, only via usart.h"
 #endif
+/** @endcond */
 /**@}*/
 

include/libopencm3/stm32/common/usart_common_f24.h

@@ -28,7 +28,9 @@
 The order of header inclusion is important. usart.h includes the device
 specific memorymap.h header before including this header file.*/
 
+/** @cond */
 #ifdef LIBOPENCM3_USART_H
+/** @endcond */
 #ifndef LIBOPENCM3_USART_COMMON_F24_H
 #define LIBOPENCM3_USART_COMMON_F24_H
 
@@ -72,7 +74,9 @@ specific memorymap.h header before including this header file.*/
 #define USART_CR3_ONEBIT		(1 << 11)
 
 #endif
+/** @cond */
 #else
 #warning "usart_common_f24.h should not be included explicitly, only via usart.h"
 #endif
+/** @endcond */
 

include/libopencm3/stm32/f1/adc.h

@@ -44,7 +44,7 @@ LGPL License Terms @ref lgpl_license
 /* ADC port base addresses (for convenience) */
 /****************************************************************************/
 /** @defgroup adc_reg_base ADC register base addresses
-@ingroup STM32F1xx_adc_defines
+@ingroup adc_defines
 
 @{*/
 #define ADC1				ADC1_BASE
@@ -166,7 +166,7 @@ LGPL License Terms @ref lgpl_license
 
 /****************************************************************************/
 /** @defgroup adc_channel ADC Channel Numbers
-@ingroup STM32F1xx_adc_defines
+@ingroup adc_defines
 
 @{*/
 #define ADC_CHANNEL0		0x00
@@ -225,7 +225,7 @@ LGPL License Terms @ref lgpl_license
 /****************************************************************************/
 /* ADC_CR1 DUALMOD[3:0] ADC Mode Selection */
 /** @defgroup adc_cr1_dualmod ADC Mode Selection
-@ingroup STM32F1xx_adc_defines
+@ingroup adc_defines
 
 @{*/
 /** Independent (non-dual) mode */
@@ -255,7 +255,7 @@ LGPL License Terms @ref lgpl_license
 /* DISCNUM[2:0]: Discontinuous mode channel count. */
 /****************************************************************************/
 /** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode.
-@ingroup STM32F1xx_adc_defines
+@ingroup adc_defines
 
 @{*/
 #define ADC_CR1_DISCNUM_1CHANNELS       (0x0 << 13)
@@ -304,7 +304,7 @@ LGPL License Terms @ref lgpl_license
 /****************************************************************************/
 /* ADC_CR1 AWDCH[4:0] ADC watchdog channel */
 /** @defgroup adc_watchdog_channel ADC watchdog channel
-@ingroup STM32F1xx_adc_defines
+@ingroup adc_defines
 
 @{*/
 #define ADC_CR1_AWDCH_CHANNEL0		(0x00 << 0)
@@ -348,7 +348,7 @@ LGPL License Terms @ref lgpl_license
 /****************************************************************************/
 /* ADC_CR2 EXTSEL[2:0] ADC Trigger Identifier for ADC1 and ADC2 */
 /** @defgroup adc_trigger_regular_12 ADC Trigger Identifier for ADC1 and ADC2
-@ingroup STM32F1xx_adc_defines
+@ingroup adc_defines
 
 @{*/
 /** Timer 1 Compare Output 1 */
@@ -373,7 +373,7 @@ LGPL License Terms @ref lgpl_license
 /****************************************************************************/
 /* ADC_CR2 EXTSEL[2:0] ADC Trigger Identifier for ADC3 */
 /** @defgroup adc_trigger_regular_3 ADC Trigger Identifier for ADC3
-@ingroup STM32F1xx_adc_defines
+@ingroup adc_defines
 
 @{*/
 /** Timer 2 Compare Output 1 */
@@ -405,7 +405,7 @@ LGPL License Terms @ref lgpl_license
 /****************************************************************************/
 /* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC1 and ADC2 */
 /** @defgroup adc_trigger_injected_12 ADC Injected Trigger Identifier for ADC1 and ADC2
-@ingroup STM32F1xx_adc_defines
+@ingroup adc_defines
 
 @{*/
 /** Timer 1 Trigger Output */
@@ -430,7 +430,7 @@ LGPL License Terms @ref lgpl_license
 /****************************************************************************/
 /* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC3 */
 /** @defgroup adc_trigger_injected_3 ADC Injected Trigger Identifier for ADC3
-@ingroup STM32F1xx_adc_defines
+@ingroup adc_defines
 
 @{*/
 /** Timer 1 Trigger Output */
@@ -503,7 +503,7 @@ LGPL License Terms @ref lgpl_license
 /****************************************************************************/
 /* ADC_SMPR1 ADC Sample Time Selection for Channels */
 /** @defgroup adc_sample_r1 ADC Sample Time Selection for ADC1
-@ingroup STM32F1xx_adc_defines
+@ingroup adc_defines
 
 @{*/
 #define ADC_SMPR1_SMP_1DOT5CYC		0x0
@@ -541,7 +541,7 @@ LGPL License Terms @ref lgpl_license
 /****************************************************************************/
 /* ADC_SMPR2 ADC Sample Time Selection for Channels */
 /** @defgroup adc_sample_r2 ADC Sample Time Selection for ADC2
-@ingroup STM32F1xx_adc_defines
+@ingroup adc_defines
 
 @{*/
 #define ADC_SMPR2_SMP_1DOT5CYC		0x0
@@ -558,7 +558,7 @@ LGPL License Terms @ref lgpl_license
 /****************************************************************************/
 /* ADC_SMPRG ADC Sample Time Selection for Channels */
 /** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels
-@ingroup STM32F1xx_adc_defines
+@ingroup adc_defines
 
 @{*/
 #define ADC_SMPR_SMP_1DOT5CYC		0x0
@@ -633,7 +633,7 @@ LGPL License Terms @ref lgpl_license
 /* JL[2:0]: Discontinous mode channel count injected channels. */
 /****************************************************************************/
 /** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro injected channels.
-@ingroup STM32F1xx_adc_defines
+@ingroup adc_defines
 
 @{*/
 #define ADC_JSQR_JL_1CHANNELS       (0x0 << ADC_JSQR_JL_LSB)

lib/stm32/common/crc_common_all.c

@@ -63,6 +63,7 @@ Writes data words consecutively to the register, the write operation stalling
 until the computation of each word is complete.
 
 @param[in] datap Unsigned int32. pointer to an array of 32 bit data words.
+@param[in] size int. Size of the array.
 @returns int32 Final computed CRC result
 */
 

lib/stm32/common/dma_common_f13.c

@@ -88,7 +88,7 @@ The interrupt flag for the channel is returned.
 
 @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
 @param[in] channel unsigned int8. Channel number: @ref dma_ch
-@param[in] interrupt unsigned int32. Interrupt number: @ref dma_ch
+@param[in] interrupt unsigned int32. Interrupt number: @ref dma_if_offset
 @returns bool interrupt flag is set.
 */
 

lib/stm32/common/timer_common_all.c

@@ -95,7 +95,7 @@ push-pull outputs where the PWM output will appear.
 #include <libopencm3/stm32/timer.h>
 #include <libopencm3/stm32/rcc.h>
 
-#define ADVANCED_TIMERS (defined (TIM1_BASE) || defined(TIM8_BASE))
+#define ADVANCED_TIMERS (defined(TIM1_BASE) || defined(TIM8_BASE))
 
 /*---------------------------------------------------------------------------*/
 /** @brief Reset a Timer.
@@ -223,7 +223,7 @@ bool timer_interrupt_source(u32 timer_peripheral, u32 flag)
 	if (((TIM_SR(timer_peripheral) & TIM_DIER(timer_peripheral) & flag) == 0) ||
 		(flag > TIM_SR_BIF)) return false;
 /* Only an interrupt source for advanced timers */
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((flag == TIM_SR_BIF) || (flag == TIM_SR_COMIF))
 		return ((timer_peripheral == TIM1) || (timer_peripheral == TIM8));
 #endif
@@ -499,7 +499,7 @@ If several settings are to be made, use the logical OR of the output control val
 
 void timer_set_output_idle_state(u32 timer_peripheral, u32 outputs)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
     	TIM_CR2(timer_peripheral) |= outputs & TIM_CR2_OIS_MASK;
 #else
@@ -523,7 +523,7 @@ This determines the value of the timer output compare when it enters idle state.
 
 void timer_reset_output_idle_state(u32 timer_peripheral, u32 outputs)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
     	TIM_CR2(timer_peripheral) &= ~(outputs & TIM_CR2_OIS_MASK);
 #else
@@ -616,7 +616,7 @@ outputs.
 
 void timer_enable_compare_control_update_on_trigger(u32 timer_peripheral)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
 		TIM_CR2(timer_peripheral) |= TIM_CR2_CCUS;
 #else
@@ -639,7 +639,7 @@ outputs.
 
 void timer_disable_compare_control_update_on_trigger(u32 timer_peripheral)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
 		TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCUS;
 #else
@@ -661,7 +661,7 @@ outputs.
 
 void timer_enable_preload_complementry_enable_bits(u32 timer_peripheral)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
 		TIM_CR2(timer_peripheral) |= TIM_CR2_CCPC;
 #else
@@ -682,7 +682,7 @@ outputs.
 
 void timer_disable_preload_complementry_enable_bits(u32 timer_peripheral)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
 		TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCPC;
 #else
@@ -718,7 +718,7 @@ count cycles have been completed.
 
 void timer_set_repetition_counter(u32 timer_peripheral, u32 value)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
 		TIM_RCR(timer_peripheral) = value;
 #else
@@ -1136,7 +1136,7 @@ void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id)
 	}
 
 	/* Acting for TIM1 and TIM8 only from here onwards. */
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
 		return;
 #else
@@ -1195,7 +1195,7 @@ void timer_set_oc_polarity_low(u32 timer_peripheral, enum tim_oc_id oc_id)
 	}
 
 	/* Acting for TIM1 and TIM8 only from here onwards. */
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
 		return;
 #else
@@ -1254,7 +1254,7 @@ void timer_enable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id)
 	}
 
 	/* Acting for TIM1 and TIM8 only from here onwards. */
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
 		return;
 #else
@@ -1313,7 +1313,7 @@ void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id)
 	}
 
 	/* Acting for TIM1 and TIM8 only from here onwards. */
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
 		return;
 #else
@@ -1354,7 +1354,7 @@ void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id)
 
 void timer_set_oc_idle_state_set(u32 timer_peripheral, enum tim_oc_id oc_id)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	/* Acting for TIM1 and TIM8 only. */
 	if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
 		return;
@@ -1403,7 +1403,7 @@ void timer_set_oc_idle_state_set(u32 timer_peripheral, enum tim_oc_id oc_id)
 
 void timer_set_oc_idle_state_unset(u32 timer_peripheral, enum tim_oc_id oc_id)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	/* Acting for TIM1 and TIM8 only. */
 	if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
 		return;
@@ -1490,7 +1490,7 @@ timer <b>even if break or deadtime features are not being used</b>.
 
 void timer_enable_break_main_output(u32 timer_peripheral)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
 		TIM_BDTR(timer_peripheral) |= TIM_BDTR_MOE;
 #else
@@ -1511,7 +1511,7 @@ the Master Output Enable in the Break and Deadtime Register.
 
 void timer_disable_break_main_output(u32 timer_peripheral)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
 		TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_MOE;
 #else
@@ -1533,7 +1533,7 @@ break event.
 
 void timer_enable_break_automatic_output(u32 timer_peripheral)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
 		TIM_BDTR(timer_peripheral) |= TIM_BDTR_AOE;
 #else
@@ -1555,7 +1555,7 @@ break event.
 
 void timer_disable_break_automatic_output(u32 timer_peripheral)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
 		TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_AOE;
 #else
@@ -1575,7 +1575,7 @@ Sets the break function to activate when the break input becomes high.
 
 void timer_set_break_polarity_high(u32 timer_peripheral)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
 		TIM_BDTR(timer_peripheral) |= TIM_BDTR_BKP;
 #else
@@ -1595,7 +1595,7 @@ Sets the break function to activate when the break input becomes low.
 
 void timer_set_break_polarity_low(u32 timer_peripheral)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
 		TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_BKP;
 #else
@@ -1615,7 +1615,7 @@ Enables the break function of an advanced timer.
 
 void timer_enable_break(u32 timer_peripheral)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
 		TIM_BDTR(timer_peripheral) |= TIM_BDTR_BKE;
 #else
@@ -1635,7 +1635,7 @@ Disables the break function of an advanced timer.
 
 void timer_disable_break(u32 timer_peripheral)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
 		TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_BKE;
 #else
@@ -1659,7 +1659,7 @@ inactive level as defined by the output polarity.
 
 void timer_set_enabled_off_state_in_run_mode(u32 timer_peripheral)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
 		TIM_BDTR(timer_peripheral) |= TIM_BDTR_OSSR;
 #else
@@ -1682,7 +1682,7 @@ disabled, the output is also disabled.
 
 void timer_set_disabled_off_state_in_run_mode(u32 timer_peripheral)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
 		TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_OSSR;
 #else
@@ -1704,7 +1704,7 @@ inactive level as defined by the output polarity.
 
 void timer_set_enabled_off_state_in_idle_mode(u32 timer_peripheral)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
 		TIM_BDTR(timer_peripheral) |= TIM_BDTR_OSSI;
 #else
@@ -1725,7 +1725,7 @@ timer. When the master output is disabled the output is also disabled.
 
 void timer_set_disabled_off_state_in_idle_mode(u32 timer_peripheral)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
 		TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_OSSI;
 #else
@@ -1748,7 +1748,7 @@ timer reset has occurred.
 
 void timer_set_break_lock(u32 timer_peripheral, u32 lock)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
 		TIM_BDTR(timer_peripheral) |= lock;
 #else
@@ -1777,7 +1777,7 @@ number of DTSC cycles:
 
 void timer_set_deadtime(u32 timer_peripheral, u32 deadtime)
 {
-#if (defined(ADVANCED_TIMERS) && (ADVANCED_TIMERS))
+#if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
 		TIM_BDTR(timer_peripheral) |= deadtime;
 #else
@@ -1824,7 +1824,7 @@ u32 timer_get_counter(u32 timer_peripheral)
 Set the value of a timer's counter register contents.
 
 @param[in] timer_peripheral Unsigned int32. Timer register address base
-@param[in] Unsigned int32. Counter value.
+@param[in] count Unsigned int32. Counter value.
 */
 
 void timer_set_counter(u32 timer_peripheral, u32 count)