STM32F0: Fix PLL multiplication factor for 48MHz setup

It was set to overclocking configuration!
11 years ago · f622437cfb
1 changed files with 2 additions and 2 deletions
--- a/lib/stm32/f0/rcc.c
+++ b/lib/stm32/f0/rcc.c
@ -587,8 +587,8 @@ void rcc_clock_setup_in_hsi_out_48mhz(void)
 	flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);
-	/* 8MHz * 12 / 2 = 24MHz	 */
+	/* 8MHz * 12 / 2 = 48MHz	 */
-	rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL16);
+	rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL12);
 	RCC_CFGR &= RCC_CFGR_PLLSRC;