Adds handling for missing cases. While i2c only has 3 cases, uarts have
all 4, so make sure they're handled properly.
Removes duplicated/redundant definitions.
Adds doxygen wrappers, even if only for internal use.
Fixes: e41ac6ea71 stm32: added peripheral clock get helpers for all stm32
Signed-of-by: Karl Palsson <karlp@tweak.au>
Allows for abstraction for code that's dependent on knowing the source clock
for a peripheral. Implemented a few core peripherals that tend to have clock
tree differences between platforms (USART, timers, I2C, SPI).
We were never going to be capable of supporting every single part
variant with their own files, so stop trying. We've been supporting the
linker script generator for a long time now, so move on from these old
static files.
Breaking: if you were using one of these, and don't wish to use the
linker script generator, you should simply declare a stub linker script,
and include the generic section definitions file, and provide this in
your own application.
Old:
LDSCRIPT = $(OPENCM3_DIR)/lib/stm32/l1/stm32l15xxb.ld
New (linker script generator):
DEVICE=stm32l151cb
New (manual):
* Add file mymemorymap.ld, with contents similar too:
```
MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 48K
}
/* Include the common ld script. */
INCLUDE cortex-m-generic.ld
```
LDSCRIPT=mymemorymap.ld
See ld/README for more information on using the linker script generator
In this commit, support for the different base addresses for different
F7 parts is added, but the mechanism is now in place for L1 and others.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
(whitespace fixed, commit msg reworded)
Unlike with the doxygen source generation, we can't autoguess which of
the class files are eligible automatically. Instead, make a stub hid
file, (which we can now start adding to, if desired) and include it in
all builds that include other class stubs.
Add basically what's needed to have some minimal but usefull subset of
function for a timer: irqs, compare, period, out polarity, enable/disable
and start.
The leading - makes it rather inconsistent with the majority of other
projects around the world. Use the form everyone else uses.
To solve this, properly pass prefix to inner makes as was always
intended.
Fixes: https://github.com/libopencm3/libopencm3/issues/1058
Turns out, there's lots of common code for flash. Pull up prefetch
on/off to start with, as there's only a single bit name different.
Pull up the definitions of common API functions too, starting with
flash_set_ws. Even if the implementations are different, things that
meant to be the same, should be defined centrally.
STM32L0 uses the same DMA peripheral as STM32F0, F1, L1 and others
with some differences. Those are mostly in the number of supported
controllers and channels.
This patch enables the basic support with no attempt to only expose
the available controllers / channels.
For more information see the ST Application Note AN2548.
Signed-off-by: Martin Sivak <mars@montik.net>
split spi stuff in three part:
- v1 : basic spi peripheral
- v1_frf : v1 spi with frf mode additional bit in spi_cr2 / spi_sr
- v2 : spi with variable datasize, fifo and other fancy stuff.
v1 maps to f1 chips
v1_frf to f2, f4 and l0,l1
v2 to f0, f3 and l4
This breaks spi_master_init API for v2 devices : function prototype from
common spi header used to be abused, with DFF bit reused for CRCL bit.
New v2 spi_master_init does not handle anymore CRCL bits, as it does not
usually mess with other crc configuration.
Instead of every "simple" target having their own duplicate file with
all the section mappings, just provide a single, simple,
"cortex-m-generic.ld" that works with our startup code and any simple
rom/ram system. This also drops the pointless copying of files all over
the place. Using -L flags properly is sufficient, and the standard file
is now in the root of the library already.
rcc_osc_bypass_enable and rcc_osc_bypass_disable have been copy/pasted
around for the last time! There's a compile bit to check for L0/L1, but
otherwise this is just code duplication for no gain.
According to reference manuals both l0 and l4 have "v2" i2c peripheral.
This patch adds i2c support to l0 and l4 using previously unified "v2" i2c
headers and implementation.
No real hardware has been tested so far. Only compilation tests for both
libopencm3 and libopencm3-examples for all stm32 families.
Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
Tested with a Lora radio application that used three GPIO lines to send
different interrupts from the radio module to the L052. Tested with a
Jeenode Zero Rev1
Start providing async routines for all blocking routines, to make it
easier to use libopencm3 in some RTOS environments. This is not in
anyway intended to be complete, this just covers a single blocking
routine, rcc_wait_for_osc_ready. Documentation added to the top level,
and provided for all stm32 families.
Now that the big pieces of the adc-v2 common files are in place, start
including l0 in the builds. This includes only the very very basic core v2
peripheral functions, and the very basic definitions.
As done by esden for the F4, remove typedefs and add prefixes to clock enums
This extends this to all stm32 families.
Let's not hide the fact that these variables are structs/enums.
We are filling up the namespace badly enough, we should be prefixing as
much as we can with the module names at least. As users we already run
often enough in namespace colisions we don't have to make it worse.
* CLOCK_3V3_xxx enums renamed to RCC_CLOCK_3V3_xxx
* clock enums (PLL, HSI, HSE ...) prefixed with RCC_
* scale enum of pwr module prefixed with PWR_
Renamed every instance of variable CFLAGS in target specific Makefiles
to TGT_CFLAGS to free up CFLAGS for user defined compiler flags.
Added information in README.md about existence and usage of CFLAGS
environment variable in build process.