The order of the UCPD1 and UCPD2 bits as described by the
rcc_periph_clken and rcc_periph_rst enums is swapped with regard to the
datasheet. Swap them.
Fixes: https://github.com/libopencm3/libopencm3/issues/234
uses the new mechanisms introduced to address a similar problem on F7.
Tested on a medium density part (0x429) that returns the same ids as
before, tested on a high density part that now _doesnt_, but that's now
correct :)
Reduced the sea of enums, and renamed config parameters to match other
implementations, cribbing off of the G0 config, as it is closer to the level
of complexity. Updated initialization code to utilize the new values.
Added flash and LDO configuration from RCC init to be more consistent with
STM32 platform initialization.
PLL configuration on the H7 is pretty involved, and takes a number of
configurations to make it work. In order to make peripheral drivers a bit
easier to implement, working with a soft clock tree in the rcc module which
stores the clock settings for each clock as they are setup such that users
can request the clock value from the RCC module for configuration. Added
getter for the clock which allows the user to pass the base address of the
peripheral, and get the peripheral clock value for convenience.
Clock configuration is still missing values for setting up all of the kernel
clocks for the peripherals, but this is in work, and there is a framework to
do so.
Have tested to 400MHz without issue. Peripherals that are explicitly supported
are working and the clock tree values appear to follow correctly.
Added LDO settings to allow setting the scaling to support high frequencies.
In this commit, support for the different base addresses for different
F7 parts is added, but the mechanism is now in place for L1 and others.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
(whitespace fixed, commit msg reworded)
We don't need groupings around each enum, they format nicely into a
section already. Likewise, the doxygen _is_ documentation, so we don't
need extra versions of it in places. Also fix a few warnings generated.
According to L4/L0/G0 RM, in case of clock error, interrupt flag must
be cleared, and CECS flag should be cleared as soon as clock meets
requirement.
Reviewed-on: https://github.com/libopencm3/libopencm3/pull/1062
If noise source error occurs, flag must be cleared and data register
must be discarded (at least 12 reads to flush pipeline on G0). Other
device mention start/restart of chip, so, do both (better safe than
sorry).
Reviewed-on: https://github.com/libopencm3/libopencm3/pull/1062
- match the same logic as the f0 api
- use ADC_CFGR1_AWD1CH_VAL macro to mask the channel bits
- don't check if channel is < 18q
- enable the awd in addition to setting the selection to single channel monitoring (in following with the signature and @brief 'enable'
rtc_common_all never existed, and f3 has the same "v2" peripheral used
by ~all parts other than the f1. We don't have any f3 rtc test code,
but the existing code was clearly wrong, and this is at least including
the correct basic defines.
Fixes: https://github.com/libopencm3/libopencm3/issues/1106
A normal git clone doesn't catch these, as it _knows_ that the files are
in the git repo and should be tracked. However, downloading a tarball,
and adding it to a new git repo shows up the problem as important files
are simply not added, and would be dropped by git clean.
Reported-by: https://github.com/libopencm3/libopencm3/issues/1153
Guillaume Revaillot
Guillaume Revaillot
Karl Palsson
Kevin Stefanik
Guillaume Revaillot
Florian Larysch
Brian Viele
François Finfe
Matthew Lai
dima
Jakob Haufe
Caleb Szalacinski
Fabio Pugliese Ornellas
Jacob Walser
balanceTWK
Brian Cooke