The original rcc_peripheral_enable_clock aren't explicitly deprecated,
as they do let you enable multiple periphs in one call. But they're
error prone, from user feedback, so update the docs to ensure people
know what the other options are.
Original code used the special macros for rcc_periph_clock_enable
instead of the appropraite APB1ENR bit definition.
Switch to the correct, simpler form, using the correct parameter.
Updates to a base set of includes to map to the h7 include files which are
mainly based on the f7 versions for simple devices (e.g. SPI, USART, GPIO).
Custom files that have been implemented from the datasheet/ref manual include
the memory map, RCC, PWR definitions, and irq.json file for generation of
nvic files for interrupt mapping.
Additional functionality, especially PLL and tweaks for non-F7 compatible
implementations coming in future commits.
Added documentation tree configuration.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Changed dmaX_streamX to dmaX_strX in a few places for consistency
v2 "single" peripheral with a couple of tweaks :
- added registers to configure two additionnal advanced analog watchdog.
- different adc sampling time time based on channel groups.
- 8 steps adc sequence injection, using chselr/chselrmode.
And a note on the rm explaining that after every configuration change to ADC_CFGR1's
SCANDIR or CHSELRMOD or CHSELR register, user need to check that configuration
is applied before any other modification / adc conversion start.. making adc_set_reqular
a bit painfull to read..
DMAMUX peripheral is a dma request router/trigger, present on g0, wb, h7 and l4+.
Basically it allows to easily map peripheral requests to whatever dma channel we
want to use (similarily to the DMA_CSELR register, but without limitation) but,
it also also adds some clever dma request synchronization and even some dma request
generation logic via internal request generator "channels", allowing some requests
chaining, or triggering reqs from non dma capable peripherals.
nb: g0 only features 1 dmamux bloc, supports 7 irq and 4 generators, l4+ supports 13
dma channels and 3 generators and h7 has two dmamuxes, with support for the 15 dma
channels and 7 generators - so as much CxCR and RGxCR register - but they are bit
to bit compatible - excluding of course the sync/sig and dma requests id mappings.
btw, currently, request generator channels are defined in common header, but maybe
we should define them in device header ? or we dont care (like for dma channels,
only defined in dma_f24 but not for other devices ?).
See ST AN5224 for more information
same same, bit for bit, except not ;) - Channel request mapping now
depends on a new DMAMUX peripheral, and there's no default preset.
So, before enabling dma channel after its configuration, request
must be configured by :
dmamux_set_dma_channel_request(DMAMUX1, DMA_CHANNELx, request_number_from_datasheet);
Updates the main memory map and the makefile.
Adds the SWM050 to devices.data, so that a linker script can be automatically generated.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Add basically what's needed to have some minimal but usefull subset of
function for a timer: irqs, compare, period, out polarity, enable/disable
and start.
Fix some direct includes, tag properly, include a stub file to pull in
shared header documentation and re-arrange some existing documentation
to make it present nicely.
Was completely undocumented before. Just needed different tagging so it
could be picked up.
No attempt at this stage of sharing more code between the cmu modules.
gpio_common was built, but wasn't picked up by any documentation.
Use the peripheral_apis style from stm32, but try out the #pragma once
style. Downside is you don't get warnings if you include an sub layer
.h file. Upsides are
* no ifdef/endif blocks
* no /**@cond*/ /**@endcond*/ blocks
* that's enough win!
Karl Palsson
TomasPech
Mathias Nord
Brian Viele
Karl Palsson
Caleb Szalacinski
Guillaume Revaillot
Matt Anderson
Nicholas Rossomando
Jonathan Halmen
Guillaume Revaillot