Was completely undocumented before. Just needed different tagging so it
could be picked up.
No attempt at this stage of sharing more code between the cmu modules.
gpio_common was built, but wasn't picked up by any documentation.
Use the peripheral_apis style from stm32, but try out the #pragma once
style. Downside is you don't get warnings if you include an sub layer
.h file. Upsides are
* no ifdef/endif blocks
* no /**@cond*/ /**@endcond*/ blocks
* that's enough win!
F09x and L4 share the same cselr register, as well as some L0s, factorize
definitions in a new shared header and add helpers.
fyi, that register allows to redefine dma channel peripheral mapping - see
device datasheet for mapping tables.
Regular rng peripheral, with one additional bit : clock error detection
apparently available on l4 chips). Curiously, Clock error detection is
_disabled_ when bit is set, but bit is cleared by default, so peripheral
/ clock error detection behaves like all other chips..
NB: RNG need proper rcc_ccicr_rngsel bits set to work, no clock is set by
default. Note also that on that chip fRNGCLK must be higher than fHCLK/32
You can't have two mainpage items, and the second was just being
ignored. This restores them, which makes the left side list longer,
which we may or may not like, but it's at least how it was documented to
be.
The internal stack has a hard internal limit of 8, which is as many as
all supported devices support, but not as flexible as the arbitrary
addressing that USB actually allows.
At _least_ document this.
Fixes: https://github.com/libopencm3/libopencm3/issues/666
* Include the doc-swm050.h core file that defines the base groups.
* Fix/tweak groupings to make things consistent with other targets.
* Drop redundant type information. That's all included from the function
signatures automatically by doxygen.
* Added register descriptions from datasheet.
Karl Palsson
Karl Palsson
Guillaume Revaillot
Eric Van Albert