STM32L0 uses the same DMA peripheral as STM32F0, F1, L1 and others
with some differences. Those are mostly in the number of supported
controllers and channels.
This patch enables the basic support with no attempt to only expose
the available controllers / channels.
For more information see the ST Application Note AN2548.
Signed-off-by: Martin Sivak <mars@montik.net>
split spi stuff in three part:
- v1 : basic spi peripheral
- v1_frf : v1 spi with frf mode additional bit in spi_cr2 / spi_sr
- v2 : spi with variable datasize, fifo and other fancy stuff.
v1 maps to f1 chips
v1_frf to f2, f4 and l0,l1
v2 to f0, f3 and l4
This breaks spi_master_init API for v2 devices : function prototype from
common spi header used to be abused, with DFF bit reused for CRCL bit.
New v2 spi_master_init does not handle anymore CRCL bits, as it does not
usually mess with other crc configuration.
Instead of every "simple" target having their own duplicate file with
all the section mappings, just provide a single, simple,
"cortex-m-generic.ld" that works with our startup code and any simple
rom/ram system. This also drops the pointless copying of files all over
the place. Using -L flags properly is sufficient, and the standard file
is now in the root of the library already.
Somewhat replaces some earlier work done by hg/lg, but much more
complete, so we kept it as is, because it's bringing in even more parts
after this.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
The original submitter of this squished everything into one series, and
has not returned. The code mostly appears good, and review comments were
followed for the most part. The project doesn't really maintain any
testing or board farm for sam3/sam4 parts, so we're going to just trust
our users.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
sam/4l: IRQ Configuration file (irq.json)
sam/4l: Basic Memory Map.
sam/4l: GPIO Defines.
sam/4l: GPIO Functions
Added everything that needed to compile the library: Makefile, Linker
Script and common includes.
sam/4l: SCIF function to start OSC.
sam/4l: GPIO Enable/Disable and Multiplexing configuration functions.
sam/4l: PLL Clock configuration.
sam/4l: Peripheral clock configuration and basic USART support.
sam: USART Character length configuration.
sam/4l: Generic Clock configuration functions.
sam/4l: Analog to Digital Converter Interface (ADCIFE) basic support.
Originally sourced from: https://github.com/libopencm3/libopencm3/pull/382
fixed some typos from the manual and poor merging/rebaseing,
and one judgment call on using a specific name for a conflicting
bit definition.
The stm32fx07 is common DesignWare IP, used in both STM32 and EFM32 chips.
Rename the files to make this more clear, and easier to use in other
targets.
Makefile doesn't even refer to it, and it's empty anyway. Not required
for doxygen purposes, (anymore?) so just drop it. File had _never_ been
included in the f3 makefile.
The ADC v2 peripheral doesn't have the same behaviour of starting, where
the hardware clears the bit immediately, on v2, it is not cleared until
the ADC is stopped, or the end of sequence flag is set.
Fixes https://github.com/libopencm3/libopencm3/issues/557
The SPI br parameter has always been the 3 bit fpclk divider field, and
was never a target or explicit bit rate. Correct the comments, and drop
the duplicate commentary that wasn't included in the doxygen output
anyway.
Fixes: a7a3770d Add initial SPI code
Karl Palsson
Martin Sivak
Guillaume Revaillot
kbob
Maxim Sloyko
Jordi Pakey-Rodriguez
Frantisek Burian
Sebastian Holzapfel
Joel Holdsworth
Bruno Randolf
Gregory Schlomoff
Grigory Revzin
Cem Basoglu
Karl Palsson
Paul Fertser