The original submitter of this squished everything into one series, and
has not returned. The code mostly appears good, and review comments were
followed for the most part. The project doesn't really maintain any
testing or board farm for sam3/sam4 parts, so we're going to just trust
our users.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
sam/4l: IRQ Configuration file (irq.json)
sam/4l: Basic Memory Map.
sam/4l: GPIO Defines.
sam/4l: GPIO Functions
Added everything that needed to compile the library: Makefile, Linker
Script and common includes.
sam/4l: SCIF function to start OSC.
sam/4l: GPIO Enable/Disable and Multiplexing configuration functions.
sam/4l: PLL Clock configuration.
sam/4l: Peripheral clock configuration and basic USART support.
sam: USART Character length configuration.
sam/4l: Generic Clock configuration functions.
sam/4l: Analog to Digital Converter Interface (ADCIFE) basic support.
Thoughts: should this be a "sam0" family rather than samd? (Much like Atmel's
own software package lumps all the cortex-m0+ devices in one family)
This was enough to get a basic blinky working at least.
Newlib and arm-non-eabi-gcc likes to use the FPU by default on
Cortex-M4F chips. AS a result, do the right thing and enable the FPU
by default.
This fixes issues where code is generated which uses the FPU and
causes the CPU to hard-fault. This change removes the responsibility
of FPU initialization from the application code.
This makes the lm4f consistent with other M4+ devices that enable the
FPU in core library startup code.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Helpful if you don't like seeing:
(gdb) vecstate
HardFault: forced due to escalated or disabled configurable fault (see below)
UsageFault due to access to disabled/absent coprocessor
Values from RM0351rev1, with the correction of the duplicate TIM1_CC entry.
Only stub support so far, but this opens up the beginning of build testing.
Most changes are noise from doxygen.
Readme udpated to explain newer FP_FLAGS for m7
stm32f7 library is skipped if the toolchain doesn't support it yet.
Freescale Vybrid is a familiy of ARM SoC, wheras the VF6xx models
have two cores in one SoC, a Cortex-A5 and a Cortex-M4. This adds
initial support for the Cortex-M4 in the libopencm3 library.
By using two different ram areas (pc_ram and ps_ram) the user can
put the code in a RAM area bounded to the code bus. The data can
be stored in the data area. However, currently the initial values
of for the variables in the data section are stored in the code
section and copied to the ram section by the initialization code
(like it's copied from ROM to RAM on microcontrollers).
Added --terse and --mailback options to the make stylecheck target. It
also does continue even if it enounters a possible error.
We decided on two exceptions from the linux kernel coding standard:
- Empty wait while loops may end with ; on the same line.
- All blocks after while, if, for have to be in brackets even if they
only contain one statement. Otherwise it is easy to introduce an
error.
Checkpatch needs to be adapted to reflect those changes.
Add an "#ifdef(LM4F)" clause to include/libopencm3/dispatch/nvic.h
and lib/dispatch/vector_nvic.c. This compiles in the vector table
and allows interrupts to be used.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
the LM3S irq list was previously unused as it was missing in the
dispatch files; now it got added. (before HEAD^, it wouldn't have made
any difference because the discriminating constant wasn't defined
anyway)
also, this enhances the warning messages
Dmitry Rezvanov
kbob
Maxim Sloyko
Sebastian Holzapfel
Karl Palsson
Alexandru Gagniuc
Kuldeep Singh Dhaka
Frantisek Burian
Stefan Agner
Felix Held
Federico Ruiz Ugalde
Ben Gamari
Piotr Esden-Tempski
Gareth McMullin
Gareth McMullin
Silvio Gissi
chrysn