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550 lines
16 KiB
550 lines
16 KiB
/** @defgroup can_file CAN
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@ingroup STM32F_files
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@brief <b>libopencm3 STM32Fxxx CAN</b>
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
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@date 12 November 2012
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Devices can have up to two CAN peripherals. The peripherals support up to 1MBit
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transmission rate. The peripheral has several filters for incoming messages that
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can be distributed between two FIFOs and three transmit mailboxes.
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/stm32/can.h>
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#include <libopencm3/stm32/rcc.h>
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/* Timeout for CAN INIT acknowledge
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* this value is difficult to define.
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* INIT is set latest after finishing the current transfer.
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* Assuming the lowest CAN speed of 100kbps one CAN frame may take about 1.6ms
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* WAIT loop timeout varies on compiler switches, optimization, CPU architecture
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* and CPU speed
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*
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* The same timeout value is used for leaving INIT where the longest time is
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* 11 bits(110 us on 100 kbps).
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*/
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#define CAN_MSR_INAK_TIMEOUT 0x0000FFFF
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/*---------------------------------------------------------------------------*/
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/** @brief CAN Reset
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The CAN peripheral and all its associated configuration registers are placed in
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the reset condition. The reset is effective via the RCC peripheral reset
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system.
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@param[in] canport Unsigned int32. CAN block register address base @ref
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can_reg_base.
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*/
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void can_reset(uint32_t canport)
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{
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if (canport == CAN1) {
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rcc_periph_reset_pulse(RST_CAN1);
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} else {
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#if defined(BX_CAN2_BASE)
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rcc_periph_reset_pulse(RST_CAN2);
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#endif
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief CAN Init
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Initialize the selected CAN peripheral block.
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@param[in] canport Unsigend int32. CAN register base address @ref can_reg_base.
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@param[in] ttcm bool. Time triggered communication mode.
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@param[in] abom bool. Automatic bus-off management.
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@param[in] awum bool. Automatic wakeup mode.
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@param[in] nart bool. No automatic retransmission.
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@param[in] rflm bool. Receive FIFO locked mode.
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@param[in] txfp bool. Transmit FIFO priority.
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@param[in] sjw Unsigned int32. Resynchronization time quanta jump width.
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@param[in] ts1 Unsigned int32. Time segment 1 time quanta width.
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@param[in] ts2 Unsigned int32. Time segment 2 time quanta width.
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@param[in] brp Unsigned int32. Baud rate prescaler.
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@returns int 0 on success, 1 on initialization failure.
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*/
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int can_init(uint32_t canport, bool ttcm, bool abom, bool awum, bool nart,
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bool rflm, bool txfp, uint32_t sjw, uint32_t ts1, uint32_t ts2,
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uint32_t brp, bool loopback, bool silent)
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{
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volatile uint32_t wait_ack;
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int ret = 0;
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/* Exit from sleep mode. */
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CAN_MCR(canport) &= ~CAN_MCR_SLEEP;
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/* Request initialization "enter". */
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CAN_MCR(canport) |= CAN_MCR_INRQ;
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/* Wait for acknowledge. */
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wait_ack = CAN_MSR_INAK_TIMEOUT;
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while ((--wait_ack) &&
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((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK));
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/* Check the acknowledge. */
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if ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK) {
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return 1;
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}
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/* clear can timing bits */
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CAN_BTR(canport) = 0;
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/* Set the automatic bus-off management. */
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if (ttcm) {
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CAN_MCR(canport) |= CAN_MCR_TTCM;
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} else {
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CAN_MCR(canport) &= ~CAN_MCR_TTCM;
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}
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if (abom) {
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CAN_MCR(canport) |= CAN_MCR_ABOM;
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} else {
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CAN_MCR(canport) &= ~CAN_MCR_ABOM;
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}
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if (awum) {
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CAN_MCR(canport) |= CAN_MCR_AWUM;
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} else {
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CAN_MCR(canport) &= ~CAN_MCR_AWUM;
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}
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if (nart) {
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CAN_MCR(canport) |= CAN_MCR_NART;
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} else {
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CAN_MCR(canport) &= ~CAN_MCR_NART;
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}
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if (rflm) {
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CAN_MCR(canport) |= CAN_MCR_RFLM;
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} else {
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CAN_MCR(canport) &= ~CAN_MCR_RFLM;
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}
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if (txfp) {
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CAN_MCR(canport) |= CAN_MCR_TXFP;
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} else {
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CAN_MCR(canport) &= ~CAN_MCR_TXFP;
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}
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if (silent) {
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CAN_BTR(canport) |= CAN_BTR_SILM;
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} else {
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CAN_BTR(canport) &= ~CAN_BTR_SILM;
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}
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if (loopback) {
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CAN_BTR(canport) |= CAN_BTR_LBKM;
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} else {
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CAN_BTR(canport) &= ~CAN_BTR_LBKM;
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}
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/* Set bit timings. */
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CAN_BTR(canport) |= sjw | ts2 | ts1 |
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((brp - 1ul) & CAN_BTR_BRP_MASK);
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/* Request initialization "leave". */
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CAN_MCR(canport) &= ~CAN_MCR_INRQ;
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/* Wait for acknowledge. */
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wait_ack = CAN_MSR_INAK_TIMEOUT;
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while ((--wait_ack) &&
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((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK));
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if ((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK) {
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ret = 1;
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}
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return ret;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief CAN Filter Init
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Initialize incoming message filter and assign to FIFO.
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@param[in] nr Unsigned int32. ID number of the filter.
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@param[in] scale_32bit true for single 32bit, false for dual 16bit
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@param[in] id_list_mode true for id lists, false for id/mask
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@param[in] fr1 Unsigned int32. First filter register content.
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@param[in] fr2 Unsigned int32. Second filter register content.
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@param[in] fifo Unsigned int32. FIFO id.
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@param[in] enable bool. Enable filter?
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*/
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void can_filter_init(uint32_t nr, bool scale_32bit,
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bool id_list_mode, uint32_t fr1, uint32_t fr2,
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uint32_t fifo, bool enable)
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{
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uint32_t filter_select_bit = 0x00000001 << nr;
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/* Request initialization "enter". */
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CAN_FMR(CAN1) |= CAN_FMR_FINIT;
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/* Deactivate the filter. */
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CAN_FA1R(CAN1) &= ~filter_select_bit;
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if (scale_32bit) {
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/* Set 32-bit scale for the filter. */
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CAN_FS1R(CAN1) |= filter_select_bit;
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} else {
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/* Set 16-bit scale for the filter. */
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CAN_FS1R(CAN1) &= ~filter_select_bit;
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}
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if (id_list_mode) {
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/* Set filter mode to ID list mode. */
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CAN_FM1R(CAN1) |= filter_select_bit;
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} else {
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/* Set filter mode to id/mask mode. */
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CAN_FM1R(CAN1) &= ~filter_select_bit;
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}
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/* Set the first filter register. */
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CAN_FiR1(CAN1, nr) = fr1;
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/* Set the second filter register. */
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CAN_FiR2(CAN1, nr) = fr2;
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/* Select FIFO0 or FIFO1 as filter assignement. */
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if (fifo) {
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CAN_FFA1R(CAN1) |= filter_select_bit; /* FIFO1 */
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} else {
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CAN_FFA1R(CAN1) &= ~filter_select_bit; /* FIFO0 */
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}
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if (enable) {
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CAN_FA1R(CAN1) |= filter_select_bit; /* Activate filter. */
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}
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/* Request initialization "leave". */
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CAN_FMR(CAN1) &= ~CAN_FMR_FINIT;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief CAN Initialize a 16bit Message ID Mask Filter
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@param[in] nr Unsigned int32. ID number of the filter.
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@param[in] id1 Unsigned int16. First message ID to filter.
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@param[in] mask1 Unsigned int16. First message ID bit mask.
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@param[in] id2 Unsigned int16. Second message ID to filter.
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@param[in] mask2 Unsigned int16. Second message ID bit mask.
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@param[in] fifo Unsigned int32. FIFO id.
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@param[in] enable bool. Enable filter?
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*/
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void can_filter_id_mask_16bit_init(uint32_t nr, uint16_t id1,
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uint16_t mask1, uint16_t id2,
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uint16_t mask2, uint32_t fifo, bool enable)
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{
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can_filter_init(nr, false, false,
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((uint32_t)mask1 << 16) | (uint32_t)id1,
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((uint32_t)mask2 << 16) | (uint32_t)id2, fifo, enable);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief CAN Initialize a 32bit Message ID Mask Filter
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@param[in] nr Unsigned int32. ID number of the filter.
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@param[in] id Unsigned int32. Message ID to filter.
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@param[in] mask Unsigned int32. Message ID bit mask.
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@param[in] fifo Unsigned int32. FIFO id.
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@param[in] enable bool. Enable filter?
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*/
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void can_filter_id_mask_32bit_init(uint32_t nr, uint32_t id,
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uint32_t mask, uint32_t fifo, bool enable)
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{
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can_filter_init(nr, true, false, id, mask, fifo, enable);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief CAN Initialize a 16bit Message ID List Filter
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@param[in] nr Unsigned int32. ID number of the filter.
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@param[in] id1 Unsigned int16. First message ID to match.
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@param[in] id2 Unsigned int16. Second message ID to match.
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@param[in] id3 Unsigned int16. Third message ID to match.
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@param[in] id4 Unsigned int16. Fourth message ID to match.
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@param[in] fifo Unsigned int32. FIFO id.
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@param[in] enable bool. Enable filter?
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*/
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void can_filter_id_list_16bit_init(uint32_t nr,
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uint16_t id1, uint16_t id2,
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uint16_t id3, uint16_t id4,
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uint32_t fifo, bool enable)
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{
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can_filter_init(nr, false, true,
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((uint32_t)id1 << 16) | (uint32_t)id2,
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((uint32_t)id3 << 16) | (uint32_t)id4, fifo, enable);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief CAN Initialize a 32bit Message ID List Filter
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@param[in] nr Unsigned int32. ID number of the filter.
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@param[in] id1 Unsigned int32. First message ID to match.
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@param[in] id2 Unsigned int32. Second message ID to match.
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@param[in] fifo Unsigned int32. FIFO id.
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@param[in] enable bool. Enable filter?
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*/
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void can_filter_id_list_32bit_init(uint32_t nr,
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uint32_t id1, uint32_t id2,
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uint32_t fifo, bool enable)
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{
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can_filter_init(nr, true, true, id1, id2, fifo, enable);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief CAN Enable IRQ
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@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
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@param[in] irq Unsigned int32. IRQ bit(s).
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*/
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void can_enable_irq(uint32_t canport, uint32_t irq)
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{
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CAN_IER(canport) |= irq;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief CAN Disable IRQ
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@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
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@param[in] irq Unsigned int32. IRQ bit(s).
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*/
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void can_disable_irq(uint32_t canport, uint32_t irq)
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{
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CAN_IER(canport) &= ~irq;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief CAN Transmit Message
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@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
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@param[in] id Unsigned int32. Message ID.
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@param[in] ext bool. Extended message ID?
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@param[in] rtr bool. Request transmit?
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@param[in] length Unsigned int8. Message payload length.
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@param[in] data Unsigned int8[]. Message payload data.
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@returns int 0, 1 or 2 on success and depending on which outgoing mailbox got
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selected. -1 if no mailbox was available and no transmission got queued.
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*/
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int can_transmit(uint32_t canport, uint32_t id, bool ext, bool rtr,
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uint8_t length, uint8_t *data)
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{
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int ret = 0;
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uint32_t mailbox = 0;
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union {
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uint8_t data8[4];
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uint32_t data32;
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} tdlxr, tdhxr;
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/* Check which transmit mailbox is empty if any. */
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if ((CAN_TSR(canport) & CAN_TSR_TME0) == CAN_TSR_TME0) {
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ret = 0;
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mailbox = CAN_MBOX0;
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} else if ((CAN_TSR(canport) & CAN_TSR_TME1) == CAN_TSR_TME1) {
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ret = 1;
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mailbox = CAN_MBOX1;
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} else if ((CAN_TSR(canport) & CAN_TSR_TME2) == CAN_TSR_TME2) {
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ret = 2;
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mailbox = CAN_MBOX2;
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} else {
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ret = -1;
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}
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/* If we have no empty mailbox return with an error. */
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if (ret == -1) {
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return ret;
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}
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if (ext) {
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/* Set extended ID. */
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CAN_TIxR(canport, mailbox) = (id << CAN_TIxR_EXID_SHIFT) |
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CAN_TIxR_IDE;
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} else {
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/* Set standard ID. */
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CAN_TIxR(canport, mailbox) = id << CAN_TIxR_STID_SHIFT;
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}
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/* Set/clear remote transmission request bit. */
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if (rtr) {
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CAN_TIxR(canport, mailbox) |= CAN_TIxR_RTR; /* Set */
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}
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/* Set the DLC. */
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CAN_TDTxR(canport, mailbox) &= ~CAN_TDTxR_DLC_MASK;
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CAN_TDTxR(canport, mailbox) |= (length & CAN_TDTxR_DLC_MASK);
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switch (length) {
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case 8:
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tdhxr.data8[3] = data[7];
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/* fall through */
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case 7:
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tdhxr.data8[2] = data[6];
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/* fall through */
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case 6:
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tdhxr.data8[1] = data[5];
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/* fall through */
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case 5:
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tdhxr.data8[0] = data[4];
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/* fall through */
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case 4:
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tdlxr.data8[3] = data[3];
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/* fall through */
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case 3:
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tdlxr.data8[2] = data[2];
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/* fall through */
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case 2:
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tdlxr.data8[1] = data[1];
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/* fall through */
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case 1:
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tdlxr.data8[0] = data[0];
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/* fall through */
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default:
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break;
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}
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/* Set the data. */
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CAN_TDLxR(canport, mailbox) = tdlxr.data32;
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CAN_TDHxR(canport, mailbox) = tdhxr.data32;
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/* Request transmission. */
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CAN_TIxR(canport, mailbox) |= CAN_TIxR_TXRQ;
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return ret;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief CAN Release FIFO
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@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
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@param[in] fifo Unsigned int8. FIFO id.
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*/
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void can_fifo_release(uint32_t canport, uint8_t fifo)
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{
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if (fifo == 0) {
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CAN_RF0R(canport) |= CAN_RF1R_RFOM1;
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} else {
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CAN_RF1R(canport) |= CAN_RF1R_RFOM1;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief CAN Receive Message
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@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
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@param[in] fifo Unsigned int8. FIFO id.
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@param[in] release bool. Release the FIFO automatically after coping data out.
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@param[out] id Unsigned int32 pointer. Message ID.
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@param[out] ext bool pointer. The message ID is extended?
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@param[out] rtr bool pointer. Request of transmission?
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@param[out] fmi Unsigned int8 pointer. ID of the matched filter.
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@param[out] length Unsigned int8 pointer. Length of message payload.
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@param[out] data Unsigned int8[]. Message payload data.
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@param[out] timestamp Pointer to store the message timestamp.
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Only valid on time triggered CAN. Use NULL to ignore.
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*/
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void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id,
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bool *ext, bool *rtr, uint8_t *fmi, uint8_t *length,
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uint8_t *data, uint16_t *timestamp)
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{
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uint32_t fifo_id = 0;
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union {
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uint8_t data8[4];
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uint32_t data32;
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} rdlxr, rdhxr;
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const uint32_t fifoid_array[2] = {CAN_FIFO0, CAN_FIFO1};
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fifo_id = fifoid_array[fifo];
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/* Get type of CAN ID and CAN ID. */
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if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_IDE) {
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*ext = true;
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/* Get extended CAN ID. */
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*id = (CAN_RIxR(canport, fifo_id) >> CAN_RIxR_EXID_SHIFT) &
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CAN_RIxR_EXID_MASK;
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} else {
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*ext = false;
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/* Get standard CAN ID. */
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*id = (CAN_RIxR(canport, fifo_id) >> CAN_RIxR_STID_SHIFT) &
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CAN_RIxR_STID_MASK;
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}
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/* Get remote transmit flag. */
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if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_RTR) {
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*rtr = true;
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} else {
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*rtr = false;
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}
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/* Get filter match ID. */
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*fmi = ((CAN_RDTxR(canport, fifo_id) & CAN_RDTxR_FMI_MASK) >>
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CAN_RDTxR_FMI_SHIFT);
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|
|
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/* Get data length. */
|
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*length = CAN_RDTxR(canport, fifo_id) & CAN_RDTxR_DLC_MASK;
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/* accelerate reception by copying the CAN data from the controller
|
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* memory to the fast internal RAM
|
|
*/
|
|
|
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if (timestamp) {
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*timestamp = (CAN_RDTxR(canport, fifo_id) &
|
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CAN_RDTxR_TIME_MASK) >> CAN_RDTxR_TIME_SHIFT;
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}
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rdlxr.data32 = CAN_RDLxR(canport, fifo_id);
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rdhxr.data32 = CAN_RDHxR(canport, fifo_id);
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/* */
|
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/* Get data.
|
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* Byte wise copy is needed because we do not know the alignment
|
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* of the input buffer.
|
|
* Here copying 8 bytes unconditionally is faster than using loop
|
|
*
|
|
* It is OK to copy all 8 bytes because the upper layer must be
|
|
* prepared for data length bigger expected.
|
|
* In contrary the driver has no information about the intended size.
|
|
* This could be different if the max length would be handed over
|
|
* to the function, but it is not the case
|
|
*/
|
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data[0] = rdlxr.data8[0];
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data[1] = rdlxr.data8[1];
|
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data[2] = rdlxr.data8[2];
|
|
data[3] = rdlxr.data8[3];
|
|
data[4] = rdhxr.data8[0];
|
|
data[5] = rdhxr.data8[1];
|
|
data[6] = rdhxr.data8[2];
|
|
data[7] = rdhxr.data8[3];
|
|
|
|
/* Release the FIFO. */
|
|
if (release) {
|
|
can_fifo_release(canport, fifo);
|
|
}
|
|
}
|
|
|
|
bool can_available_mailbox(uint32_t canport)
|
|
{
|
|
return CAN_TSR(canport) & (CAN_TSR_TME0 | CAN_TSR_TME1 | CAN_TSR_TME2);
|
|
}
|
|
|