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413 lines
7.9 KiB
413 lines
7.9 KiB
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/stm32/f2/rcc.h>
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#include <libopencm3/stm32/f2/flash.h>
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/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */
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u32 rcc_ppre1_frequency = 16000000;
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u32 rcc_ppre2_frequency = 16000000;
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const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] =
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{
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{ /* 120MHz */
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.pllm = 8,
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.plln = 240,
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.pllp = 2,
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.pllq = 5,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.flash_config = FLASH_ICE | FLASH_DCE | FLASH_LATENCY_3WS,
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.apb1_frequency = 30000000,
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.apb2_frequency = 60000000,
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},
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};
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void rcc_osc_ready_int_clear(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CIR |= RCC_CIR_PLLRDYC;
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break;
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case HSE:
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RCC_CIR |= RCC_CIR_HSERDYC;
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break;
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case HSI:
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RCC_CIR |= RCC_CIR_HSIRDYC;
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break;
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case LSE:
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RCC_CIR |= RCC_CIR_LSERDYC;
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break;
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case LSI:
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RCC_CIR |= RCC_CIR_LSIRDYC;
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break;
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}
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}
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void rcc_osc_ready_int_enable(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CIR |= RCC_CIR_PLLRDYIE;
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break;
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case HSE:
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RCC_CIR |= RCC_CIR_HSERDYIE;
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break;
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case HSI:
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RCC_CIR |= RCC_CIR_HSIRDYIE;
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break;
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case LSE:
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RCC_CIR |= RCC_CIR_LSERDYIE;
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break;
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case LSI:
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RCC_CIR |= RCC_CIR_LSIRDYIE;
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break;
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}
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}
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void rcc_osc_ready_int_disable(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CIR &= ~RCC_CIR_PLLRDYIE;
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break;
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case HSE:
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RCC_CIR &= ~RCC_CIR_HSERDYIE;
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break;
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case HSI:
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RCC_CIR &= ~RCC_CIR_HSIRDYIE;
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break;
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case LSE:
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RCC_CIR &= ~RCC_CIR_LSERDYIE;
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break;
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case LSI:
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RCC_CIR &= ~RCC_CIR_LSIRDYIE;
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break;
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}
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}
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int rcc_osc_ready_int_flag(osc_t osc)
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{
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switch (osc) {
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case PLL:
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return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
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break;
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case HSE:
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return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
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break;
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case HSI:
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return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
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break;
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case LSE:
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return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
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break;
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case LSI:
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return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
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break;
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}
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/* Shouldn't be reached. */
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return -1;
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}
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void rcc_css_int_clear(void)
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{
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RCC_CIR |= RCC_CIR_CSSC;
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}
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int rcc_css_int_flag(void)
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{
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return ((RCC_CIR & RCC_CIR_CSSF) != 0);
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}
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void rcc_wait_for_osc_ready(osc_t osc)
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{
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switch (osc) {
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case PLL:
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while ((RCC_CR & RCC_CR_PLLRDY) == 0);
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break;
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case HSE:
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while ((RCC_CR & RCC_CR_HSERDY) == 0);
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break;
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case HSI:
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while ((RCC_CR & RCC_CR_HSIRDY) == 0);
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break;
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case LSE:
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while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0);
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break;
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case LSI:
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while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
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break;
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}
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}
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void rcc_wait_for_sysclk_status(osc_t osc)
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{
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switch (osc) {
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case PLL:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL);
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break;
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case HSE:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE);
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break;
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case HSI:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI);
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break;
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default:
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/* Shouldn't be reached. */
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break;
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}
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}
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void rcc_osc_on(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CR |= RCC_CR_PLLON;
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break;
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case HSE:
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RCC_CR |= RCC_CR_HSEON;
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break;
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case HSI:
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RCC_CR |= RCC_CR_HSION;
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break;
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case LSE:
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RCC_BDCR |= RCC_BDCR_LSEON;
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break;
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case LSI:
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RCC_CSR |= RCC_CSR_LSION;
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break;
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}
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}
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void rcc_osc_off(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CR &= ~RCC_CR_PLLON;
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break;
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case HSE:
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RCC_CR &= ~RCC_CR_HSEON;
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break;
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case HSI:
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RCC_CR &= ~RCC_CR_HSION;
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break;
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case LSE:
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RCC_BDCR &= ~RCC_BDCR_LSEON;
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break;
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case LSI:
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RCC_CSR &= ~RCC_CSR_LSION;
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break;
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}
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}
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void rcc_css_enable(void)
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{
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RCC_CR |= RCC_CR_CSSON;
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}
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void rcc_css_disable(void)
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{
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RCC_CR &= ~RCC_CR_CSSON;
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}
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void rcc_osc_bypass_enable(osc_t osc)
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{
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switch (osc) {
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case HSE:
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RCC_CR |= RCC_CR_HSEBYP;
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break;
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case LSE:
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RCC_BDCR |= RCC_BDCR_LSEBYP;
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break;
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case PLL:
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case HSI:
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case LSI:
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/* Do nothing, only HSE/LSE allowed here. */
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break;
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}
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}
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void rcc_osc_bypass_disable(osc_t osc)
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{
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switch (osc) {
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case HSE:
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RCC_CR &= ~RCC_CR_HSEBYP;
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break;
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case LSE:
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RCC_BDCR &= ~RCC_BDCR_LSEBYP;
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break;
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case PLL:
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case HSI:
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case LSI:
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/* Do nothing, only HSE/LSE allowed here. */
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break;
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}
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}
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void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en)
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{
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*reg |= en;
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}
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void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en)
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{
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*reg &= ~en;
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}
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void rcc_peripheral_reset(volatile u32 *reg, u32 reset)
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{
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*reg |= reset;
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}
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void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
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{
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*reg &= ~clear_reset;
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}
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void rcc_set_sysclk_source(u32 clk)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 1) | (1 << 0));
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RCC_CFGR = (reg32 | clk);
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}
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void rcc_set_pll_source(u32 pllsrc)
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{
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u32 reg32;
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reg32 = RCC_PLLCFGR;
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reg32 &= ~(1 << 22);
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RCC_PLLCFGR = (reg32 | (pllsrc << 22));
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}
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void rcc_set_ppre2(u32 ppre2)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 13) | (1 << 14) | (1 << 15));
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RCC_CFGR = (reg32 | (ppre2 << 13));
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}
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void rcc_set_ppre1(u32 ppre1)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 10) | (1 << 11) | (1 << 12));
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RCC_CFGR = (reg32 | (ppre1 << 10));
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}
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void rcc_set_hpre(u32 hpre)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
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RCC_CFGR = (reg32 | (hpre << 4));
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}
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void rcc_set_rtcpre(u32 rtcpre)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20));
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RCC_CFGR = (reg32 | (rtcpre << 16));
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}
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void rcc_set_main_pll_hsi(u32 pllm, u32 plln, u32 pllp, u32 pllq)
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{
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RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
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(plln << RCC_PLLCFGR_PLLN_SHIFT) |
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(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
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(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
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}
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void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq)
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{
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RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
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(plln << RCC_PLLCFGR_PLLN_SHIFT) |
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(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
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RCC_PLLCFGR_PLLSRC |
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(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
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}
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u32 rcc_system_clock_source(void)
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{
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/* Return the clock source which is used as system clock. */
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return ((RCC_CFGR & 0x000c) >> 2);
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}
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void rcc_clock_setup_hse_3v3(const clock_scale_t *clock)
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{
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/* Enable internal high-speed oscillator. */
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rcc_osc_on(HSI);
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rcc_wait_for_osc_ready(HSI);
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/* Select HSI as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
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/* Enable external high-speed oscillator 8MHz. */
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rcc_osc_on(HSE);
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rcc_wait_for_osc_ready(HSE);
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/*
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* Set prescalers for AHB, ADC, ABP1, ABP2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(clock->hpre);
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rcc_set_ppre1(clock->ppre1);
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rcc_set_ppre2(clock->ppre2);
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rcc_set_main_pll_hse(clock->pllm, clock->plln,
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clock->pllp, clock->pllq);
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/* Enable PLL oscillator and wait for it to stabilize. */
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rcc_osc_on(PLL);
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rcc_wait_for_osc_ready(PLL);
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/* Configure flash settings. */
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flash_set_ws(clock->flash_config);
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/* Select PLL as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
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/* Wait for PLL clock to be selected. */
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rcc_wait_for_sysclk_status(PLL);
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/* Set the peripheral clock frequencies used. */
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rcc_ppre1_frequency = clock->apb1_frequency;
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rcc_ppre2_frequency = clock->apb2_frequency;
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}
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void rcc_backupdomain_reset(void)
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{
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/* Set the backup domain software reset. */
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RCC_BDCR |= RCC_BDCR_BDRST;
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/* Clear the backup domain software reset. */
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RCC_BDCR &= ~RCC_BDCR_BDRST;
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}
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