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185 lines
5.5 KiB
185 lines
5.5 KiB
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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* Copyright (C) 2012 Fergus Noble <fergusnoble@gmail.com>
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* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/** @defgroup CM3_nvic_file NVIC
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@ingroup CM3_files
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@brief <b>libopencm3 Cortex Nested Vectored Interrupt Controller</b>
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
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@author @htmlonly © @endhtmlonly 2012 Fergus Noble <fergusnoble@gmail.com>
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@date 18 August 2012
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Cortex processors provide 14 cortex-defined interrupts (NMI, usage faults,
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systicks etc.) and varying numbers of implementation defined interrupts
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(typically peripherial interrupts and DMA).
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@see Cortex-M3 Devices Generic User Guide
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@see STM32F10xxx Cortex-M3 programming manual
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LGPL License Terms @ref lgpl_license
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*/
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/**@{*/
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#include <libopencm3/cm3/nvic.h>
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#include <libopencm3/cm3/scs.h>
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/*---------------------------------------------------------------------------*/
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/** @brief NVIC Enable Interrupt
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Enables a user interrupt.
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@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
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*/
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void nvic_enable_irq(uint8_t irqn)
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{
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NVIC_ISER(irqn / 32) = (1 << (irqn % 32));
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}
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/*---------------------------------------------------------------------------*/
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/** @brief NVIC Disable Interrupt
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Disables a user interrupt.
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@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
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*/
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void nvic_disable_irq(uint8_t irqn)
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{
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NVIC_ICER(irqn / 32) = (1 << (irqn % 32));
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}
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/*---------------------------------------------------------------------------*/
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/** @brief NVIC Return Pending Interrupt
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True if the interrupt has occurred and is waiting for service.
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@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
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@return Boolean. Interrupt pending.
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*/
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uint8_t nvic_get_pending_irq(uint8_t irqn)
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{
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return NVIC_ISPR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief NVIC Set Pending Interrupt
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Force a user interrupt to a pending state. This has no effect if the interrupt
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is already pending.
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@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
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*/
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void nvic_set_pending_irq(uint8_t irqn)
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{
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NVIC_ISPR(irqn / 32) = (1 << (irqn % 32));
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}
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/*---------------------------------------------------------------------------*/
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/** @brief NVIC Clear Pending Interrupt
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Force remove a user interrupt from a pending state. This has no effect if the
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interrupt is actively being serviced.
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@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
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*/
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void nvic_clear_pending_irq(uint8_t irqn)
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{
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NVIC_ICPR(irqn / 32) = (1 << (irqn % 32));
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}
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/*---------------------------------------------------------------------------*/
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/** @brief NVIC Return Active Interrupt
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Interrupt has occurred and is currently being serviced.
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@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
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@return Boolean. Interrupt active.
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*/
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uint8_t nvic_get_active_irq(uint8_t irqn)
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{
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return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief NVIC Return Enabled Interrupt
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@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
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@return Boolean. Interrupt enabled.
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*/
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uint8_t nvic_get_irq_enabled(uint8_t irqn)
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{
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return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief NVIC Set Interrupt Priority
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There are 16 priority levels only, given by the upper four bits of the priority
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byte, as required by ARM standards. The priority levels are interpreted
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according to the pre-emptive priority grouping set in the SCB Application
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Interrupt and Reset Control Register (SCB_AIRCR), as done in @ref
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scb_set_priority_grouping.
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@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
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@param[in] priority Unsigned int8. Interrupt priority (0 ... 255 in steps of 16)
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*/
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void nvic_set_priority(uint8_t irqn, uint8_t priority)
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{
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/* code from lpc43xx/nvic.c -- this is quite a hack and alludes to the
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* negative interrupt numbers assigned to the system interrupts. better
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* handling would mean signed integers. */
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if (irqn >= NVIC_IRQ_COUNT) {
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/* Cortex-M system interrupts */
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SCS_SHPR((irqn & 0xF) - 4) = priority;
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} else {
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/* Device specific interrupts */
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NVIC_IPR(irqn) = priority;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief NVIC Software Trigger Interrupt
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Generate an interrupt from software. This has no effect for unprivileged access
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unless the privilege level has been elevated through the System Control
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Registers.
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@param[in] irqn Unsigned int16. Interrupt number (0 ... 239)
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*/
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void nvic_generate_software_interrupt(uint16_t irqn)
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{
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if (irqn <= 239) {
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NVIC_STIR |= irqn;
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}
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}
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/**@}*/
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