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/***************************************************************************//**
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* @file ad9361_api.h |
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* @brief Header file of AD9361 API Driver. |
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* @author DBogdan (dragos.bogdan@analog.com) |
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******************************************************************************** |
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* Copyright 2013(c) Analog Devices, Inc. |
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* |
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* All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* - Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* - Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* - Neither the name of Analog Devices, Inc. nor the names of its |
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* contributors may be used to endorse or promote products derived |
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* from this software without specific prior written permission. |
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* - The use of this software may or may not infringe the patent rights |
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* of one or more patent holders. This license does not release you |
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* from the requirement that you obtain separate licenses from these |
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* patent holders to use this software. |
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* - Use of the software either in source or binary form, must be run |
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* on or directly connected to an Analog Devices Inc. component. |
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* |
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* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR |
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, |
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR |
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*******************************************************************************/ |
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#ifndef AD9361_API_H_ |
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#define AD9361_API_H_ |
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/******************************************************************************/ |
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/***************************** Include Files **********************************/ |
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/******************************************************************************/ |
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#include "util.h" |
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/******************************************************************************/ |
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/*************************** Types Declarations *******************************/ |
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/******************************************************************************/ |
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typedef struct |
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{ |
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/* Device selection */ |
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enum dev_id dev_sel; |
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/* Identification number */ |
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uint8_t id_no; |
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/* Reference Clock */ |
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uint32_t reference_clk_rate; |
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/* Base Configuration */ |
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uint8_t two_rx_two_tx_mode_enable; /* adi,2rx-2tx-mode-enable */ |
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uint8_t one_rx_one_tx_mode_use_rx_num; /* adi,1rx-1tx-mode-use-rx-num */ |
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uint8_t one_rx_one_tx_mode_use_tx_num; /* adi,1rx-1tx-mode-use-tx-num */ |
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uint8_t frequency_division_duplex_mode_enable; /* adi,frequency-division-duplex-mode-enable */ |
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uint8_t frequency_division_duplex_independent_mode_enable; /* adi,frequency-division-duplex-independent-mode-enable */ |
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uint8_t tdd_use_dual_synth_mode_enable; /* adi,tdd-use-dual-synth-mode-enable */ |
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uint8_t tdd_skip_vco_cal_enable; /* adi,tdd-skip-vco-cal-enable */ |
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uint32_t tx_fastlock_delay_ns; /* adi,tx-fastlock-delay-ns */ |
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uint32_t rx_fastlock_delay_ns; /* adi,rx-fastlock-delay-ns */ |
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uint8_t rx_fastlock_pincontrol_enable; /* adi,rx-fastlock-pincontrol-enable */ |
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uint8_t tx_fastlock_pincontrol_enable; /* adi,tx-fastlock-pincontrol-enable */ |
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uint8_t external_rx_lo_enable; /* adi,external-rx-lo-enable */ |
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uint8_t external_tx_lo_enable; /* adi,external-tx-lo-enable */ |
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uint8_t dc_offset_tracking_update_event_mask; /* adi,dc-offset-tracking-update-event-mask */ |
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uint8_t dc_offset_attenuation_high_range; /* adi,dc-offset-attenuation-high-range */ |
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uint8_t dc_offset_attenuation_low_range; /* adi,dc-offset-attenuation-low-range */ |
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uint8_t dc_offset_count_high_range; /* adi,dc-offset-count-high-range */ |
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uint8_t dc_offset_count_low_range; /* adi,dc-offset-count-low-range */ |
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uint8_t split_gain_table_mode_enable; /* adi,split-gain-table-mode-enable */ |
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uint32_t trx_synthesizer_target_fref_overwrite_hz; /* adi,trx-synthesizer-target-fref-overwrite-hz */ |
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uint8_t qec_tracking_slow_mode_enable; /* adi,qec-tracking-slow-mode-enable */ |
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/* ENSM Control */ |
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uint8_t ensm_enable_pin_pulse_mode_enable; /* adi,ensm-enable-pin-pulse-mode-enable */ |
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uint8_t ensm_enable_txnrx_control_enable; /* adi,ensm-enable-txnrx-control-enable */ |
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/* LO Control */ |
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uint64_t rx_synthesizer_frequency_hz; /* adi,rx-synthesizer-frequency-hz */ |
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uint64_t tx_synthesizer_frequency_hz; /* adi,tx-synthesizer-frequency-hz */ |
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/* Rate & BW Control */ |
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uint32_t rx_path_clock_frequencies[6]; /* adi,rx-path-clock-frequencies */ |
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uint32_t tx_path_clock_frequencies[6]; /* adi,tx-path-clock-frequencies */ |
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uint32_t rf_rx_bandwidth_hz; /* adi,rf-rx-bandwidth-hz */ |
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uint32_t rf_tx_bandwidth_hz; /* adi,rf-tx-bandwidth-hz */ |
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/* RF Port Control */ |
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uint32_t rx_rf_port_input_select; /* adi,rx-rf-port-input-select */ |
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uint32_t tx_rf_port_input_select; /* adi,tx-rf-port-input-select */ |
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/* TX Attenuation Control */ |
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int32_t tx_attenuation_mdB; /* adi,tx-attenuation-mdB */ |
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uint8_t update_tx_gain_in_alert_enable; /* adi,update-tx-gain-in-alert-enable */ |
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/* Reference Clock Control */ |
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uint8_t xo_disable_use_ext_refclk_enable; /* adi,xo-disable-use-ext-refclk-enable */ |
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uint32_t dcxo_coarse_and_fine_tune[2]; /* adi,dcxo-coarse-and-fine-tune */ |
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uint32_t clk_output_mode_select; /* adi,clk-output-mode-select */ |
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/* Gain Control */ |
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uint8_t gc_rx1_mode; /* adi,gc-rx1-mode */ |
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uint8_t gc_rx2_mode; /* adi,gc-rx2-mode */ |
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uint8_t gc_adc_large_overload_thresh; /* adi,gc-adc-large-overload-thresh */ |
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uint8_t gc_adc_ovr_sample_size; /* adi,gc-adc-ovr-sample-size */ |
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uint8_t gc_adc_small_overload_thresh; /* adi,gc-adc-small-overload-thresh */ |
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uint16_t gc_dec_pow_measurement_duration; /* adi,gc-dec-pow-measurement-duration */ |
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uint8_t gc_dig_gain_enable; /* adi,gc-dig-gain-enable */ |
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uint16_t gc_lmt_overload_high_thresh; /* adi,gc-lmt-overload-high-thresh */ |
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uint16_t gc_lmt_overload_low_thresh; /* adi,gc-lmt-overload-low-thresh */ |
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uint8_t gc_low_power_thresh; /* adi,gc-low-power-thresh */ |
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uint8_t gc_max_dig_gain; /* adi,gc-max-dig-gain */ |
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/* Gain MGC Control */ |
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uint8_t mgc_dec_gain_step; /* adi,mgc-dec-gain-step */ |
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uint8_t mgc_inc_gain_step; /* adi,mgc-inc-gain-step */ |
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uint8_t mgc_rx1_ctrl_inp_enable; /* adi,mgc-rx1-ctrl-inp-enable */ |
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uint8_t mgc_rx2_ctrl_inp_enable; /* adi,mgc-rx2-ctrl-inp-enable */ |
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uint8_t mgc_split_table_ctrl_inp_gain_mode; /* adi,mgc-split-table-ctrl-inp-gain-mode */ |
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/* Gain AGC Control */ |
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uint8_t agc_adc_large_overload_exceed_counter; /* adi,agc-adc-large-overload-exceed-counter */ |
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uint8_t agc_adc_large_overload_inc_steps; /* adi,agc-adc-large-overload-inc-steps */ |
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uint8_t agc_adc_lmt_small_overload_prevent_gain_inc_enable; /* adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable */ |
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uint8_t agc_adc_small_overload_exceed_counter; /* adi,agc-adc-small-overload-exceed-counter */ |
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uint8_t agc_dig_gain_step_size; /* adi,agc-dig-gain-step-size */ |
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uint8_t agc_dig_saturation_exceed_counter; /* adi,agc-dig-saturation-exceed-counter */ |
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uint32_t agc_gain_update_interval_us; /* adi,agc-gain-update-interval-us */ |
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uint8_t agc_immed_gain_change_if_large_adc_overload_enable; /* adi,agc-immed-gain-change-if-large-adc-overload-enable */ |
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uint8_t agc_immed_gain_change_if_large_lmt_overload_enable; /* adi,agc-immed-gain-change-if-large-lmt-overload-enable */ |
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uint8_t agc_inner_thresh_high; /* adi,agc-inner-thresh-high */ |
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uint8_t agc_inner_thresh_high_dec_steps; /* adi,agc-inner-thresh-high-dec-steps */ |
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uint8_t agc_inner_thresh_low; /* adi,agc-inner-thresh-low */ |
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uint8_t agc_inner_thresh_low_inc_steps; /* adi,agc-inner-thresh-low-inc-steps */ |
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uint8_t agc_lmt_overload_large_exceed_counter; /* adi,agc-lmt-overload-large-exceed-counter */ |
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uint8_t agc_lmt_overload_large_inc_steps; /* adi,agc-lmt-overload-large-inc-steps */ |
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uint8_t agc_lmt_overload_small_exceed_counter; /* adi,agc-lmt-overload-small-exceed-counter */ |
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uint8_t agc_outer_thresh_high; /* adi,agc-outer-thresh-high */ |
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uint8_t agc_outer_thresh_high_dec_steps; /* adi,agc-outer-thresh-high-dec-steps */ |
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uint8_t agc_outer_thresh_low; /* adi,agc-outer-thresh-low */ |
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uint8_t agc_outer_thresh_low_inc_steps; /* adi,agc-outer-thresh-low-inc-steps */ |
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uint32_t agc_attack_delay_extra_margin_us; /* adi,agc-attack-delay-extra-margin-us */ |
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uint8_t agc_sync_for_gain_counter_enable; /* adi,agc-sync-for-gain-counter-enable */ |
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/* Fast AGC */ |
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uint32_t fagc_dec_pow_measuremnt_duration; /* adi,fagc-dec-pow-measurement-duration */ |
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uint32_t fagc_state_wait_time_ns; /* adi,fagc-state-wait-time-ns */ |
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/* Fast AGC - Low Power */ |
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uint8_t fagc_allow_agc_gain_increase; /* adi,fagc-allow-agc-gain-increase-enable */ |
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uint32_t fagc_lp_thresh_increment_time; /* adi,fagc-lp-thresh-increment-time */ |
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uint32_t fagc_lp_thresh_increment_steps; /* adi,fagc-lp-thresh-increment-steps */ |
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/* Fast AGC - Lock Level */ |
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uint32_t fagc_lock_level; /* adi,fagc-lock-level */ |
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uint8_t fagc_lock_level_lmt_gain_increase_en; /* adi,fagc-lock-level-lmt-gain-increase-enable */ |
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uint32_t fagc_lock_level_gain_increase_upper_limit; /* adi,fagc-lock-level-gain-increase-upper-limit */ |
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/* Fast AGC - Peak Detectors and Final Settling */ |
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uint32_t fagc_lpf_final_settling_steps; /* adi,fagc-lpf-final-settling-steps */ |
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uint32_t fagc_lmt_final_settling_steps; /* adi,fagc-lmt-final-settling-steps */ |
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uint32_t fagc_final_overrange_count; /* adi,fagc-final-overrange-count */ |
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/* Fast AGC - Final Power Test */ |
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uint8_t fagc_gain_increase_after_gain_lock_en; /* adi,fagc-gain-increase-after-gain-lock-enable */ |
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/* Fast AGC - Unlocking the Gain */ |
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uint32_t fagc_gain_index_type_after_exit_rx_mode; /* adi,fagc-gain-index-type-after-exit-rx-mode */ |
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uint8_t fagc_use_last_lock_level_for_set_gain_en; /* adi,fagc-use-last-lock-level-for-set-gain-enable */ |
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uint8_t fagc_rst_gla_stronger_sig_thresh_exceeded_en; /* adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable */ |
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uint32_t fagc_optimized_gain_offset; /* adi,fagc-optimized-gain-offset */ |
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uint32_t fagc_rst_gla_stronger_sig_thresh_above_ll; /* adi,fagc-rst-gla-stronger-sig-thresh-above-ll */ |
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uint8_t fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en; /* adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable */ |
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uint8_t fagc_rst_gla_engergy_lost_goto_optim_gain_en; /* adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable */ |
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uint32_t fagc_rst_gla_engergy_lost_sig_thresh_below_ll; /* adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll */ |
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uint32_t fagc_energy_lost_stronger_sig_gain_lock_exit_cnt; /* adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt */ |
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uint8_t fagc_rst_gla_large_adc_overload_en; /* adi,fagc-rst-gla-large-adc-overload-enable */ |
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uint8_t fagc_rst_gla_large_lmt_overload_en; /* adi,fagc-rst-gla-large-lmt-overload-enable */ |
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uint8_t fagc_rst_gla_en_agc_pulled_high_en; /* adi,fagc-rst-gla-en-agc-pulled-high-enable */ |
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uint32_t fagc_rst_gla_if_en_agc_pulled_high_mode; /* adi,fagc-rst-gla-if-en-agc-pulled-high-mode */ |
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uint32_t fagc_power_measurement_duration_in_state5; /* adi,fagc-power-measurement-duration-in-state5 */ |
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/* RSSI Control */ |
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uint32_t rssi_delay; /* adi,rssi-delay */ |
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uint32_t rssi_duration; /* adi,rssi-duration */ |
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uint8_t rssi_restart_mode; /* adi,rssi-restart-mode */ |
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uint8_t rssi_unit_is_rx_samples_enable; /* adi,rssi-unit-is-rx-samples-enable */ |
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uint32_t rssi_wait; /* adi,rssi-wait */ |
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/* Aux ADC Control */ |
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uint32_t aux_adc_decimation; /* adi,aux-adc-decimation */ |
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uint32_t aux_adc_rate; /* adi,aux-adc-rate */ |
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/* AuxDAC Control */ |
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uint8_t aux_dac_manual_mode_enable; /* adi,aux-dac-manual-mode-enable */ |
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uint32_t aux_dac1_default_value_mV; /* adi,aux-dac1-default-value-mV */ |
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uint8_t aux_dac1_active_in_rx_enable; /* adi,aux-dac1-active-in-rx-enable */ |
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uint8_t aux_dac1_active_in_tx_enable; /* adi,aux-dac1-active-in-tx-enable */ |
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uint8_t aux_dac1_active_in_alert_enable; /* adi,aux-dac1-active-in-alert-enable */ |
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uint32_t aux_dac1_rx_delay_us; /* adi,aux-dac1-rx-delay-us */ |
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uint32_t aux_dac1_tx_delay_us; /* adi,aux-dac1-tx-delay-us */ |
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uint32_t aux_dac2_default_value_mV; /* adi,aux-dac2-default-value-mV */ |
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uint8_t aux_dac2_active_in_rx_enable; /* adi,aux-dac2-active-in-rx-enable */ |
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uint8_t aux_dac2_active_in_tx_enable; /* adi,aux-dac2-active-in-tx-enable */ |
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uint8_t aux_dac2_active_in_alert_enable; /* adi,aux-dac2-active-in-alert-enable */ |
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uint32_t aux_dac2_rx_delay_us; /* adi,aux-dac2-rx-delay-us */ |
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uint32_t aux_dac2_tx_delay_us; /* adi,aux-dac2-tx-delay-us */ |
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/* Temperature Sensor Control */ |
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uint32_t temp_sense_decimation; /* adi,temp-sense-decimation */ |
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uint16_t temp_sense_measurement_interval_ms; /* adi,temp-sense-measurement-interval-ms */ |
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int8_t temp_sense_offset_signed; /* adi,temp-sense-offset-signed */ |
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uint8_t temp_sense_periodic_measurement_enable; /* adi,temp-sense-periodic-measurement-enable */ |
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/* Control Out Setup */ |
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uint8_t ctrl_outs_enable_mask; /* adi,ctrl-outs-enable-mask */ |
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uint8_t ctrl_outs_index; /* adi,ctrl-outs-index */ |
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/* External LNA Control */ |
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uint32_t elna_settling_delay_ns; /* adi,elna-settling-delay-ns */ |
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uint32_t elna_gain_mdB; /* adi,elna-gain-mdB */ |
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uint32_t elna_bypass_loss_mdB; /* adi,elna-bypass-loss-mdB */ |
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uint8_t elna_rx1_gpo0_control_enable; /* adi,elna-rx1-gpo0-control-enable */ |
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uint8_t elna_rx2_gpo1_control_enable; /* adi,elna-rx2-gpo1-control-enable */ |
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uint8_t elna_gaintable_all_index_enable; /* adi,elna-gaintable-all-index-enable */ |
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/* Digital Interface Control */ |
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uint8_t digital_interface_tune_skip_mode; /* adi,digital-interface-tune-skip-mode */ |
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uint8_t digital_interface_tune_fir_disable; /* adi,digital-interface-tune-fir-disable */ |
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uint8_t pp_tx_swap_enable; /* adi,pp-tx-swap-enable */ |
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uint8_t pp_rx_swap_enable; /* adi,pp-rx-swap-enable */ |
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uint8_t tx_channel_swap_enable; /* adi,tx-channel-swap-enable */ |
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uint8_t rx_channel_swap_enable; /* adi,rx-channel-swap-enable */ |
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uint8_t rx_frame_pulse_mode_enable; /* adi,rx-frame-pulse-mode-enable */ |
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uint8_t two_t_two_r_timing_enable; /* adi,2t2r-timing-enable */ |
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uint8_t invert_data_bus_enable; /* adi,invert-data-bus-enable */ |
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uint8_t invert_data_clk_enable; /* adi,invert-data-clk-enable */ |
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uint8_t fdd_alt_word_order_enable; /* adi,fdd-alt-word-order-enable */ |
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uint8_t invert_rx_frame_enable; /* adi,invert-rx-frame-enable */ |
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uint8_t fdd_rx_rate_2tx_enable; /* adi,fdd-rx-rate-2tx-enable */ |
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uint8_t swap_ports_enable; /* adi,swap-ports-enable */ |
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uint8_t single_data_rate_enable; /* adi,single-data-rate-enable */ |
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uint8_t lvds_mode_enable; /* adi,lvds-mode-enable */ |
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uint8_t half_duplex_mode_enable; /* adi,half-duplex-mode-enable */ |
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uint8_t single_port_mode_enable; /* adi,single-port-mode-enable */ |
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uint8_t full_port_enable; /* adi,full-port-enable */ |
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uint8_t full_duplex_swap_bits_enable; /* adi,full-duplex-swap-bits-enable */ |
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uint32_t delay_rx_data; /* adi,delay-rx-data */ |
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uint32_t rx_data_clock_delay; /* adi,rx-data-clock-delay */ |
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uint32_t rx_data_delay; /* adi,rx-data-delay */ |
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uint32_t tx_fb_clock_delay; /* adi,tx-fb-clock-delay */ |
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uint32_t tx_data_delay; /* adi,tx-data-delay */ |
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uint32_t lvds_bias_mV; /* adi,lvds-bias-mV */ |
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uint8_t lvds_rx_onchip_termination_enable; /* adi,lvds-rx-onchip-termination-enable */ |
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uint8_t rx1rx2_phase_inversion_en; /* adi,rx1-rx2-phase-inversion-enable */ |
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uint8_t lvds_invert1_control; /* adi,lvds-invert1-control */ |
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uint8_t lvds_invert2_control; /* adi,lvds-invert2-control */ |
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/* GPO Control */ |
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uint8_t gpo0_inactive_state_high_enable; /* adi,gpo0-inactive-state-high-enable */ |
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uint8_t gpo1_inactive_state_high_enable; /* adi,gpo1-inactive-state-high-enable */ |
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uint8_t gpo2_inactive_state_high_enable; /* adi,gpo2-inactive-state-high-enable */ |
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uint8_t gpo3_inactive_state_high_enable; /* adi,gpo3-inactive-state-high-enable */ |
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uint8_t gpo0_slave_rx_enable; /* adi,gpo0-slave-rx-enable */ |
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uint8_t gpo0_slave_tx_enable; /* adi,gpo0-slave-tx-enable */ |
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uint8_t gpo1_slave_rx_enable; /* adi,gpo1-slave-rx-enable */ |
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uint8_t gpo1_slave_tx_enable; /* adi,gpo1-slave-tx-enable */ |
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uint8_t gpo2_slave_rx_enable; /* adi,gpo2-slave-rx-enable */ |
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uint8_t gpo2_slave_tx_enable; /* adi,gpo2-slave-tx-enable */ |
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uint8_t gpo3_slave_rx_enable; /* adi,gpo3-slave-rx-enable */ |
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uint8_t gpo3_slave_tx_enable; /* adi,gpo3-slave-tx-enable */ |
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uint8_t gpo0_rx_delay_us; /* adi,gpo0-rx-delay-us */ |
|||
uint8_t gpo0_tx_delay_us; /* adi,gpo0-tx-delay-us */ |
|||
uint8_t gpo1_rx_delay_us; /* adi,gpo1-rx-delay-us */ |
|||
uint8_t gpo1_tx_delay_us; /* adi,gpo1-tx-delay-us */ |
|||
uint8_t gpo2_rx_delay_us; /* adi,gpo2-rx-delay-us */ |
|||
uint8_t gpo2_tx_delay_us; /* adi,gpo2-tx-delay-us */ |
|||
uint8_t gpo3_rx_delay_us; /* adi,gpo3-rx-delay-us */ |
|||
uint8_t gpo3_tx_delay_us; /* adi,gpo3-tx-delay-us */ |
|||
/* Tx Monitor Control */ |
|||
uint32_t low_high_gain_threshold_mdB; /* adi,txmon-low-high-thresh */ |
|||
uint32_t low_gain_dB; /* adi,txmon-low-gain */ |
|||
uint32_t high_gain_dB; /* adi,txmon-high-gain */ |
|||
uint8_t tx_mon_track_en; /* adi,txmon-dc-tracking-enable */ |
|||
uint8_t one_shot_mode_en; /* adi,txmon-one-shot-mode-enable */ |
|||
uint32_t tx_mon_delay; /* adi,txmon-delay */ |
|||
uint32_t tx_mon_duration; /* adi,txmon-duration */ |
|||
uint32_t tx1_mon_front_end_gain; /* adi,txmon-1-front-end-gain */ |
|||
uint32_t tx2_mon_front_end_gain; /* adi,txmon-2-front-end-gain */ |
|||
uint32_t tx1_mon_lo_cm; /* adi,txmon-1-lo-cm */ |
|||
uint32_t tx2_mon_lo_cm; /* adi,txmon-2-lo-cm */ |
|||
/* GPIO definitions */ |
|||
int32_t gpio_resetb; /* reset-gpios */ |
|||
/* MCS Sync */ |
|||
int32_t gpio_sync; /* sync-gpios */ |
|||
int32_t gpio_cal_sw1; /* cal-sw1-gpios */ |
|||
int32_t gpio_cal_sw2; /* cal-sw2-gpios */ |
|||
/* External LO clocks */ |
|||
uint32_t (*ad9361_rfpll_ext_recalc_rate)(struct refclk_scale *clk_priv); |
|||
int32_t (*ad9361_rfpll_ext_round_rate)(struct refclk_scale *clk_priv, uint32_t rate); |
|||
int32_t (*ad9361_rfpll_ext_set_rate)(struct refclk_scale *clk_priv, uint32_t rate); |
|||
}AD9361_InitParam; |
|||
|
|||
typedef struct |
|||
{ |
|||
uint32_t rx; /* 1, 2, 3(both) */ |
|||
int32_t rx_gain; /* -12, -6, 0, 6 */ |
|||
uint32_t rx_dec; /* 1, 2, 4 */ |
|||
int16_t rx_coef[128]; |
|||
uint8_t rx_coef_size; |
|||
uint32_t rx_path_clks[6]; |
|||
uint32_t rx_bandwidth; |
|||
}AD9361_RXFIRConfig; |
|||
|
|||
typedef struct |
|||
{ |
|||
uint32_t tx; /* 1, 2, 3(both) */ |
|||
int32_t tx_gain; /* -6, 0 */ |
|||
uint32_t tx_int; /* 1, 2, 4 */ |
|||
int16_t tx_coef[128]; |
|||
uint8_t tx_coef_size; |
|||
uint32_t tx_path_clks[6]; |
|||
uint32_t tx_bandwidth; |
|||
}AD9361_TXFIRConfig; |
|||
|
|||
enum ad9361_ensm_mode { |
|||
ENSM_MODE_TX, |
|||
ENSM_MODE_RX, |
|||
ENSM_MODE_ALERT, |
|||
ENSM_MODE_FDD, |
|||
ENSM_MODE_WAIT, |
|||
ENSM_MODE_SLEEP, |
|||
ENSM_MODE_PINCTRL, |
|||
ENSM_MODE_PINCTRL_FDD_INDEP, |
|||
}; |
|||
|
|||
#define ENABLE 1 |
|||
#define DISABLE 0 |
|||
|
|||
#define RX1 0 |
|||
#define RX2 1 |
|||
|
|||
#define TX1 0 |
|||
#define TX2 1 |
|||
|
|||
#define A_BALANCED 0 |
|||
#define B_BALANCED 1 |
|||
#define C_BALANCED 2 |
|||
#define A_N 3 |
|||
#define A_P 4 |
|||
#define B_N 5 |
|||
#define B_P 6 |
|||
#define C_N 7 |
|||
#define C_P 8 |
|||
#define TX_MON1 9 |
|||
#define TX_MON2 10 |
|||
#define TX_MON1_2 11 |
|||
|
|||
#define TXA 0 |
|||
#define TXB 1 |
|||
|
|||
#define MODE_1x1 1 |
|||
#define MODE_2x2 2 |
|||
|
|||
#define HIGHEST_OSR 0 |
|||
#define NOMINAL_OSR 1 |
|||
|
|||
#define INT_LO 0 |
|||
#define EXT_LO 1 |
|||
|
|||
/******************************************************************************/ |
|||
/************************ Functions Declarations ******************************/ |
|||
/******************************************************************************/ |
|||
/* Initialize the AD9361 part. */ |
|||
int32_t ad9361_init (struct ad9361_rf_phy **ad9361_phy, AD9361_InitParam *init_param); |
|||
/* Set the Enable State Machine (ENSM) mode. */ |
|||
int32_t ad9361_set_en_state_machine_mode (struct ad9361_rf_phy *phy, uint32_t mode); |
|||
/* Get the Enable State Machine (ENSM) mode. */ |
|||
int32_t ad9361_get_en_state_machine_mode (struct ad9361_rf_phy *phy, uint32_t *mode); |
|||
/* Set the receive RF gain for the selected channel. */ |
|||
int32_t ad9361_set_rx_rf_gain (struct ad9361_rf_phy *phy, uint8_t ch, int32_t gain_db); |
|||
/* Get current receive RF gain for the selected channel. */ |
|||
int32_t ad9361_get_rx_rf_gain (struct ad9361_rf_phy *phy, uint8_t ch, int32_t *gain_db); |
|||
/* Set the RX RF bandwidth. */ |
|||
int32_t ad9361_set_rx_rf_bandwidth (struct ad9361_rf_phy *phy, uint32_t bandwidth_hz); |
|||
/* Get the RX RF bandwidth. */ |
|||
int32_t ad9361_get_rx_rf_bandwidth (struct ad9361_rf_phy *phy, uint32_t *bandwidth_hz); |
|||
/* Set the RX sampling frequency. */ |
|||
int32_t ad9361_set_rx_sampling_freq (struct ad9361_rf_phy *phy, uint32_t sampling_freq_hz); |
|||
/* Get current RX sampling frequency. */ |
|||
int32_t ad9361_get_rx_sampling_freq (struct ad9361_rf_phy *phy, uint32_t *sampling_freq_hz); |
|||
/* Set the RX LO frequency. */ |
|||
int32_t ad9361_set_rx_lo_freq (struct ad9361_rf_phy *phy, uint64_t lo_freq_hz); |
|||
/* Get current RX LO frequency. */ |
|||
int32_t ad9361_get_rx_lo_freq (struct ad9361_rf_phy *phy, uint64_t *lo_freq_hz); |
|||
/* Switch between internal and external LO. */ |
|||
int32_t ad9361_set_rx_lo_int_ext(struct ad9361_rf_phy *phy, uint8_t int_ext); |
|||
/* Get the RSSI for the selected channel. */ |
|||
int32_t ad9361_get_rx_rssi (struct ad9361_rf_phy *phy, uint8_t ch, struct rf_rssi *rssi); |
|||
/* Set the gain control mode for the selected channel. */ |
|||
int32_t ad9361_set_rx_gain_control_mode (struct ad9361_rf_phy *phy, uint8_t ch, uint8_t gc_mode); |
|||
/* Get the gain control mode for the selected channel. */ |
|||
int32_t ad9361_get_rx_gain_control_mode (struct ad9361_rf_phy *phy, uint8_t ch, uint8_t *gc_mode); |
|||
/* Set the RX FIR filter configuration. */ |
|||
int32_t ad9361_set_rx_fir_config (struct ad9361_rf_phy *phy, AD9361_RXFIRConfig fir_cfg); |
|||
/* Get the RX FIR filter configuration. */ |
|||
int32_t ad9361_get_rx_fir_config(struct ad9361_rf_phy *phy, uint8_t rx_ch, AD9361_RXFIRConfig *fir_cfg); |
|||
/* Enable/disable the RX FIR filter. */ |
|||
int32_t ad9361_set_rx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t en_dis); |
|||
/* Get the status of the RX FIR filter. */ |
|||
int32_t ad9361_get_rx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t *en_dis); |
|||
/* Enable/disable the RX RFDC Tracking. */ |
|||
int32_t ad9361_set_rx_rfdc_track_en_dis (struct ad9361_rf_phy *phy, uint8_t en_dis); |
|||
/* Get the status of the RX RFDC Tracking. */ |
|||
int32_t ad9361_get_rx_rfdc_track_en_dis (struct ad9361_rf_phy *phy, uint8_t *en_dis); |
|||
/* Enable/disable the RX BasebandDC Tracking. */ |
|||
int32_t ad9361_set_rx_bbdc_track_en_dis (struct ad9361_rf_phy *phy, uint8_t en_dis); |
|||
/* Get the status of the RX BasebandDC Tracking. */ |
|||
int32_t ad9361_get_rx_bbdc_track_en_dis (struct ad9361_rf_phy *phy, uint8_t *en_dis); |
|||
/* Enable/disable the RX Quadrature Tracking. */ |
|||
int32_t ad9361_set_rx_quad_track_en_dis (struct ad9361_rf_phy *phy, uint8_t en_dis); |
|||
/* Get the status of the RX Quadrature Tracking. */ |
|||
int32_t ad9361_get_rx_quad_track_en_dis (struct ad9361_rf_phy *phy, uint8_t *en_dis); |
|||
/* Set the RX RF input port. */ |
|||
int32_t ad9361_set_rx_rf_port_input (struct ad9361_rf_phy *phy, uint32_t mode); |
|||
/* Get the selected RX RF input port. */ |
|||
int32_t ad9361_get_rx_rf_port_input (struct ad9361_rf_phy *phy, uint32_t *mode); |
|||
/* Store RX fastlock profile. */ |
|||
int32_t ad9361_rx_fastlock_store(struct ad9361_rf_phy *phy, uint32_t profile); |
|||
/* Recall RX fastlock profile. */ |
|||
int32_t ad9361_rx_fastlock_recall(struct ad9361_rf_phy *phy, uint32_t profile); |
|||
/* Load RX fastlock profile. */ |
|||
int32_t ad9361_rx_fastlock_load(struct ad9361_rf_phy *phy, uint32_t profile, uint8_t *values); |
|||
/* Save RX fastlock profile. */ |
|||
int32_t ad9361_rx_fastlock_save(struct ad9361_rf_phy *phy, uint32_t profile, uint8_t *values); |
|||
/* Set power down TX LO/Synthesizers */ |
|||
int32_t ad9361_set_rx_lo_powerdown(struct ad9361_rf_phy *phy, uint8_t pd); |
|||
/* Get power down TX LO/Synthesizers */ |
|||
int32_t ad9361_get_rx_lo_powerdown(struct ad9361_rf_phy *phy, uint8_t *pd); |
|||
/* Set the transmit attenuation for the selected channel. */ |
|||
int32_t ad9361_set_tx_attenuation (struct ad9361_rf_phy *phy, uint8_t ch, uint32_t attenuation_mdb); |
|||
/* Get current transmit attenuation for the selected channel. */ |
|||
int32_t ad9361_get_tx_attenuation (struct ad9361_rf_phy *phy, uint8_t ch, uint32_t *attenuation_mdb); |
|||
/* Set the TX RF bandwidth. */ |
|||
int32_t ad9361_set_tx_rf_bandwidth (struct ad9361_rf_phy *phy, uint32_t bandwidth_hz); |
|||
/* Get the TX RF bandwidth. */ |
|||
int32_t ad9361_get_tx_rf_bandwidth (struct ad9361_rf_phy *phy, uint32_t *bandwidth_hz); |
|||
/* Set the TX sampling frequency. */ |
|||
int32_t ad9361_set_tx_sampling_freq (struct ad9361_rf_phy *phy, uint32_t sampling_freq_hz); |
|||
/* Get current TX sampling frequency. */ |
|||
int32_t ad9361_get_tx_sampling_freq (struct ad9361_rf_phy *phy, uint32_t *sampling_freq_hz); |
|||
/* Set the TX LO frequency. */ |
|||
int32_t ad9361_set_tx_lo_freq (struct ad9361_rf_phy *phy, uint64_t lo_freq_hz); |
|||
/* Get current TX LO frequency. */ |
|||
int32_t ad9361_get_tx_lo_freq (struct ad9361_rf_phy *phy, uint64_t *lo_freq_hz); |
|||
/* Switch between internal and external LO. */ |
|||
int32_t ad9361_set_tx_lo_int_ext(struct ad9361_rf_phy *phy, uint8_t int_ext); |
|||
/* Set the TX FIR filter configuration. */ |
|||
int32_t ad9361_set_tx_fir_config (struct ad9361_rf_phy *phy, AD9361_TXFIRConfig fir_cfg); |
|||
/* Get the TX FIR filter configuration. */ |
|||
int32_t ad9361_get_tx_fir_config(struct ad9361_rf_phy *phy, uint8_t tx_ch, AD9361_TXFIRConfig *fir_cfg); |
|||
/* Enable/disable the TX FIR filter. */ |
|||
int32_t ad9361_set_tx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t en_dis); |
|||
/* Get the status of the TX FIR filter. */ |
|||
int32_t ad9361_get_tx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t *en_dis); |
|||
/* Get the TX RSSI for the selected channel. */ |
|||
int32_t ad9361_get_tx_rssi (struct ad9361_rf_phy *phy, uint8_t ch, uint32_t *rssi_db_x_1000); |
|||
/* Set the TX RF output port. */ |
|||
int32_t ad9361_set_tx_rf_port_output (struct ad9361_rf_phy *phy, uint32_t mode); |
|||
/* Get the selected TX RF output port. */ |
|||
int32_t ad9361_get_tx_rf_port_output (struct ad9361_rf_phy *phy, uint32_t *mode); |
|||
/* Enable/disable the auto calibration. */ |
|||
int32_t ad9361_set_tx_auto_cal_en_dis (struct ad9361_rf_phy *phy, uint8_t en_dis); |
|||
/* Get the status of the auto calibration flag. */ |
|||
int32_t ad9361_get_tx_auto_cal_en_dis (struct ad9361_rf_phy *phy, uint8_t *en_dis); |
|||
/* Store TX fastlock profile. */ |
|||
int32_t ad9361_tx_fastlock_store(struct ad9361_rf_phy *phy, uint32_t profile); |
|||
/* Recall TX fastlock profile. */ |
|||
int32_t ad9361_tx_fastlock_recall(struct ad9361_rf_phy *phy, uint32_t profile); |
|||
/* Load TX fastlock profile. */ |
|||
int32_t ad9361_tx_fastlock_load(struct ad9361_rf_phy *phy, uint32_t profile, uint8_t *values); |
|||
/* Save TX fastlock profile. */ |
|||
int32_t ad9361_tx_fastlock_save(struct ad9361_rf_phy *phy, uint32_t profile, uint8_t *values); |
|||
/* Set power down TX LO/Synthesizers */ |
|||
int32_t ad9361_set_tx_lo_powerdown(struct ad9361_rf_phy *phy, uint8_t pd); |
|||
/* Get power down TX LO/Synthesizers */ |
|||
int32_t ad9361_get_tx_lo_powerdown(struct ad9361_rf_phy *phy, uint8_t *pd); |
|||
/* Set the RX and TX path rates. */ |
|||
int32_t ad9361_set_trx_path_clks(struct ad9361_rf_phy *phy, uint32_t *rx_path_clks, uint32_t *tx_path_clks); |
|||
/* Get the RX and TX path rates. */ |
|||
int32_t ad9361_get_trx_path_clks(struct ad9361_rf_phy *phy, uint32_t *rx_path_clks, uint32_t *tx_path_clks); |
|||
/* Power Down RX/TX LO/Synthesizers */ |
|||
int32_t ad9361_set_trx_lo_powerdown(struct ad9361_rf_phy *phy, uint8_t pd_rx, uint8_t pd_tx); |
|||
/* Set the number of channels mode. */ |
|||
int32_t ad9361_set_no_ch_mode(struct ad9361_rf_phy *phy, uint8_t no_ch_mode); |
|||
/* Do multi chip synchronization. */ |
|||
//int32_t ad9361_do_mcs(struct ad9361_rf_phy *phy_master, struct ad9361_rf_phy *phy_slave);
|
|||
/* Enable/disable the TRX FIR filters. */ |
|||
int32_t ad9361_set_trx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t en_dis); |
|||
/* Set the OSR rate governor. */ |
|||
int32_t ad9361_set_trx_rate_gov (struct ad9361_rf_phy *phy, uint32_t rate_gov); |
|||
/* Get the OSR rate governor. */ |
|||
int32_t ad9361_get_trx_rate_gov (struct ad9361_rf_phy *phy, uint32_t *rate_gov); |
|||
/* Perform the selected calibration. */ |
|||
int32_t ad9361_do_calib(struct ad9361_rf_phy *phy, uint32_t cal, int32_t arg); |
|||
/* Load and enable TRX FIR filters configurations. */ |
|||
int32_t ad9361_trx_load_enable_fir(struct ad9361_rf_phy *phy, |
|||
AD9361_RXFIRConfig rx_fir_cfg, |
|||
AD9361_TXFIRConfig tx_fir_cfg); |
|||
/* Do DCXO coarse tuning. */ |
|||
int32_t ad9361_do_dcxo_tune_coarse(struct ad9361_rf_phy *phy, |
|||
uint32_t coarse); |
|||
/* Do DCXO fine tuning. */ |
|||
int32_t ad9361_do_dcxo_tune_fine(struct ad9361_rf_phy *phy, |
|||
uint32_t fine); |
|||
#endif |
|||
@ -0,0 +1,597 @@ |
|||
|
|||
/***************************************************************************//**
|
|||
* @file ad9361_conv.c |
|||
* @brief Implementation of AD9361 Conv Driver. |
|||
******************************************************************************** |
|||
* Copyright 2014-2015(c) Analog Devices, Inc. |
|||
* |
|||
* All rights reserved. |
|||
* |
|||
* Redistribution and use in source and binary forms, with or without |
|||
* modification, are permitted provided that the following conditions are met: |
|||
* - Redistributions of source code must retain the above copyright |
|||
* notice, this list of conditions and the following disclaimer. |
|||
* - Redistributions in binary form must reproduce the above copyright |
|||
* notice, this list of conditions and the following disclaimer in |
|||
* the documentation and/or other materials provided with the |
|||
* distribution. |
|||
* - Neither the name of Analog Devices, Inc. nor the names of its |
|||
* contributors may be used to endorse or promote products derived |
|||
* from this software without specific prior written permission. |
|||
* - The use of this software may or may not infringe the patent rights |
|||
* of one or more patent holders. This license does not release you |
|||
* from the requirement that you obtain separate licenses from these |
|||
* patent holders to use this software. |
|||
* - Use of the software either in source or binary form, must be run |
|||
* on or directly connected to an Analog Devices Inc. component. |
|||
* |
|||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR |
|||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, |
|||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
|||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, |
|||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
|||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR |
|||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
|||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
|||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
|||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
|||
*******************************************************************************/ |
|||
|
|||
/******************************************************************************/ |
|||
/***************************** Include Files **********************************/ |
|||
/******************************************************************************/ |
|||
#include <inttypes.h> |
|||
#include <string.h> |
|||
#include "ad9361.h" |
|||
#include "platform.h" |
|||
#include "config.h" |
|||
|
|||
#ifndef AXI_ADC_NOT_PRESENT |
|||
/**
|
|||
* HDL loopback enable/disable. |
|||
* @param phy The AD9361 state structure. |
|||
* @param enable Enable/disable option. |
|||
* @return 0 in case of success, negative error code otherwise. |
|||
*/ |
|||
int32_t ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable) |
|||
{ |
|||
struct axiadc_converter *conv = phy->adc_conv; |
|||
struct axiadc_state *st = phy->adc_state; |
|||
int32_t reg, addr, chan; |
|||
|
|||
uint32_t version = axiadc_read(st, 0x4000); |
|||
|
|||
/* Still there but implemented a bit different */ |
|||
if (PCORE_VERSION_MAJOR(version) > 7) |
|||
addr = 0x4418; |
|||
else |
|||
addr = 0x4414; |
|||
|
|||
for (chan = 0; chan < conv->chip_info->num_channels; chan++) { |
|||
reg = axiadc_read(st, addr + (chan) * 0x40); |
|||
|
|||
if (PCORE_VERSION_MAJOR(version) > 7) { |
|||
if (enable && reg != 0x8) { |
|||
conv->scratch_reg[chan] = reg; |
|||
reg = 0x8; |
|||
} else if (reg == 0x8) { |
|||
reg = conv->scratch_reg[chan]; |
|||
} |
|||
} else { |
|||
/* DAC_LB_ENB If set enables loopback of receive data */ |
|||
if (enable) |
|||
reg |= BIT(1); |
|||
else |
|||
reg &= ~BIT(1); |
|||
} |
|||
axiadc_write(st, addr + (chan) * 0x40, reg); |
|||
} |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
/**
|
|||
* Set IO delay. |
|||
* @param st The AXI ADC state structure. |
|||
* @param lane Lane number. |
|||
* @param val Value. |
|||
* @param tx The Synthesizer TX = 1, RX = 0. |
|||
* @return 0 in case of success, negative error code otherwise. |
|||
*/ |
|||
static int32_t ad9361_iodelay_set(struct axiadc_state *st, unsigned lane, |
|||
unsigned val, bool tx) |
|||
{ |
|||
if (tx) { |
|||
if (PCORE_VERSION_MAJOR(st->pcore_version) > 8) |
|||
axiadc_write(st, 0x4000 + ADI_REG_DELAY(lane), val); |
|||
else |
|||
return -ENODEV; |
|||
} else { |
|||
axiadc_idelay_set(st, lane, val); |
|||
} |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
/**
|
|||
* Set midscale IO delay. |
|||
* @param phy The AD9361 state structure. |
|||
* @param tx The Synthesizer TX = 1, RX = 0. |
|||
* @return 0 in case of success, negative error code otherwise. |
|||
*/ |
|||
static int32_t ad9361_midscale_iodelay(struct ad9361_rf_phy *phy, bool tx) |
|||
{ |
|||
struct axiadc_state *st = phy->adc_state; |
|||
int32_t ret = 0, i; |
|||
|
|||
for (i = 0; i < 7; i++) |
|||
ret |= ad9361_iodelay_set(st, i, 15, tx); |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
/**
|
|||
* Digital tune IO delay. |
|||
* @param phy The AD9361 state structure. |
|||
* @param tx The Synthesizer TX = 1, RX = 0. |
|||
* @return 0 in case of success, negative error code otherwise. |
|||
*/ |
|||
static int32_t ad9361_dig_tune_iodelay(struct ad9361_rf_phy *phy, bool tx) |
|||
{ |
|||
struct axiadc_converter *conv = phy->adc_conv; |
|||
struct axiadc_state *st = phy->adc_state; |
|||
int32_t ret, i, j, chan, num_chan; |
|||
uint32_t s0, c0; |
|||
uint8_t field[32]; |
|||
|
|||
num_chan = (conv->chip_info->num_channels > 4) ? 4 : conv->chip_info->num_channels; |
|||
|
|||
for (i = 0; i < 7; i++) { |
|||
for (j = 0; j < 32; j++) { |
|||
ad9361_iodelay_set(st, i, j, tx); |
|||
mdelay(1); |
|||
|
|||
for (chan = 0; chan < num_chan; chan++) |
|||
axiadc_write(st, ADI_REG_CHAN_STATUS(chan), |
|||
ADI_PN_ERR | ADI_PN_OOS); |
|||
mdelay(10); |
|||
|
|||
for (chan = 0, ret = 0; chan < num_chan; chan++) |
|||
ret |= axiadc_read(st, ADI_REG_CHAN_STATUS(chan)); |
|||
|
|||
field[j] = ret; |
|||
} |
|||
|
|||
c0 = ad9361_find_opt(&field[0], 32, &s0); |
|||
ad9361_iodelay_set(st, i, s0 + c0 / 2, tx); |
|||
|
|||
dev_dbg(&phy->spi->dev, |
|||
"%s Lane %"PRId32", window cnt %"PRIu32" , start %"PRIu32", IODELAY set to %"PRIu32"\n", |
|||
tx ? "TX" :"RX", i , c0, s0, s0 + c0 / 2); |
|||
} |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
/**
|
|||
* Digital tune verbose print. |
|||
* @param phy The AD9361 state structure. |
|||
* @param field Field. |
|||
* @param tx The Synthesizer TX = 1, RX = 0. |
|||
* @return 0 in case of success, negative error code otherwise. |
|||
*/ |
|||
static void ad9361_dig_tune_verbose_print(struct ad9361_rf_phy *phy, |
|||
uint8_t field[][16], bool tx) |
|||
{ |
|||
int32_t i, j; |
|||
|
|||
printk("SAMPL CLK: %"PRIu32" tuning: %s\n", |
|||
clk_get_rate(phy, phy->ref_clk_scale[RX_SAMPL_CLK]), tx ? "TX" : "RX"); |
|||
printk(" "); |
|||
for (i = 0; i < 16; i++) |
|||
printk("%"PRIx32":", i); |
|||
printk("\n"); |
|||
|
|||
for (i = 0; i < 2; i++) { |
|||
printk("%"PRIx32":", i); |
|||
for (j = 0; j < 16; j++) { |
|||
printk("%c ", (field[i][j] ? '#' : 'o')); |
|||
} |
|||
printk("\n"); |
|||
} |
|||
printk("\n"); |
|||
} |
|||
|
|||
/**
|
|||
* Digital interface timing analysis. |
|||
* @param phy The AD9361 state structure. |
|||
* @param buf The buffer. |
|||
* @param buflen The buffer length. |
|||
* @return The size in case of success, negative error code otherwise. |
|||
*/ |
|||
int32_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy, |
|||
char *buf, int32_t buflen) |
|||
{ |
|||
struct axiadc_state *st = phy->adc_state; |
|||
int32_t ret, i, j, chan, len = 0; |
|||
uint8_t field[16][16]; |
|||
uint8_t rx; |
|||
|
|||
dev_dbg(&phy->spi->dev, "%s:\n", __func__); |
|||
|
|||
rx = ad9361_spi_read(phy->spi, REG_RX_CLOCK_DATA_DELAY); |
|||
|
|||
ad9361_bist_prbs(phy, BIST_INJ_RX); |
|||
|
|||
for (i = 0; i < 16; i++) { |
|||
for (j = 0; j < 16; j++) { |
|||
ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY, |
|||
DATA_CLK_DELAY(j) | RX_DATA_DELAY(i)); |
|||
for (chan = 0; chan < 4; chan++) |
|||
axiadc_write(st, ADI_REG_CHAN_STATUS(chan), |
|||
ADI_PN_ERR | ADI_PN_OOS); |
|||
|
|||
mdelay(1); |
|||
|
|||
if (axiadc_read(st, ADI_REG_STATUS) & ADI_STATUS) { |
|||
for (chan = 0, ret = 0; chan < 4; chan++) |
|||
ret |= axiadc_read(st, ADI_REG_CHAN_STATUS(chan)); |
|||
} |
|||
else { |
|||
ret = 1; |
|||
} |
|||
|
|||
field[i][j] = ret; |
|||
} |
|||
} |
|||
|
|||
ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY, rx); |
|||
|
|||
ad9361_bist_prbs(phy, BIST_DISABLE); |
|||
|
|||
len += snprintf(buf + len, buflen, "CLK: %"PRIu32" Hz 'o' = PASS\n", |
|||
clk_get_rate(phy, phy->ref_clk_scale[RX_SAMPL_CLK])); |
|||
len += snprintf(buf + len, buflen, "DC"); |
|||
for (i = 0; i < 16; i++) |
|||
len += snprintf(buf + len, buflen, "%"PRIx32":", i); |
|||
len += snprintf(buf + len, buflen, "\n"); |
|||
|
|||
for (i = 0; i < 16; i++) { |
|||
len += snprintf(buf + len, buflen, "%"PRIx32":", i); |
|||
for (j = 0; j < 16; j++) { |
|||
len += snprintf(buf + len, buflen, "%c ", |
|||
(field[i][j] ? '.' : 'o')); |
|||
} |
|||
len += snprintf(buf + len, buflen, "\n"); |
|||
} |
|||
len += snprintf(buf + len, buflen, "\n"); |
|||
|
|||
return len; |
|||
} |
|||
|
|||
/**
|
|||
* Digital tune. |
|||
* @param phy The AD9361 state structure. |
|||
* @param max_freq Maximum frequency. |
|||
* @param flags Flags: BE_VERBOSE, BE_MOREVERBOSE, DO_IDELAY, DO_ODELAY. |
|||
* @return 0 in case of success, negative error code otherwise. |
|||
*/ |
|||
int32_t ad9361_dig_tune(struct ad9361_rf_phy *phy, uint32_t max_freq, |
|||
enum dig_tune_flags flags) |
|||
{ |
|||
struct axiadc_converter *conv = phy->adc_conv; |
|||
struct axiadc_state *st = phy->adc_state; |
|||
int32_t ret, i, j, k, chan, t, num_chan, err = 0; |
|||
uint32_t s0, s1, c0, c1, tmp, saved = 0; |
|||
uint8_t field[2][16]; |
|||
uint32_t saved_dsel[4], saved_chan_ctrl6[4], saved_chan_ctrl0[4]; |
|||
uint32_t rates[3] = {25000000U, 40000000U, 61440000U}; |
|||
uint32_t hdl_dac_version; |
|||
|
|||
dev_dbg(&phy->spi->dev, "%s: freq %"PRIu32" flags 0x%X\n", __func__, |
|||
max_freq, flags); |
|||
|
|||
hdl_dac_version = axiadc_read(st, 0x4000); |
|||
|
|||
if ((phy->pdata->dig_interface_tune_skipmode == 2) || |
|||
(flags & RESTORE_DEFAULT)) { |
|||
/* skip completely and use defaults */ |
|||
ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY, |
|||
phy->pdata->port_ctrl.rx_clk_data_delay); |
|||
|
|||
ad9361_spi_write(phy->spi, REG_TX_CLOCK_DATA_DELAY, |
|||
phy->pdata->port_ctrl.tx_clk_data_delay); |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
/* Mute TX, we don't want to transmit the PRBS */ |
|||
ad9361_tx_mute(phy, 1); |
|||
|
|||
if (flags & DO_IDELAY) |
|||
ad9361_midscale_iodelay(phy, 0); |
|||
|
|||
if (flags & DO_ODELAY) |
|||
ad9361_midscale_iodelay(phy, 1); |
|||
|
|||
if (!phy->pdata->fdd) { |
|||
ad9361_set_ensm_mode(phy, true, false); |
|||
ad9361_ensm_force_state(phy, ENSM_STATE_FDD); |
|||
} else { |
|||
ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); |
|||
ad9361_ensm_restore_prev_state(phy); |
|||
} |
|||
|
|||
num_chan = (conv->chip_info->num_channels > 4) ? 4 : |
|||
conv->chip_info->num_channels; |
|||
|
|||
ad9361_bist_prbs(phy, BIST_INJ_RX); |
|||
|
|||
for (t = 0; t < 2; t++) { |
|||
memset(field, 0, 32); |
|||
for (k = 0; (uint32_t)k < (max_freq ? ARRAY_SIZE(rates) : 1); k++) { |
|||
if (max_freq) |
|||
ad9361_set_trx_clock_chain_freq(phy, |
|||
((phy->pdata->port_ctrl.pp_conf[2] & LVDS_MODE) || !phy->pdata->rx2tx2) ? |
|||
rates[k] : rates[k] / 2); |
|||
for (i = 0; i < 2; i++) { |
|||
for (j = 0; j < 16; j++) { |
|||
ad9361_spi_write(phy->spi, |
|||
REG_RX_CLOCK_DATA_DELAY + t, |
|||
RX_DATA_DELAY(i == 0 ? j : 0) | |
|||
DATA_CLK_DELAY(i ? j : 0)); |
|||
for (chan = 0; chan < num_chan; chan++) |
|||
axiadc_write(st, ADI_REG_CHAN_STATUS(chan), |
|||
ADI_PN_ERR | ADI_PN_OOS); |
|||
mdelay(4); |
|||
|
|||
if ((t == 1) || (axiadc_read(st, ADI_REG_STATUS) & ADI_STATUS)) { |
|||
for (chan = 0, ret = 0; chan < num_chan; chan++) { |
|||
ret |= axiadc_read(st, ADI_REG_CHAN_STATUS(chan)); |
|||
} |
|||
} |
|||
else { |
|||
ret = 1; |
|||
} |
|||
|
|||
field[i][j] |= ret; |
|||
} |
|||
} |
|||
if ((flags & BE_MOREVERBOSE) && max_freq) { |
|||
ad9361_dig_tune_verbose_print(phy, field, t); |
|||
} |
|||
} |
|||
|
|||
c0 = ad9361_find_opt(&field[0][0], 16, &s0); |
|||
c1 = ad9361_find_opt(&field[1][0], 16, &s1); |
|||
|
|||
if (!c0 && !c1) { |
|||
ad9361_dig_tune_verbose_print(phy, field, t); |
|||
dev_err(&phy->spi->dev, "%s: Tuning %s FAILED!", __func__, |
|||
t ? "TX" : "RX"); |
|||
err |= -EIO; |
|||
} else if (flags & BE_VERBOSE) { |
|||
ad9361_dig_tune_verbose_print(phy, field, t); |
|||
} |
|||
|
|||
if (c1 > c0) |
|||
ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY + t, |
|||
DATA_CLK_DELAY(s1 + c1 / 2) | |
|||
RX_DATA_DELAY(0)); |
|||
else |
|||
ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY + t, |
|||
DATA_CLK_DELAY(0) | |
|||
RX_DATA_DELAY(s0 + c0 / 2)); |
|||
|
|||
if (t == 0) { |
|||
if (flags & DO_IDELAY) |
|||
ad9361_dig_tune_iodelay(phy, 0); |
|||
|
|||
/* Now do the loopback and tune the digital out */ |
|||
ad9361_bist_prbs(phy, BIST_DISABLE); |
|||
|
|||
axiadc_write(st, ADI_REG_RSTN, ADI_MMCM_RSTN); |
|||
axiadc_write(st, ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN); |
|||
|
|||
if (phy->pdata->dig_interface_tune_skipmode == 1) { |
|||
/* skip TX */ |
|||
if (!(flags & SKIP_STORE_RESULT)) |
|||
phy->pdata->port_ctrl.rx_clk_data_delay = |
|||
ad9361_spi_read(phy->spi, REG_RX_CLOCK_DATA_DELAY); |
|||
|
|||
if (!phy->pdata->fdd) { |
|||
ad9361_set_ensm_mode(phy, phy->pdata->fdd, |
|||
phy->pdata->ensm_pin_ctrl); |
|||
ad9361_ensm_restore_prev_state(phy); |
|||
} |
|||
|
|||
ad9361_tx_mute(phy, 0); |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
ad9361_bist_loopback(phy, 1); |
|||
axiadc_write(st, 0x4000 + ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN); |
|||
|
|||
for (chan = 0; chan < num_chan; chan++) { |
|||
saved_chan_ctrl0[chan] = axiadc_read(st, ADI_REG_CHAN_CNTRL(chan)); |
|||
axiadc_write(st, ADI_REG_CHAN_CNTRL(chan), |
|||
ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE | |
|||
ADI_ENABLE | ADI_IQCOR_ENB); |
|||
axiadc_set_pnsel(st, chan, ADC_PN_CUSTOM); |
|||
saved_chan_ctrl6[chan] = axiadc_read(st, 0x4414 + (chan) * 0x40); |
|||
if (PCORE_VERSION_MAJOR(hdl_dac_version) > 7) |
|||
{ |
|||
saved_dsel[chan] = axiadc_read(st, 0x4418 + (chan) * 0x40); |
|||
axiadc_write(st, 0x4418 + (chan) * 0x40, 9); |
|||
axiadc_write(st, 0x4414 + (chan) * 0x40, 0); /* !IQCOR_ENB */ |
|||
axiadc_write(st, 0x4044, 0x1); |
|||
} |
|||
else |
|||
axiadc_write(st, 0x4414 + (chan) * 0x40, 1); /* DAC_PN_ENB */ |
|||
|
|||
} |
|||
if (PCORE_VERSION_MAJOR(hdl_dac_version) < 8) { |
|||
saved = tmp = axiadc_read(st, 0x4048); |
|||
tmp &= ~0xF; |
|||
tmp |= 1; |
|||
axiadc_write(st, 0x4048, tmp); |
|||
|
|||
} |
|||
} else { |
|||
if (flags & DO_ODELAY) |
|||
ad9361_dig_tune_iodelay(phy, 1); |
|||
|
|||
ad9361_bist_loopback(phy, 0); |
|||
|
|||
if (PCORE_VERSION_MAJOR(hdl_dac_version) < 8) |
|||
axiadc_write(st, 0x4048, saved); |
|||
|
|||
for (chan = 0; chan < num_chan; chan++) { |
|||
axiadc_write(st, ADI_REG_CHAN_CNTRL(chan), |
|||
saved_chan_ctrl0[chan]); |
|||
axiadc_set_pnsel(st, chan, ADC_PN9); |
|||
if (PCORE_VERSION_MAJOR(hdl_dac_version) > 7) |
|||
{ |
|||
axiadc_write(st, 0x4418 + (chan) * 0x40, saved_dsel[chan]); |
|||
axiadc_write(st, 0x4044, 0x1); |
|||
} |
|||
|
|||
axiadc_write(st, 0x4414 + (chan) * 0x40, saved_chan_ctrl6[chan]); |
|||
|
|||
} |
|||
|
|||
if (err == -EIO) { |
|||
ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY, |
|||
phy->pdata->port_ctrl.rx_clk_data_delay); |
|||
|
|||
ad9361_spi_write(phy->spi, REG_TX_CLOCK_DATA_DELAY, |
|||
phy->pdata->port_ctrl.tx_clk_data_delay); |
|||
if (!max_freq) |
|||
err = 0; |
|||
} else if (!(flags & SKIP_STORE_RESULT)) { |
|||
phy->pdata->port_ctrl.rx_clk_data_delay = |
|||
ad9361_spi_read(phy->spi, REG_RX_CLOCK_DATA_DELAY); |
|||
phy->pdata->port_ctrl.tx_clk_data_delay = |
|||
ad9361_spi_read(phy->spi, REG_TX_CLOCK_DATA_DELAY); |
|||
} |
|||
|
|||
if (!phy->pdata->fdd) { |
|||
ad9361_set_ensm_mode(phy, phy->pdata->fdd, phy->pdata->ensm_pin_ctrl); |
|||
ad9361_ensm_restore_prev_state(phy); |
|||
} |
|||
|
|||
axiadc_write(st, ADI_REG_RSTN, ADI_MMCM_RSTN); |
|||
axiadc_write(st, ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN); |
|||
|
|||
ad9361_tx_mute(phy, 0); |
|||
|
|||
return err; |
|||
} |
|||
} |
|||
|
|||
return -EINVAL; |
|||
} |
|||
|
|||
/**
|
|||
* Setup the AD9361 device. |
|||
* @param phy The AD9361 state structure. |
|||
* @return 0 in case of success, negative error code otherwise. |
|||
*/ |
|||
int32_t ad9361_post_setup(struct ad9361_rf_phy *phy) |
|||
{ |
|||
struct axiadc_converter *conv = phy->adc_conv; |
|||
struct axiadc_state *st = phy->adc_state; |
|||
int32_t rx2tx2 = phy->pdata->rx2tx2; |
|||
int32_t tmp, num_chan, flags; |
|||
int32_t i, ret; |
|||
|
|||
num_chan = (conv->chip_info->num_channels > 4) ? 4 : conv->chip_info->num_channels; |
|||
|
|||
axiadc_write(st, ADI_REG_CNTRL, rx2tx2 ? 0 : ADI_R1_MODE); |
|||
tmp = axiadc_read(st, 0x4048); |
|||
|
|||
if (!rx2tx2) { |
|||
axiadc_write(st, 0x4048, tmp | BIT(5)); /* R1_MODE */ |
|||
axiadc_write(st, 0x404c, |
|||
(phy->pdata->port_ctrl.pp_conf[2] & LVDS_MODE) ? 1 : 0); /* RATE */ |
|||
} |
|||
else { |
|||
tmp &= ~BIT(5); |
|||
axiadc_write(st, 0x4048, tmp); |
|||
axiadc_write(st, 0x404c, |
|||
(phy->pdata->port_ctrl.pp_conf[2] & LVDS_MODE) ? 3 : 1); /* RATE */ |
|||
} |
|||
|
|||
#ifdef ALTERA_PLATFORM |
|||
axiadc_write(st, 0x404c, 1); |
|||
#endif |
|||
|
|||
for (i = 0; i < num_chan; i++) { |
|||
axiadc_write(st, ADI_REG_CHAN_CNTRL_1(i), |
|||
ADI_DCFILT_OFFSET(0)); |
|||
axiadc_write(st, ADI_REG_CHAN_CNTRL_2(i), |
|||
(i & 1) ? 0x00004000 : 0x40000000); |
|||
axiadc_write(st, ADI_REG_CHAN_CNTRL(i), |
|||
ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE | |
|||
ADI_ENABLE | ADI_IQCOR_ENB); |
|||
} |
|||
|
|||
flags = 0x0; |
|||
|
|||
ret = ad9361_dig_tune(phy, ((conv->chip_info->num_channels > 4) || |
|||
axiadc_read(st, 0x0004)) ? 0 : 61440000, flags); |
|||
if (ret < 0) |
|||
return ret; |
|||
|
|||
if (flags & (DO_IDELAY | DO_ODELAY)) { |
|||
ret = ad9361_dig_tune(phy, (axiadc_read(st, ADI_REG_ID)) ? |
|||
0 : 61440000, flags & BE_VERBOSE); |
|||
if (ret < 0) |
|||
return ret; |
|||
} |
|||
|
|||
ret = ad9361_set_trx_clock_chain(phy, |
|||
phy->pdata->rx_path_clks, |
|||
phy->pdata->tx_path_clks); |
|||
|
|||
ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); |
|||
ad9361_ensm_restore_prev_state(phy); |
|||
|
|||
return ret; |
|||
} |
|||
#else |
|||
/**
|
|||
* HDL loopback enable/disable. |
|||
* @param phy The AD9361 state structure. |
|||
* @param enable Enable/disable option. |
|||
* @return 0 in case of success, negative error code otherwise. |
|||
*/ |
|||
int32_t ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable) |
|||
{ |
|||
return -ENODEV; |
|||
} |
|||
|
|||
/**
|
|||
* Digital tune. |
|||
* @param phy The AD9361 state structure. |
|||
* @param max_freq Maximum frequency. |
|||
* @param flags Flags: BE_VERBOSE, BE_MOREVERBOSE, DO_IDELAY, DO_ODELAY. |
|||
* @return 0 in case of success, negative error code otherwise. |
|||
*/ |
|||
int32_t ad9361_dig_tune(struct ad9361_rf_phy *phy, uint32_t max_freq, |
|||
enum dig_tune_flags flags) |
|||
{ |
|||
return 0; |
|||
} |
|||
|
|||
/**
|
|||
* Setup the AD9361 device. |
|||
* @param phy The AD9361 state structure. |
|||
* @return 0 in case of success, negative error code otherwise. |
|||
*/ |
|||
int32_t ad9361_post_setup(struct ad9361_rf_phy *phy) |
|||
{ |
|||
return 0; |
|||
} |
|||
#endif |
|||
@ -0,0 +1,116 @@ |
|||
/***************************************************************************//**
|
|||
* @file common.h |
|||
* @brief Header file of Common Driver. |
|||
* @author DBogdan (dragos.bogdan@analog.com) |
|||
******************************************************************************** |
|||
* Copyright 2013(c) Analog Devices, Inc. |
|||
* |
|||
* All rights reserved. |
|||
* |
|||
* Redistribution and use in source and binary forms, with or without |
|||
* modification, are permitted provided that the following conditions are met: |
|||
* - Redistributions of source code must retain the above copyright |
|||
* notice, this list of conditions and the following disclaimer. |
|||
* - Redistributions in binary form must reproduce the above copyright |
|||
* notice, this list of conditions and the following disclaimer in |
|||
* the documentation and/or other materials provided with the |
|||
* distribution. |
|||
* - Neither the name of Analog Devices, Inc. nor the names of its |
|||
* contributors may be used to endorse or promote products derived |
|||
* from this software without specific prior written permission. |
|||
* - The use of this software may or may not infringe the patent rights |
|||
* of one or more patent holders. This license does not release you |
|||
* from the requirement that you obtain separate licenses from these |
|||
* patent holders to use this software. |
|||
* - Use of the software either in source or binary form, must be run |
|||
* on or directly connected to an Analog Devices Inc. component. |
|||
* |
|||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR |
|||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, |
|||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
|||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, |
|||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
|||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR |
|||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
|||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
|||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
|||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
|||
*******************************************************************************/ |
|||
#ifndef COMMON_H_ |
|||
#define COMMON_H_ |
|||
|
|||
/******************************************************************************/ |
|||
/***************************** Include Files **********************************/ |
|||
/******************************************************************************/ |
|||
#include <stdint.h> |
|||
|
|||
/******************************************************************************/ |
|||
/********************** Macros and Constants Definitions **********************/ |
|||
/******************************************************************************/ |
|||
#define EIO 5 /* I/O error */ |
|||
#define EAGAIN 11 /* Try again */ |
|||
#define ENOMEM 12 /* Out of memory */ |
|||
#define EFAULT 14 /* Bad address */ |
|||
#define ENODEV 19 /* No such device */ |
|||
#define EINVAL 22 /* Invalid argument */ |
|||
#define ETIMEDOUT 110 /* Connection timed out */ |
|||
|
|||
/******************************************************************************/ |
|||
/*************************** Types Declarations *******************************/ |
|||
/******************************************************************************/ |
|||
#if defined (__STDC__) && (__STDC_VERSION__ >= 199901L) |
|||
#include <stdbool.h> |
|||
#else |
|||
typedef enum { false, true } bool; |
|||
#endif |
|||
|
|||
/* copy from config.h */ |
|||
#define HAVE_VERBOSE_MESSAGES /* Recommended during development prints errors and warnings */ |
|||
//#define HAVE_DEBUG_MESSAGES /* For Debug purposes only */
|
|||
|
|||
/*
|
|||
* In case memory footprint is a concern these options allow |
|||
* to disable unused functionality which may free up a few kb |
|||
*/ |
|||
|
|||
#define HAVE_SPLIT_GAIN_TABLE 1 /* only set to 0 in case split_gain_table_mode_enable = 0*/ |
|||
#define HAVE_TDD_SYNTH_TABLE 1 /* only set to 0 in case split_gain_table_mode_enable = 0*/ |
|||
|
|||
#define AD9361_DEVICE 1 /* set it 1 if AD9361 device is used, 0 otherwise */ |
|||
#define AD9364_DEVICE 0 /* set it 1 if AD9364 device is used, 0 otherwise */ |
|||
#define AD9363A_DEVICE 0 /* set it 1 if AD9363A device is used, 0 otherwise */ |
|||
|
|||
//#define CONSOLE_COMMANDS
|
|||
#define XILINX_PLATFORM |
|||
//#define ALTERA_PLATFORM
|
|||
//#define FMCOMMS5
|
|||
//#define PICOZED_SDR
|
|||
//#define PICOZED_SDR_CMOS
|
|||
#define CAPTURE_SCRIPT |
|||
#define AXI_ADC_NOT_PRESENT |
|||
#define TDD_SWITCH_STATE_EXAMPLE |
|||
|
|||
struct clk { |
|||
const char *name; |
|||
uint32_t rate; |
|||
}; |
|||
|
|||
struct clk_hw { |
|||
struct clk *clk; |
|||
}; |
|||
|
|||
struct clk_init_data { |
|||
const char *name; |
|||
const struct clk_ops *ops; |
|||
const char **parent_names; |
|||
uint8_t num_parents; |
|||
uint32_t flags; |
|||
}; |
|||
|
|||
struct clk_onecell_data { |
|||
struct clk **clks; |
|||
uint32_t clk_num; |
|||
}; |
|||
|
|||
#endif |
|||
|
|||
@ -0,0 +1,36 @@ |
|||
#include "spi.h" |
|||
#include "gpio.h" |
|||
#include "dwt.h" |
|||
#include "util.h" |
|||
#include "platform.h" |
|||
|
|||
int gpio_is_valid(int number) |
|||
{ |
|||
if (number > 0) { |
|||
return 1; |
|||
} |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
void gpio_set_value(unsigned gpio, int value) |
|||
{ |
|||
gpio_write(gpio, value); |
|||
} |
|||
|
|||
void udelay(unsigned long us) |
|||
{ |
|||
dwt_wait_us(us); |
|||
} |
|||
|
|||
void mdelay(unsigned long ms) |
|||
{ |
|||
dwt_wait_ms(ms); |
|||
} |
|||
|
|||
int spi_write_then_read(struct spi_device *spi, const unsigned char *txbuf, unsigned n_tx, |
|||
unsigned char *rxbuf, unsigned n_rx) |
|||
{ |
|||
return SUCCESS; |
|||
} |
|||
|
|||
@ -0,0 +1,15 @@ |
|||
#ifndef __PLATFORM_H__ |
|||
#define __PLATFORM_H__ |
|||
|
|||
struct spi_device; |
|||
int spi_write_then_read(struct spi_device *, const unsigned char *txbuf, unsigned n_tx, |
|||
unsigned char *rxbuf, unsigned n_rx); |
|||
|
|||
int gpio_is_valid(int number); |
|||
void gpio_set_value(unsigned gpio, int value); |
|||
|
|||
void mdelay(unsigned long ms); |
|||
void udelay(unsigned long us); |
|||
|
|||
#endif |
|||
|
|||
@ -0,0 +1,347 @@ |
|||
/***************************************************************************//**
|
|||
* @file util.c |
|||
* @brief Implementation of Util Driver. |
|||
* @author DBogdan (dragos.bogdan@analog.com) |
|||
******************************************************************************** |
|||
* Copyright 2013(c) Analog Devices, Inc. |
|||
* |
|||
* All rights reserved. |
|||
* |
|||
* Redistribution and use in source and binary forms, with or without |
|||
* modification, are permitted provided that the following conditions are met: |
|||
* - Redistributions of source code must retain the above copyright |
|||
* notice, this list of conditions and the following disclaimer. |
|||
* - Redistributions in binary form must reproduce the above copyright |
|||
* notice, this list of conditions and the following disclaimer in |
|||
* the documentation and/or other materials provided with the |
|||
* distribution. |
|||
* - Neither the name of Analog Devices, Inc. nor the names of its |
|||
* contributors may be used to endorse or promote products derived |
|||
* from this software without specific prior written permission. |
|||
* - The use of this software may or may not infringe the patent rights |
|||
* of one or more patent holders. This license does not release you |
|||
* from the requirement that you obtain separate licenses from these |
|||
* patent holders to use this software. |
|||
* - Use of the software either in source or binary form, must be run |
|||
* on or directly connected to an Analog Devices Inc. component. |
|||
* |
|||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR |
|||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, |
|||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
|||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, |
|||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
|||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR |
|||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
|||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
|||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
|||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
|||
*******************************************************************************/ |
|||
|
|||
/******************************************************************************/ |
|||
/***************************** Include Files **********************************/ |
|||
/******************************************************************************/ |
|||
#include "util.h" |
|||
#include "string.h" |
|||
#include "spi.h" |
|||
#include "platform.h" |
|||
|
|||
/******************************************************************************/ |
|||
/*************************** Macros Definitions *******************************/ |
|||
/******************************************************************************/ |
|||
#define BITS_PER_LONG 32 |
|||
|
|||
/***************************************************************************//**
|
|||
* @brief clk_prepare_enable |
|||
*******************************************************************************/ |
|||
int32_t clk_prepare_enable(struct clk *clk) |
|||
{ |
|||
if (clk) { |
|||
// Unused variable - fix compiler warning
|
|||
} |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
/***************************************************************************//**
|
|||
* @brief clk_get_rate |
|||
*******************************************************************************/ |
|||
uint32_t clk_get_rate(struct ad9361_rf_phy *phy, |
|||
struct refclk_scale *clk_priv) |
|||
{ |
|||
uint32_t rate = 0; |
|||
uint32_t source; |
|||
|
|||
source = clk_priv->source; |
|||
|
|||
switch (source) { |
|||
case TX_REFCLK: |
|||
case RX_REFCLK: |
|||
case BB_REFCLK: |
|||
rate = ad9361_clk_factor_recalc_rate(clk_priv, |
|||
phy->clk_refin->rate); |
|||
break; |
|||
case TX_RFPLL_INT: |
|||
case RX_RFPLL_INT: |
|||
rate = ad9361_rfpll_int_recalc_rate(clk_priv, |
|||
phy->clks[clk_priv->parent_source]->rate); |
|||
case RX_RFPLL_DUMMY: |
|||
case TX_RFPLL_DUMMY: |
|||
rate = ad9361_rfpll_dummy_recalc_rate(clk_priv); |
|||
break; |
|||
case TX_RFPLL: |
|||
case RX_RFPLL: |
|||
rate = ad9361_rfpll_recalc_rate(clk_priv); |
|||
break; |
|||
case BBPLL_CLK: |
|||
rate = ad9361_bbpll_recalc_rate(clk_priv, |
|||
phy->clks[clk_priv->parent_source]->rate); |
|||
break; |
|||
case ADC_CLK: |
|||
case R2_CLK: |
|||
case R1_CLK: |
|||
case CLKRF_CLK: |
|||
case RX_SAMPL_CLK: |
|||
case DAC_CLK: |
|||
case T2_CLK: |
|||
case T1_CLK: |
|||
case CLKTF_CLK: |
|||
case TX_SAMPL_CLK: |
|||
rate = ad9361_clk_factor_recalc_rate(clk_priv, |
|||
phy->clks[clk_priv->parent_source]->rate); |
|||
break; |
|||
default: |
|||
break; |
|||
} |
|||
|
|||
return rate; |
|||
} |
|||
|
|||
/***************************************************************************//**
|
|||
* @brief clk_set_rate |
|||
*******************************************************************************/ |
|||
int32_t clk_set_rate(struct ad9361_rf_phy *phy, |
|||
struct refclk_scale *clk_priv, |
|||
uint32_t rate) |
|||
{ |
|||
uint32_t source; |
|||
int32_t i; |
|||
uint32_t round_rate; |
|||
|
|||
source = clk_priv->source; |
|||
if(phy->clks[source]->rate != rate) |
|||
{ |
|||
switch (source) { |
|||
case TX_REFCLK: |
|||
case RX_REFCLK: |
|||
case BB_REFCLK: |
|||
round_rate = ad9361_clk_factor_round_rate(clk_priv, rate, |
|||
&phy->clk_refin->rate); |
|||
ad9361_clk_factor_set_rate(clk_priv, round_rate, |
|||
phy->clk_refin->rate); |
|||
phy->clks[source]->rate = ad9361_clk_factor_recalc_rate(clk_priv, |
|||
phy->clk_refin->rate); |
|||
break; |
|||
case TX_RFPLL_INT: |
|||
case RX_RFPLL_INT: |
|||
round_rate = ad9361_rfpll_int_round_rate(clk_priv, rate, |
|||
&phy->clks[clk_priv->parent_source]->rate); |
|||
ad9361_rfpll_int_set_rate(clk_priv, round_rate, |
|||
phy->clks[clk_priv->parent_source]->rate); |
|||
phy->clks[source]->rate = ad9361_rfpll_int_recalc_rate(clk_priv, |
|||
phy->clks[clk_priv->parent_source]->rate); |
|||
break; |
|||
case RX_RFPLL_DUMMY: |
|||
case TX_RFPLL_DUMMY: |
|||
ad9361_rfpll_dummy_set_rate(clk_priv, rate); |
|||
case TX_RFPLL: |
|||
case RX_RFPLL: |
|||
round_rate = ad9361_rfpll_round_rate(clk_priv, rate); |
|||
ad9361_rfpll_set_rate(clk_priv, round_rate); |
|||
phy->clks[source]->rate = ad9361_rfpll_recalc_rate(clk_priv); |
|||
break; |
|||
case BBPLL_CLK: |
|||
round_rate = ad9361_bbpll_round_rate(clk_priv, rate, |
|||
&phy->clks[clk_priv->parent_source]->rate); |
|||
ad9361_bbpll_set_rate(clk_priv, round_rate, |
|||
phy->clks[clk_priv->parent_source]->rate); |
|||
phy->clks[source]->rate = ad9361_bbpll_recalc_rate(clk_priv, |
|||
phy->clks[clk_priv->parent_source]->rate); |
|||
phy->bbpll_initialized = true; |
|||
break; |
|||
case ADC_CLK: |
|||
case R2_CLK: |
|||
case R1_CLK: |
|||
case CLKRF_CLK: |
|||
case RX_SAMPL_CLK: |
|||
case DAC_CLK: |
|||
case T2_CLK: |
|||
case T1_CLK: |
|||
case CLKTF_CLK: |
|||
case TX_SAMPL_CLK: |
|||
round_rate = ad9361_clk_factor_round_rate(clk_priv, rate, |
|||
&phy->clks[clk_priv->parent_source]->rate); |
|||
ad9361_clk_factor_set_rate(clk_priv, round_rate, |
|||
phy->clks[clk_priv->parent_source]->rate); |
|||
phy->clks[source]->rate = ad9361_clk_factor_recalc_rate(clk_priv, |
|||
phy->clks[clk_priv->parent_source]->rate); |
|||
break; |
|||
default: |
|||
break; |
|||
} |
|||
for(i = BB_REFCLK; i < BBPLL_CLK; i++) |
|||
{ |
|||
phy->clks[i]->rate = ad9361_clk_factor_recalc_rate(phy->ref_clk_scale[i], |
|||
phy->clk_refin->rate); |
|||
} |
|||
phy->clks[BBPLL_CLK]->rate = ad9361_bbpll_recalc_rate(phy->ref_clk_scale[BBPLL_CLK], |
|||
phy->clks[phy->ref_clk_scale[BBPLL_CLK]->parent_source]->rate); |
|||
for(i = ADC_CLK; i < RX_RFPLL_INT; i++) |
|||
{ |
|||
phy->clks[i]->rate = ad9361_clk_factor_recalc_rate(phy->ref_clk_scale[i], |
|||
phy->clks[phy->ref_clk_scale[i]->parent_source]->rate); |
|||
} |
|||
for(i = RX_RFPLL_INT; i < RX_RFPLL_DUMMY; i++) |
|||
{ |
|||
phy->clks[i]->rate = ad9361_rfpll_int_recalc_rate(phy->ref_clk_scale[i], |
|||
phy->clks[phy->ref_clk_scale[i]->parent_source]->rate); |
|||
} |
|||
for(i = RX_RFPLL_DUMMY; i < RX_RFPLL; i++) |
|||
{ |
|||
phy->clks[i]->rate = ad9361_rfpll_dummy_recalc_rate(phy->ref_clk_scale[i]); |
|||
} |
|||
for(i = RX_RFPLL; i < NUM_AD9361_CLKS; i++) |
|||
{ |
|||
phy->clks[i]->rate = ad9361_rfpll_recalc_rate(phy->ref_clk_scale[i]); |
|||
} |
|||
} else { |
|||
if ((source == BBPLL_CLK) && !phy->bbpll_initialized) { |
|||
round_rate = ad9361_bbpll_round_rate(clk_priv, rate, |
|||
&phy->clks[clk_priv->parent_source]->rate); |
|||
ad9361_bbpll_set_rate(clk_priv, round_rate, |
|||
phy->clks[clk_priv->parent_source]->rate); |
|||
phy->clks[source]->rate = ad9361_bbpll_recalc_rate(clk_priv, |
|||
phy->clks[clk_priv->parent_source]->rate); |
|||
phy->bbpll_initialized = true; |
|||
} |
|||
} |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
/***************************************************************************//**
|
|||
* @brief int_sqrt |
|||
*******************************************************************************/ |
|||
uint32_t int_sqrt(uint32_t x) |
|||
{ |
|||
uint32_t b, m, y = 0; |
|||
|
|||
if (x <= 1) |
|||
return x; |
|||
|
|||
m = 1UL << (BITS_PER_LONG - 2); |
|||
while (m != 0) { |
|||
b = y + m; |
|||
y >>= 1; |
|||
|
|||
if (x >= b) { |
|||
x -= b; |
|||
y += m; |
|||
} |
|||
m >>= 2; |
|||
} |
|||
|
|||
return y; |
|||
} |
|||
|
|||
/***************************************************************************//**
|
|||
* @brief ilog2 |
|||
*******************************************************************************/ |
|||
int32_t ilog2(int32_t x) |
|||
{ |
|||
int32_t A = !(!(x >> 16)); |
|||
int32_t count = 0; |
|||
int32_t x_copy = x; |
|||
|
|||
count = count + (A << 4); |
|||
|
|||
x_copy = (((~A + 1) & (x >> 16)) + (~(~A + 1) & x)); |
|||
|
|||
A = !(!(x_copy >> 8)); |
|||
count = count + (A << 3); |
|||
x_copy = (((~A + 1) & (x_copy >> 8)) + (~(~A + 1) & x_copy)); |
|||
|
|||
A = !(!(x_copy >> 4)); |
|||
count = count + (A << 2); |
|||
x_copy = (((~A + 1) & (x_copy >> 4)) + (~(~A + 1) & x_copy)); |
|||
|
|||
A = !(!(x_copy >> 2)); |
|||
count = count + (A << 1); |
|||
x_copy = (((~A + 1) & (x_copy >> 2)) + (~(~A + 1) & x_copy)); |
|||
|
|||
A = !(!(x_copy >> 1)); |
|||
count = count + A; |
|||
|
|||
return count; |
|||
} |
|||
|
|||
/***************************************************************************//**
|
|||
* @brief do_div |
|||
*******************************************************************************/ |
|||
uint64_t do_div(uint64_t* n, uint64_t base) |
|||
{ |
|||
uint64_t mod = 0; |
|||
|
|||
mod = *n % base; |
|||
*n = *n / base; |
|||
|
|||
return mod; |
|||
} |
|||
|
|||
/***************************************************************************//**
|
|||
* @brief find_first_bit |
|||
*******************************************************************************/ |
|||
uint32_t find_first_bit(uint32_t word) |
|||
{ |
|||
int32_t num = 0; |
|||
|
|||
if ((word & 0xffff) == 0) { |
|||
num += 16; |
|||
word >>= 16; |
|||
} |
|||
if ((word & 0xff) == 0) { |
|||
num += 8; |
|||
word >>= 8; |
|||
} |
|||
if ((word & 0xf) == 0) { |
|||
num += 4; |
|||
word >>= 4; |
|||
} |
|||
if ((word & 0x3) == 0) { |
|||
num += 2; |
|||
word >>= 2; |
|||
} |
|||
if ((word & 0x1) == 0) |
|||
num += 1; |
|||
return num; |
|||
} |
|||
|
|||
/***************************************************************************//**
|
|||
* @brief ERR_PTR |
|||
*******************************************************************************/ |
|||
void * ERR_PTR(long error) |
|||
{ |
|||
return (void *) error; |
|||
} |
|||
|
|||
/***************************************************************************//**
|
|||
* @brief zmalloc |
|||
*******************************************************************************/ |
|||
void *zmalloc(size_t size) |
|||
{ |
|||
void *ptr = malloc(size); |
|||
if (ptr) |
|||
memset(ptr, 0, size); |
|||
mdelay(1); |
|||
|
|||
return ptr; |
|||
} |
|||
@ -0,0 +1,135 @@ |
|||
/***************************************************************************//**
|
|||
* @file util.h |
|||
* @brief Header file of Util driver. |
|||
* @author DBogdan (dragos.bogdan@analog.com) |
|||
******************************************************************************** |
|||
* Copyright 2013(c) Analog Devices, Inc. |
|||
* |
|||
* All rights reserved. |
|||
* |
|||
* Redistribution and use in source and binary forms, with or without |
|||
* modification, are permitted provided that the following conditions are met: |
|||
* - Redistributions of source code must retain the above copyright |
|||
* notice, this list of conditions and the following disclaimer. |
|||
* - Redistributions in binary form must reproduce the above copyright |
|||
* notice, this list of conditions and the following disclaimer in |
|||
* the documentation and/or other materials provided with the |
|||
* distribution. |
|||
* - Neither the name of Analog Devices, Inc. nor the names of its |
|||
* contributors may be used to endorse or promote products derived |
|||
* from this software without specific prior written permission. |
|||
* - The use of this software may or may not infringe the patent rights |
|||
* of one or more patent holders. This license does not release you |
|||
* from the requirement that you obtain separate licenses from these |
|||
* patent holders to use this software. |
|||
* - Use of the software either in source or binary form, must be run |
|||
* on or directly connected to an Analog Devices Inc. component. |
|||
* |
|||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR |
|||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, |
|||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
|||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, |
|||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
|||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR |
|||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
|||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
|||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
|||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
|||
*******************************************************************************/ |
|||
#ifndef __NO_OS_PORT_H__ |
|||
#define __NO_OS_PORT_H__ |
|||
|
|||
/******************************************************************************/ |
|||
/***************************** Include Files **********************************/ |
|||
/******************************************************************************/ |
|||
#include <limits.h> |
|||
#include <stdint.h> |
|||
#include <stdio.h> |
|||
#include <stdlib.h> |
|||
#include "ad9361.h" |
|||
#include "common.h" |
|||
#include "config.h" |
|||
|
|||
|
|||
/******************************************************************************/ |
|||
/********************** Macros and Constants Definitions **********************/ |
|||
/******************************************************************************/ |
|||
#define SUCCESS 0 |
|||
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) |
|||
#define min(x, y) (((x) < (y)) ? (x) : (y)) |
|||
#define min_t(type, x, y) (type)min((type)(x), (type)(y)) |
|||
#define max(x, y) (((x) > (y)) ? (x) : (y)) |
|||
#define max_t(type, x, y) (type)max((type)(x), (type)(y)) |
|||
#define clamp(val, min_val, max_val) (max(min((val), (max_val)), (min_val))) |
|||
#define clamp_t(type, val, min_val, max_val) (type)clamp((type)(val), (type)(min_val), (type)(max_val)) |
|||
#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) |
|||
#define DIV_ROUND_CLOSEST(x, divisor) (((x) + (divisor) / 2) / (divisor)) |
|||
#define BIT(x) (1 << (x)) |
|||
#define CLK_IGNORE_UNUSED BIT(3) |
|||
#define CLK_GET_RATE_NOCACHE BIT(6) |
|||
|
|||
#if defined(HAVE_VERBOSE_MESSAGES) |
|||
#define dev_err(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); }) |
|||
#define dev_warn(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); }) |
|||
#if defined(HAVE_DEBUG_MESSAGES) |
|||
#define dev_dbg(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); }) |
|||
#else |
|||
#define dev_dbg(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); }) |
|||
#endif |
|||
#define printk(format, ...) printf(format, ## __VA_ARGS__) |
|||
#else |
|||
#define dev_err(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); }) |
|||
#define dev_warn(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); }) |
|||
#define dev_dbg(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); }) |
|||
#define printk(format, ...) ({ if (0) printf(format, ## __VA_ARGS__); }) |
|||
#endif |
|||
|
|||
struct device { |
|||
}; |
|||
|
|||
struct spi_device { |
|||
struct device dev; |
|||
uint8_t id_no; |
|||
}; |
|||
|
|||
struct axiadc_state { |
|||
struct ad9361_rf_phy *phy; |
|||
uint32_t pcore_version; |
|||
}; |
|||
|
|||
struct axiadc_chip_info { |
|||
char *name; |
|||
int32_t num_channels; |
|||
}; |
|||
|
|||
struct axiadc_converter { |
|||
struct axiadc_chip_info *chip_info; |
|||
uint32_t scratch_reg[16]; |
|||
}; |
|||
|
|||
#ifdef WIN32 |
|||
#include "basetsd.h" |
|||
typedef SSIZE_T ssize_t; |
|||
#define strsep(s, ct) 0 |
|||
#define snprintf(s, n, format, ...) 0 |
|||
#define __func__ __FUNCTION__ |
|||
#endif |
|||
|
|||
/******************************************************************************/ |
|||
/************************ Functions Declarations ******************************/ |
|||
/******************************************************************************/ |
|||
int32_t clk_prepare_enable(struct clk *clk); |
|||
uint32_t clk_get_rate(struct ad9361_rf_phy *phy, |
|||
struct refclk_scale *clk_priv); |
|||
int32_t clk_set_rate(struct ad9361_rf_phy *phy, |
|||
struct refclk_scale *clk_priv, |
|||
uint32_t rate); |
|||
uint32_t int_sqrt(uint32_t x); |
|||
int32_t ilog2(int32_t x); |
|||
uint64_t do_div(uint64_t* n, |
|||
uint64_t base); |
|||
uint32_t find_first_bit(uint32_t word); |
|||
void * ERR_PTR(long error); |
|||
void *zmalloc(size_t size); |
|||
|
|||
#endif |
|||
Loading…
Reference in new issue